+2008-08-28 Paul Brook <paul@codesourcery.com>
+
+ * config/arm/vfp.md: Document fmul{s,d} and fmac{s,d} types.
+ Remove documentation entry for fmul type.
+ Use fmuls to annotate single-precision multiplication patterns,
+ fmuld to annotate double-precision multiplication patterns,
+ fmacs to annotate single-precision multiply-accumulate patterns
+ and fmacd to annotate double-precision multiply-accumulate patterns.
+ * config/arm/vfp11.md: Update reservations accordingly.
+ * config/arm/arm.md: Note that certain values of the "type"
+ attribute are documented in vfp.md.
+ * config/arm/arm1020e.md: Remove out of date duplicate comment.
+ (v10_cvt): Use new fmul types.
+
2008-08-26 Paul Brook <paul@codesourcery.com>
* config/arm/vfp.md: Move pipeline description for VFP11 to...
(eq_attr "fpu" "vfp"))
(const_string "yes") (const_string "no"))))
-;; The VFP "type" attributes differ from those used in the FPA model.
-;; ffarith Fast floating point insns, e.g. abs, neg, cpy, cmp.
-;; farith Most arithmetic insns.
-;; fmul Double precision multiply.
-;; fdivs Single precision sqrt or division.
-;; fdivd Double precision sqrt or division.
-;; f_flag fmstat operation
-;; f_load Floating point load from memory.
-;; f_store Floating point store to memory.
-;; f_2_r Transfer vfp to arm reg.
-;; r_2_f Transfer arm to vfp reg.
-
;; Note, no instruction can issue to the VFP if the core is stalled in the
;; first execute state. We model this by using 1020a_e in the first cycle.
(define_insn_reservation "v10_ffarith" 5
(define_insn_reservation "v10_fmul" 6
(and (eq_attr "vfp10" "yes")
- (eq_attr "type" "fmul"))
+ (eq_attr "type" "fmuls,fmacs,fmuld,fmacd"))
"1020a_e+v10_fmac*2")
(define_insn_reservation "v10_fdivs" 18
;; The VFP "type" attributes differ from those used in the FPA model.
;; ffarith Fast floating point insns, e.g. abs, neg, cpy, cmp.
;; farith Most arithmetic insns.
-;; fmul Double precision multiply.
+;; fmuls Single precision multiply.
+;; fmuld Double precision multiply.
+;; fmacs Single precision multiply-accumulate.
+;; fmacd Double precision multiply-accumulate.
;; fdivs Single precision sqrt or division.
;; fdivd Double precision sqrt or division.
;; f_flag fmstat operation
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"fmuls%?\\t%0, %1, %2"
[(set_attr "predicable" "yes")
- (set_attr "type" "farith")]
+ (set_attr "type" "fmuls")]
)
(define_insn "*muldf3_vfp"
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"fmuld%?\\t%P0, %P1, %P2"
[(set_attr "predicable" "yes")
- (set_attr "type" "fmul")]
+ (set_attr "type" "fmuld")]
)
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"fnmuls%?\\t%0, %1, %2"
[(set_attr "predicable" "yes")
- (set_attr "type" "farith")]
+ (set_attr "type" "fmuls")]
)
(define_insn "*muldf3negdf_vfp"
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"fnmuld%?\\t%P0, %P1, %P2"
[(set_attr "predicable" "yes")
- (set_attr "type" "fmul")]
+ (set_attr "type" "fmuld")]
)
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"fmacs%?\\t%0, %2, %3"
[(set_attr "predicable" "yes")
- (set_attr "type" "farith")]
+ (set_attr "type" "fmacs")]
)
(define_insn "*muldf3adddf_vfp"
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"fmacd%?\\t%P0, %P2, %P3"
[(set_attr "predicable" "yes")
- (set_attr "type" "fmul")]
+ (set_attr "type" "fmacd")]
)
;; 0 = 1 * 2 - 0
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"fmscs%?\\t%0, %2, %3"
[(set_attr "predicable" "yes")
- (set_attr "type" "farith")]
+ (set_attr "type" "fmacs")]
)
(define_insn "*muldf3subdf_vfp"
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"fmscd%?\\t%P0, %P2, %P3"
[(set_attr "predicable" "yes")
- (set_attr "type" "fmul")]
+ (set_attr "type" "fmacd")]
)
;; 0 = -(1 * 2) + 0
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"fnmacs%?\\t%0, %2, %3"
[(set_attr "predicable" "yes")
- (set_attr "type" "farith")]
+ (set_attr "type" "fmacs")]
)
(define_insn "*fmuldf3negdfadddf_vfp"
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"fnmacd%?\\t%P0, %P2, %P3"
[(set_attr "predicable" "yes")
- (set_attr "type" "fmul")]
+ (set_attr "type" "fmacd")]
)
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"fnmscs%?\\t%0, %2, %3"
[(set_attr "predicable" "yes")
- (set_attr "type" "farith")]
+ (set_attr "type" "fmacs")]
)
(define_insn "*muldf3negdfsubdf_vfp"
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
"fnmscd%?\\t%P0, %P2, %P3"
[(set_attr "predicable" "yes")
- (set_attr "type" "fmul")]
+ (set_attr "type" "fmacd")]
)