clk: mediatek: clk-mtk: Add MUX_DIV_GATE macro

On MT8196, some clocks use one register for parent selection and
gating, and a separate register for frequency division. Since composite
clocks can combine a mux, divider, and gate in a single entity, add a
macro to simplify registration of such clocks by combining parent
selection, frequency scaling, and enable control into one definition.

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Laura Nao <laura.nao@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index c381d6a6d908420c26d56909bb24a2adfbdbe600..5417b9264e6df9c5fbc7548dd2d4e150ec50e9a2 100644 (file)
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -175,6 +175,25 @@ struct mtk_composite {
                .flags = 0,                                             \
        }
 
+#define MUX_DIV_GATE(_id, _name, _parents,             \
+               _mux_reg, _mux_shift, _mux_width,       \
+               _div_reg, _div_shift, _div_width,       \
+               _gate_reg, _gate_shift) {               \
+               .id            = _id,                   \
+               .name          = _name,                 \
+               .parent_names  = _parents,              \
+               .num_parents   = ARRAY_SIZE(_parents),  \
+               .mux_reg       = _mux_reg,              \
+               .mux_shift     = _mux_shift,            \
+               .mux_width     = _mux_width,            \
+               .divider_reg   = _div_reg,              \
+               .divider_shift = _div_shift,            \
+               .divider_width = _div_width,            \
+               .gate_reg      = _gate_reg,             \
+               .gate_shift    = _gate_shift,           \
+               .flags         = CLK_SET_RATE_PARENT,   \
+       }
+
 int mtk_clk_register_composites(struct device *dev,
                                const struct mtk_composite *mcs, int num,
                                void __iomem *base, spinlock_t *lock,