amd64_edac: Fix logic to determine channel for F15 M30h processors

commit 9d0e8d8348d54d60005c6c938b87b94648005d1c upstream.

Update current channel selection logic to include F15h, M30h memory
controllers.

Refer F15 M30h BKDG D18F2x110[7:6] (DRAM Controller Select Low)
(Link:http://support.amd.com/TechDocs/49125_15h_Models_30h-3Fh_BKDG.pdf)

Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Link: http://lkml.kernel.org/r/1390338216-3873-1-git-send-email-Aravind.Gopalakrishnan@amd.com
Signed-off-by: Borislav Petkov <bp@suse.de>
Signed-off-by: Jiri Slaby <jslaby@suse.cz>

diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 3c9e4e98c65111a069dcbcc5916cd2e061052938..d43a6202a5c5ba729772a6820250850fb0991560 100644 (file)
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -1238,9 +1238,17 @@ static u8 f15_m30h_determine_channel(struct amd64_pvt *pvt, u64 sys_addr,
        if (num_dcts_intlv == 2) {
                select = (sys_addr >> 8) & 0x3;
                channel = select ? 0x3 : 0;
-       } else if (num_dcts_intlv == 4)
-               channel = (sys_addr >> 8) & 0x7;
-
+       } else if (num_dcts_intlv == 4) {
+               u8 intlv_addr = dct_sel_interleave_addr(pvt);
+               switch (intlv_addr) {
+               case 0x4:
+                       channel = (sys_addr >> 8) & 0x3;
+                       break;
+               case 0x5:
+                       channel = (sys_addr >> 9) & 0x3;
+                       break;
+               }
+       }
        return channel;
 }