drm/i915/vrr: Fix intel_vrr_always_use_vrr_tg()==true on TGL

On TGL the hardware always needs TRANS_VBLANK.VBLANK_START
to be programemd with VACTIVE+SCL. Make it so.

The current way of programming it with crtc_vblank_start only
works for the legacy timing generator, as there the delayed
vblank does happen exactly at VACTIVE+SCL.

But if one tries to change intel_vrr_always_use_vrr_tg() to
always use the VRR timing generator on TGL, crtc_vblank_start
will point to the VRR timing generator's delayed vblank,
which may not match VACTIVE+SCL.

Fortunately the state checker caught the issue right away
when I tried intel_vrr_always_use_vrr_tg()==true on TGL.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20251020185038.4272-2-ville.syrjala@linux.intel.com
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a8b4619de347301aa1fd933a98f87db36d41f8ee..09d3eb422ad4cd6879bd5273dc04fc425cca8c64 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2631,6 +2631,9 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
                 * to make it stand out in register dumps.
                 */
                crtc_vblank_start = 1;
+       } else if (DISPLAY_VER(display) == 12) {
+               /* VBLANK_START - VACTIVE defines SCL on TGL */
+               crtc_vblank_start = crtc_vdisplay + crtc_state->set_context_latency;
        }
 
        if (DISPLAY_VER(display) >= 4)
@@ -2721,6 +2724,9 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc
                 * to make it stand out in register dumps.
                 */
                crtc_vblank_start = 1;
+       } else if (DISPLAY_VER(display) == 12) {
+               /* VBLANK_START - VACTIVE defines SCL on TGL */
+               crtc_vblank_start = crtc_vdisplay + crtc_state->set_context_latency;
        }
 
        /*