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Active aarch64 armv8 - armltd vexpress64 vexpress_aemv8a vexpress_aemv8a:ARM64 David Feng <fenghua@phytium.com.cn>
-Active aarch64 armv8 ultrascale xilinx ultrascale xilinx_ultrascale xilinx_ultrascale:ARM64 Michal Simek <michal.simek@xilinx.com>
+Active aarch64 armv8 zynqmp xilinx zynqmp xilinx_zynqmp xilinx_zynqmp:ARM64 Michal Simek <michal.simek@xilinx.com>
Active arc arc700 - synopsys <none> arcangel4 - Alexey Brodkin <abrodkin@synopsys.com>
Active arc arc700 - synopsys - axs101 - Alexey Brodkin <abrodkin@synopsys.com>
Active arc arc700 - synopsys <none> arcangel4-be - Alexey Brodkin <abrodkin@synopsys.com>
config_reg |= ZYNQ_QSPI_CONFIG_IFMODE_MASK |
ZYNQ_QSPI_CONFIG_MCS_MASK | ZYNQ_QSPI_CONFIG_PCS_MASK |
ZYNQ_QSPI_CONFIG_FW_MASK | ZYNQ_QSPI_CONFIG_MSTREN_MASK;
-#ifndef XILINX_ULTRASCALE
+#ifndef XILINX_ZYNQMP
if (is_dual == SF_DUAL_STACKED_FLASH)
#endif
config_reg |= 0x10;
if (qspi->mode & SPI_CPOL)
config_reg |= ZYNQ_QSPI_CONFIG_CPOL_MASK;
-#ifndef XILINX_ULTRASCALE
+#ifndef XILINX_ZYNQMP
/* Set the clock frequency */
if (zqspi->speed_hz != req_hz) {
baud_rate_val = 0;
int is_dual = -1;
int lower_mio = 0, upper_mio = 0, upper_mio_cs1 = 0;
-#ifndef XILINX_ULTRASCALE
+#ifndef XILINX_ZYNQMP
lower_mio = zynq_slcr_get_mio_pin_status("qspi0");
if (lower_mio == ZYNQ_QSPI_MIO_NUM_QSPI0)
is_dual = SF_SINGLE_FLASH;
return NULL;
}
-#ifndef XILINX_ULTRASCALE
+#ifndef XILINX_ZYNQMP
lqspi_frequency = zynq_clk_get_rate(lqspi_clk);
#endif
if (!lqspi_frequency) {
/*
- * Configuration for Xilinx UltraScale MP
+ * Configuration for Xilinx ZynqMP
* (C) Copyright 2014 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef __XILINX_ULTRASCALE_H
-#define __XILINX_ULTRASCALE_H
+#ifndef __XILINX_ZYNQMP_H
+#define __XILINX_ZYNQMP_H
#define CONFIG_REMAKE_ELF
#define CONFIG_SYS_NO_FLASH
-#define XILINX_ULTRASCALE
+#define XILINX_ZYNQMP
/* Generic Interrupt Controller Definitions */
#define GICD_BASE 0xFD3FF000
#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_IDENT_STRING " Xilinx UltraScale MP"
-#define CONFIG_BOOTP_VCI_STRING "U-boot.armv8.Xilinx_UltraScale_MP"
+#define CONFIG_IDENT_STRING " Xilinx ZynqMP"
+#define CONFIG_BOOTP_VCI_STRING "U-boot.armv8.Xilinx_ZynqMP"
/* Text base on 16MB for now - 0 doesn't work */
#define CONFIG_SYS_TEXT_BASE 0x100000
/* Flat Device Tree Definitions */
#define CONFIG_OF_LIBFDT
-#define CONFIG_DEFAULT_DEVICE_TREE ultrascale
+#define CONFIG_DEFAULT_DEVICE_TREE zynqmp
/* Generic Timer Definitions */
#define COUNTER_FREQUENCY 0x1800000 /* 24MHz */
"bootm 1000000 - 20000000\0"
#define CONFIG_BOOTARGS "console=ttyPS0"
-#define CONFIG_BOOTCOMMAND "echo Hello Xilinx UltraScale MP; run $modeboot"
+#define CONFIG_BOOTCOMMAND "echo Hello Xilinx ZynqMP; run $modeboot"
#define CONFIG_BOOTDELAY 5
#define CONFIG_BOARD_LATE_INIT
/* Monitor Command Prompt */
/* Console I/O Buffer Size */
#define CONFIG_SYS_CBSIZE 512
-#define CONFIG_SYS_PROMPT "UltraScale> "
+#define CONFIG_SYS_PROMPT "ZynqMP> "
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024)
-#endif /* __XILINX_ULTRASCALE_H */
+#endif /* __XILINX_ZYNQMP_H */