]> git.ipfire.org Git - thirdparty/u-boot.git/commitdiff
zynqmp: Rename ultrascale to zynqmp
authorMichal Simek <michal.simek@xilinx.com>
Thu, 12 Jun 2014 04:06:05 +0000 (06:06 +0200)
committerMichal Simek <michal.simek@xilinx.com>
Thu, 12 Jun 2014 04:13:19 +0000 (06:13 +0200)
Ultrascale name won't be used that's why change the name.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arch/arm/cpu/armv8/zynqmp/Makefile [moved from arch/arm/cpu/armv8/ultrascale/Makefile with 100% similarity]
arch/arm/cpu/armv8/zynqmp/clk.c [moved from arch/arm/cpu/armv8/ultrascale/clk.c with 100% similarity]
arch/arm/include/asm/arch-zynqmp/clk.h [moved from arch/arm/include/asm/arch-ultrascale/clk.h with 100% similarity]
arch/arm/include/asm/arch-zynqmp/hardware.h [moved from arch/arm/include/asm/arch-ultrascale/hardware.h with 100% similarity]
arch/arm/include/asm/arch-zynqmp/sys_proto.h [moved from arch/arm/include/asm/arch-ultrascale/sys_proto.h with 100% similarity]
board/xilinx/zynqmp/Makefile [moved from board/xilinx/ultrascale/Makefile with 84% similarity]
board/xilinx/zynqmp/zynqmp.c [moved from board/xilinx/ultrascale/ultrascale.c with 100% similarity]
boards.cfg
drivers/net/zynq_gem.c
drivers/spi/zynq_qspi.c
include/configs/xilinx_zynqmp.h [moved from include/configs/xilinx_ultrascale.h with 90% similarity]

similarity index 84%
rename from board/xilinx/ultrascale/Makefile
rename to board/xilinx/zynqmp/Makefile
index 60fb2effeaece453b45cb280d3088cf4eeff5fee..3fa468acd33385e52971b69ec72ecd4f7161ae13 100644 (file)
@@ -5,4 +5,4 @@
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
-obj-y  := ultrascale.o
+obj-y  := zynqmp.o
index 9164a0baf9f2143e69c1430a0210faaf0b7909b8..ece32290068c4b6d7b71b09c22229cef57051a3a 100644 (file)
@@ -44,7 +44,7 @@
 ###########################################################################################################
 
 Active  aarch64     armv8          -           armltd          vexpress64          vexpress_aemv8a                      vexpress_aemv8a:ARM64                                                                                                             David Feng <fenghua@phytium.com.cn>
-Active  aarch64     armv8          ultrascale  xilinx          ultrascale          xilinx_ultrascale                    xilinx_ultrascale:ARM64                                                                                                           Michal Simek <michal.simek@xilinx.com>
+Active  aarch64     armv8          zynqmp      xilinx          zynqmp              xilinx_zynqmp                        xilinx_zynqmp:ARM64                                                                                                               Michal Simek <michal.simek@xilinx.com>
 Active  arc         arc700         -           synopsys        <none>              arcangel4                            -                                                                                                                                 Alexey Brodkin <abrodkin@synopsys.com>
 Active  arc         arc700         -           synopsys        -                   axs101                               -                                                                                                                                 Alexey Brodkin <abrodkin@synopsys.com>
 Active  arc         arc700         -           synopsys        <none>              arcangel4-be                         -                                                                                                                                 Alexey Brodkin <abrodkin@synopsys.com>
index bdfeafe3fddab7a8e87f1cfc946d46ddc2a73429..fcd9e13d1e2f6323acc8a26b92ca17cfab6a371a 100644 (file)
@@ -510,7 +510,7 @@ int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr,
        memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
 
        /* Align bd_space to 1MB */
-#ifdef __XILINX_ULTRASCALE_H
+#ifdef __XILINX_ZYNQMP_H
        bd_space = memalign(1 << 20, BD_SPACE);
 #else
        bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
index d1d8152bb62aa2e8fdfd004e9dcb982735653117..c24917dc11ec43bccc3dd14536b4047c5a9992fb 100644 (file)
@@ -280,7 +280,7 @@ static void zynq_qspi_init_hw(int is_dual, unsigned int cs)
        config_reg |= ZYNQ_QSPI_CONFIG_IFMODE_MASK |
                ZYNQ_QSPI_CONFIG_MCS_MASK | ZYNQ_QSPI_CONFIG_PCS_MASK |
                ZYNQ_QSPI_CONFIG_FW_MASK | ZYNQ_QSPI_CONFIG_MSTREN_MASK;
-#ifndef XILINX_ULTRASCALE
+#ifndef XILINX_ZYNQMP
        if (is_dual == SF_DUAL_STACKED_FLASH)
 #endif
                config_reg |= 0x10;
@@ -475,7 +475,7 @@ static int zynq_qspi_setup_transfer(struct spi_device *qspi,
        if (qspi->mode & SPI_CPOL)
                config_reg |= ZYNQ_QSPI_CONFIG_CPOL_MASK;
 
-#ifndef XILINX_ULTRASCALE
+#ifndef XILINX_ZYNQMP
        /* Set the clock frequency */
        if (zqspi->speed_hz != req_hz) {
                baud_rate_val = 0;
@@ -833,7 +833,7 @@ static int zynq_qspi_check_is_dual_flash(void)
        int is_dual = -1;
        int lower_mio = 0, upper_mio = 0, upper_mio_cs1 = 0;
 
-#ifndef XILINX_ULTRASCALE
+#ifndef XILINX_ZYNQMP
        lower_mio = zynq_slcr_get_mio_pin_status("qspi0");
        if (lower_mio == ZYNQ_QSPI_MIO_NUM_QSPI0)
                is_dual = SF_SINGLE_FLASH;
@@ -905,7 +905,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
                return NULL;
        }
 
-#ifndef XILINX_ULTRASCALE
+#ifndef XILINX_ZYNQMP
        lqspi_frequency = zynq_clk_get_rate(lqspi_clk);
 #endif
        if (!lqspi_frequency) {
similarity index 90%
rename from include/configs/xilinx_ultrascale.h
rename to include/configs/xilinx_zynqmp.h
index ff1ebe1ce6e085f5d7f906ca1a03720dfe4f881e..2a5ccc966602b64901049a8671cddfdedaafb70c 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * Configuration for Xilinx UltraScale MP
+ * Configuration for Xilinx ZynqMP
  * (C) Copyright 2014 Xilinx, Inc.
  * Michal Simek <michal.simek@xilinx.com>
  *
@@ -8,8 +8,8 @@
  * SPDX-License-Identifier:    GPL-2.0+
  */
 
-#ifndef __XILINX_ULTRASCALE_H
-#define __XILINX_ULTRASCALE_H
+#ifndef __XILINX_ZYNQMP_H
+#define __XILINX_ZYNQMP_H
 
 #define CONFIG_REMAKE_ELF
 
@@ -17,7 +17,7 @@
 
 #define CONFIG_SYS_NO_FLASH
 
-#define XILINX_ULTRASCALE
+#define XILINX_ZYNQMP
 
 /* Generic Interrupt Controller Definitions */
 #define GICD_BASE      0xFD3FF000
@@ -38,8 +38,8 @@
 #define CONFIG_SYS_DCACHE_OFF
 #define CONFIG_SYS_ICACHE_OFF
 
-#define CONFIG_IDENT_STRING            " Xilinx UltraScale MP"
-#define CONFIG_BOOTP_VCI_STRING                "U-boot.armv8.Xilinx_UltraScale_MP"
+#define CONFIG_IDENT_STRING            " Xilinx ZynqMP"
+#define CONFIG_BOOTP_VCI_STRING                "U-boot.armv8.Xilinx_ZynqMP"
 
 /* Text base on 16MB for now - 0 doesn't work */
 #define CONFIG_SYS_TEXT_BASE           0x100000
@@ -48,7 +48,7 @@
 /* Flat Device Tree Definitions */
 #define CONFIG_OF_LIBFDT
 
-#define CONFIG_DEFAULT_DEVICE_TREE     ultrascale
+#define CONFIG_DEFAULT_DEVICE_TREE     zynqmp
 
 /* Generic Timer Definitions */
 #define COUNTER_FREQUENCY              0x1800000 /* 24MHz */
                "bootm 1000000 - 20000000\0"
 
 #define CONFIG_BOOTARGS                "console=ttyPS0"
-#define CONFIG_BOOTCOMMAND     "echo Hello Xilinx UltraScale MP; run $modeboot"
+#define CONFIG_BOOTCOMMAND     "echo Hello Xilinx ZynqMP; run $modeboot"
 #define CONFIG_BOOTDELAY       5
 
 #define CONFIG_BOARD_LATE_INIT
 /* Monitor Command Prompt */
 /* Console I/O Buffer Size */
 #define CONFIG_SYS_CBSIZE              512
-#define CONFIG_SYS_PROMPT              "UltraScale> "
+#define CONFIG_SYS_PROMPT              "ZynqMP> "
 #define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE + \
                                        sizeof(CONFIG_SYS_PROMPT) + 16)
 #define CONFIG_SYS_HUSH_PARSER
 
 #define CONFIG_SYS_BOOTM_LEN   (60 * 1024 * 1024)
 
-#endif /* __XILINX_ULTRASCALE_H */
+#endif /* __XILINX_ZYNQMP_H */