]> git.ipfire.org Git - thirdparty/gcc.git/commitdiff
[ARM/AArch64] Add CRC32 scheduling information to Cortex-A53 and Cortex-A57.
authorKyrylo Tkachov <kyrylo.tkachov@arm.com>
Tue, 5 Aug 2014 10:27:07 +0000 (10:27 +0000)
committerKyrylo Tkachov <ktkachov@gcc.gnu.org>
Tue, 5 Aug 2014 10:27:07 +0000 (10:27 +0000)
* config/arm/cortex-a15.md (cortex_a15_alu_shift): Add crc type
to reservation.
* config/arm/cortex-a53.md (cortex_a53_alu_shift): Likewise.

From-SVN: r213632

gcc/ChangeLog
gcc/config/arm/cortex-a15.md
gcc/config/arm/cortex-a53.md

index b58e7981e999e58f44681312a706899f4db5adf4..2a9d3534341a62d05d8d3cddd762d472a2d6f40e 100644 (file)
@@ -1,3 +1,9 @@
+2014-08-05  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       * config/arm/cortex-a15.md (cortex_a15_alu_shift): Add crc type
+       to reservation.
+       * config/arm/cortex-a53.md (cortex_a53_alu_shift): Likewise.
+
 2014-08-05  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
        * config/arm/arm.md (clzsi2): Set predicable_short_it attr to no.
index f5e01a72dcf5f2817a0f625edc766dc6608ad2f7..520f24a9f04134e60199bbaa881d9a086af9c958 100644 (file)
   "ca15_issue1,(ca15_sx1,ca15_sx1_alu)|(ca15_sx2,ca15_sx2_alu)")
 
 ;; ALU ops with immediate shift
+;; crc is also included here so that appropriate scheduling of CRC32 ARMv8-A
+;; instructions can be performed when tuning for the Cortex-A57 since that
+;; core reuses the Cortex-A15 pipeline description for the moment.
 (define_insn_reservation "cortex_a15_alu_shift" 3
   (and (eq_attr "tune" "cortexa15")
        (eq_attr "type" "extend,\
                         alu_shift_imm,alus_shift_imm,\
-                        logic_shift_imm,logics_shift_imm,\
+                        crc,logic_shift_imm,logics_shift_imm,\
                         mov_shift,mvn_shift"))
   "ca15_issue1,(ca15_sx1,ca15_sx1+ca15_sx1_shf,ca15_sx1_alu)\
               |(ca15_sx2,ca15_sx2+ca15_sx2_shf,ca15_sx2_alu)")
index 6cfdcf27c1cf7bb2b3ce4e804f500a8252aec65e..969ed232be93d8317b409b9be2885018e448abc9 100644 (file)
@@ -84,7 +84,7 @@
 (define_insn_reservation "cortex_a53_alu_shift" 2
   (and (eq_attr "tune" "cortexa53")
        (eq_attr "type" "alu_shift_imm,alus_shift_imm,\
-                        logic_shift_imm,logics_shift_imm,\
+                        crc,logic_shift_imm,logics_shift_imm,\
                         alu_shift_reg,alus_shift_reg,\
                         logic_shift_reg,logics_shift_reg,\
                         extend,mov_shift,mov_shift_reg,\