spi: xilinx_spi: Correct the fifo-depth calculation

Correctly fill the fifo depth by passing correct node in getting
it from device tree. This fixes the issue of hanging in a loop while
reading environment from spi flash during boot up which is caused by
commit "spi: xilinx_spi: Modify transfer logic for quad mode"
(sha1: c638e0e80e5ddfac2999692f4aa824021bf3f196)

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index 7bdf716a1541141a1bdfae1b49abb95581ab7bc9..581cd4dc00264d51955cc65011b2212e26c3694d 100644 (file)
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -343,13 +343,12 @@ static const struct dm_spi_ops xilinx_spi_ops = {
 static int xilinx_spi_ofdata_to_platdata(struct udevice *bus)
 {
        struct xilinx_spi_priv *priv = dev_get_priv(bus);
-       struct udevice *dev = dev_get_parent(bus);
 
        priv->regs = (struct xilinx_spi_regs *)dev_get_addr(bus);
 
        debug("%s: regs=%p\n", __func__, priv->regs);
 
-       priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+       priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
                                          "fifo-size", 0);
 
        return 0;