clk: mediatek: clk-pll: Add set/clr regs for shared PLL enable control

On MT8196, there are set/clr registers to control a shared PLL enable
register. These are intended to prevent different masters from
manipulating the PLLs independently. Add the corresponding en_set_reg
and en_clr_reg fields to the mtk_pll_data structure.

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Laura Nao <laura.nao@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
index ce453e1718e5357e992d590fa174cbd1f061d5e1..49ca25dd54182436a673246d2ae0947f805edb45 100644 (file)
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c
@@ -308,6 +308,10 @@ struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll,
                pll->en_addr = base + data->en_reg;
        else
                pll->en_addr = pll->base_addr + REG_CON0;
+       if (data->en_set_reg)
+               pll->en_set_addr = base + data->en_set_reg;
+       if (data->en_clr_reg)
+               pll->en_clr_addr = base + data->en_clr_reg;
        pll->hw.init = &init;
        pll->data = data;
 

diff --git a/drivers/clk/mediatek/clk-pll.h b/drivers/clk/mediatek/clk-pll.h
index 285c8db958b39e4cd30fe76f41a091806da9839e..c4d06bb1151675f1185570cdd57e2e1505865e0c 100644 (file)
--- a/drivers/clk/mediatek/clk-pll.h
+++ b/drivers/clk/mediatek/clk-pll.h
@@ -47,6 +47,8 @@ struct mtk_pll_data {
        const struct mtk_pll_div_table *div_table;
        const char *parent_name;
        u32 en_reg;
+       u32 en_set_reg;
+       u32 en_clr_reg;
        u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */
        u8 pcw_chg_bit;
 };
@@ -68,6 +70,8 @@ struct mtk_clk_pll {
        void __iomem    *pcw_addr;
        void __iomem    *pcw_chg_addr;
        void __iomem    *en_addr;
+       void __iomem    *en_set_addr;
+       void __iomem    *en_clr_addr;
        const struct mtk_pll_data *data;
 };