compatible = "xiaomi,ax6000", "qcom,ipq5018";
aliases {
- label-mac-device = &dp1;
+ label-mac-device = &gmac0;
led-boot = &led_system_blue;
led-failsafe = &led_system_yellow;
led-running = &led_system_blue;
#address-cells = <1>;
#size-cells = <1>;
- mac_addr_dp1: macaddr@0 {
+ mac_addr_gmac0: macaddr@0 {
reg = <0x0 0x6>;
};
- mac_addr_dp2: macaddr@6 {
+ mac_addr_gmac1: macaddr@6 {
reg = <0x6 0x6>;
};
* =================================================================
*/
-&switch {
+&uniphy0 {
status = "okay";
- switch_mac_mode = <MAC_MODE_SGMII_CHANNEL0>;
-
- qcom,port_phyinfo {
- // MAC0 -> GE Phy --- MDI --- QCA8337 Switch
- port@1 {
- port_id = <1>;
- mdiobus = <&mdio0>;
- phy_address = <7>;
- phy_dac = <0x10 0x10>;
- };
-
- // MAC1 -> Uniphy --- SGMII --- QCA8081
- port@2 {
- port_id = <2>;
- mdiobus = <&mdio1>;
- phy_address = <8>;
- port_mac_sel = "QGMAC_PORT";
- };
- };
+ assigned-clocks = <&uniphy0 UNIPHY_CLK_REF>;
+ assigned-clock-rates = <UNIPHY_REFCLK_50MHZ>;
};
// MAC0 -> GE Phy
-&dp1 {
+&gmac0 {
status = "okay";
- nvmem-cells = <&mac_addr_dp1 0>;
+ nvmem-cells = <&mac_addr_gmac0 0>;
nvmem-cell-names = "mac-address";
};
-// MAC1 ---SGMII---> QCA8081
-&dp2 {
+// MAC1 --- SGMII+ ---> QCA8081
+&gmac1 {
status = "okay";
- label = "wan";
phy-handle = <&qca8081>;
- nvmem-cells = <&mac_addr_dp2 0>;
+ phy-mode = "2500base-x";
+
+ label = "wan";
+
+ nvmem-cells = <&mac_addr_gmac1 0>;
nvmem-cell-names = "mac-address";
};
reg = <4>;
phy-handle = <&qca8337_3>;
phy-mode = "gmii";
- ethernet = <&dp1>;
+ ethernet = <&gmac0>;
};
};
};
};
};
-&switch {
+&uniphy0 {
status = "okay";
- switch_mac_mode = <MAC_MODE_SGMII_CHANNEL0>;
-
- qcom,port_phyinfo {
- // MAC0 -> GE Phy
- port@1 {
- port_id = <1>;
- mdiobus = <&mdio0>;
- phy_address = <7>;
- };
-
- // MAC1 -> Uniphy --- SGMII --- QCA8081
- port@2 {
- port_id = <2>;
- mdiobus = <&mdio1>;
- phy_address = <28>;
- port_mac_sel = "QGMAC_PORT";
- };
- };
+ assigned-clocks = <&uniphy0 UNIPHY_CLK_REF>;
+ assigned-clock-rates = <UNIPHY_REFCLK_50MHZ>;
};
// MAC0 -> GE Phy
-&dp1 {
+&gmac0 {
status = "okay";
label = "lan";
+
nvmem-cells = <&hw_mac_addr 0>;
nvmem-cell-names = "mac-address";
- phy-mode = "sgmii";
};
-// MAC1 ---SGMII---> QCA8081
-&dp2 {
+// MAC1 --- SGMII+ ---> QCA8081
+&gmac1 {
status = "okay";
- label = "wan";
phy-handle = <&qca8081>;
+ phy-mode = "2500base-x";
+
+ label = "wan";
+
nvmem-cells = <&hw_mac_addr 1>;
nvmem-cell-names = "mac-address";
};
};
};
-&switch {
+&uniphy0 {
status = "okay";
- switch_mac_mode = <MAC_MODE_SGMII_CHANNEL0>;
-
- qcom,port_phyinfo {
- // MAC0 -> GE Phy
- port@1 {
- port_id = <1>;
- mdiobus = <&mdio0>;
- phy_address = <7>;
- };
-
- // MAC1 -> Uniphy --- SGMII --- QCA8081
- port@2 {
- port_id = <2>;
- mdiobus = <&mdio1>;
- phy_address = <28>;
- port_mac_sel = "QGMAC_PORT";
- };
- };
+ assigned-clocks = <&uniphy0 UNIPHY_CLK_REF>;
+ assigned-clock-rates = <UNIPHY_REFCLK_50MHZ>;
};
// MAC0 -> GE Phy
-&dp1 {
+&gmac0 {
status = "okay";
label = "lan";
+
nvmem-cells = <&hw_mac_addr 0>;
nvmem-cell-names = "mac-address";
- phy-mode = "sgmii";
};
// MAC1 ---SGMII---> QCA8081
-&dp2 {
+&gmac1 {
status = "okay";
- label = "wan";
phy-handle = <&qca8081>;
+ phy-mode = "2500base-x";
+
+ label = "wan";
+
nvmem-cells = <&hw_mac_addr 1>;
nvmem-cell-names = "mac-address";
};
compatible = "glinet,gl-b3000", "qcom,ipq5018";
aliases {
- ethernet1 = &dp2;
- label-mac-device = &dp2;
+ ethernet1 = &gmac1;
+ label-mac-device = &gmac1;
led-boot = &led_system_blue;
led-failsafe = &led_status_white;
led-running = &led_status_white;
};
};
-&switch {
+&uniphy0 {
status = "okay";
- switch_mac_mode = <MAC_MODE_SGMII_CHANNEL0>;
-
- qcom,port_phyinfo {
- // MAC0 -> GE Phy -> QCA8337 Phy2
- port@1 {
- port_id = <1>;
- mdiobus = <&mdio0>;
- phy_address = <7>;
- };
- // MAC1 ---SGMII---> QCA8337 SerDes
- port@2 {
- port_id = <2>;
- forced-speed = <1000>;
- forced-duplex = <1>;
- };
- };
+ assigned-clocks = <&uniphy0 UNIPHY_CLK_REF>;
+ assigned-clock-rates = <UNIPHY_REFCLK_25MHZ>;
};
// MAC1 ---SGMII---> QCA8337 SerDes
-&dp2 {
+&gmac1 {
status = "okay";
- nvmem-cells = <&macaddr_dp2 0>;
+
+ phy-mode = "sgmii";
+
+ nvmem-cells = <&macaddr_gmac1 0>;
nvmem-cell-names = "mac-address";
fixed-link {
reg = <0>;
label = "cpu";
phy-mode = "sgmii";
- ethernet = <&dp2>;
+ ethernet = <&gmac1>;
qca,sgmii-enable-pll;
fixed-link {
label = "lan1";
phy-handle = <&qca8337_1>;
- nvmem-cells = <&macaddr_dp2 2>;
+ nvmem-cells = <&macaddr_gmac1 2>;
nvmem-cell-names = "mac-address";
};
label = "lan2";
phy-handle = <&qca8337_2>;
- nvmem-cells = <&macaddr_dp2 2>;
+ nvmem-cells = <&macaddr_gmac1 2>;
nvmem-cell-names = "mac-address";
};
};
#address-cells = <1>;
#size-cells = <1>;
- macaddr_dp2: macaddr@0 {
+ macaddr_gmac1: macaddr@0 {
compatible = "mac-base";
#nvmem-cell-cells = <1>;
reg = <0x6 0x6>;
compatible = "cmcc,mr3000d-ci", "qcom,ipq5018";
aliases {
- label-mac-device = <&dp1>;
+ label-mac-device = <&gmac1>;
led-boot = &led_status_red;
led-failsafe = &led_status_green;
* ===============================================================
*/
-&switch {
+&uniphy0 {
status = "okay";
- switch_mac_mode = <MAC_MODE_SGMII_CHANNEL0>;
-
- qcom,port_phyinfo {
- // MAC0 -> GE Phy -> QCA8337 Phy4
- port@1 {
- port_id = <1>;
- mdiobus = <&mdio0>;
- phy_address = <7>;
- };
-
- // MAC1 ---SGMII---> QCA8337 SerDes
- port@2 {
- port_id = <2>;
- mdiobus = <&mdio1>;
- forced-speed = <1000>;
- forced-duplex = <1>;
- };
- };
+ assigned-clocks = <&uniphy0 UNIPHY_CLK_REF>;
+ assigned-clock-rates = <UNIPHY_REFCLK_25MHZ>;
};
// MAC0 -> GE Phy
-&dp1 {
+&gmac0 {
status = "okay";
nvmem-cell-names = "mac-address";
};
// MAC1 -> SGMII
-&dp2 {
+&gmac1 {
status = "okay";
+ phy-mode = "sgmii";
+
nvmem-cell-names = "mac-address";
nvmem-cells = <&macaddr_art_6 (0)>;
port@6 {
reg = <6>;
phy-mode = "sgmii";
- ethernet = <&dp2>;
+ ethernet = <&gmac1>;
qca,sgmii-enable-pll;
fixed-link {
/dts-v1/;
#include "ipq5018.dtsi"
+#include "ipq5018-ess.dtsi"
#include "ipq5018-mx-base.dtsi"
/ {
* ===============================================================
*/
-&switch {
+&uniphy0 {
status = "okay";
- switch_mac_mode = <MAC_MODE_SGMII_CHANNEL0>;
-
- qcom,port_phyinfo {
- // MAC0 -> GE Phy
- port@1 {
- port_id = <1>;
- mdiobus = <&mdio0>;
- phy_address = <7>;
- };
-
- // MAC1 ---SGMII---> QCA8337 SerDes
- port@2 {
- port_id = <2>;
- forced-speed = <1000>;
- forced-duplex = <1>;
- };
- };
+ assigned-clocks = <&uniphy0 UNIPHY_CLK_REF>;
+ assigned-clock-rates = <UNIPHY_REFCLK_25MHZ>;
};
// MAC1 ---SGMII---> QCA8337 SerDes
-&dp2 {
+&gmac1 {
status = "okay";
+ phy-mode = "sgmii";
+
nvmem-cells = <&hw_mac_addr 0>;
nvmem-cell-names = "mac-address";
reg = <6>;
label = "cpu";
phy-mode = "sgmii";
- ethernet = <&dp2>;
+ ethernet = <&gmac1>;
qca,sgmii-enable-pll;
fixed-link {
#include "ipq5018.dtsi"
-#include "ipq5018-ess.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/dts-v1/;
#include "ipq5018.dtsi"
+#include "ipq5018-ess.dtsi"
#include "ipq5018-mx-base.dtsi"
#include "ipq5018-qcn6122.dtsi"
* ===============================================================
*/
-&switch {
+&uniphy0 {
status = "okay";
- switch_mac_mode = <MAC_MODE_SGMII_CHANNEL0>;
-
- qcom,port_phyinfo {
- // MAC0 -> GE Phy -> QCA8337 Phy4
- port@1 {
- port_id = <1>;
- mdiobus = <&mdio0>;
- phy_address = <7>;
- };
-
- // MAC1 ---SGMII---> QCA8337 SerDes
- port@2 {
- port_id = <2>;
- forced-speed = <1000>;
- forced-duplex = <1>;
- };
- };
+ assigned-clocks = <&uniphy0 UNIPHY_CLK_REF>;
+ assigned-clock-rates = <UNIPHY_REFCLK_25MHZ>;
};
// MAC1 ---SGMII---> QCA8337 SerDes
-&dp2 {
+&gmac1 {
status = "okay";
+ phy-mode = "sgmii";
+
nvmem-cells = <&hw_mac_addr 0>;
nvmem-cell-names = "mac-address";
reg = <6>;
label = "cpu";
phy-mode = "sgmii";
- ethernet = <&dp2>;
+ ethernet = <&gmac1>;
qca,sgmii-enable-pll;
fixed-link {
/dts-v1/;
#include "ipq5018.dtsi"
+#include "ipq5018-ess.dtsi"
#include "ipq5018-mx-base.dtsi"
/ {
};
aliases {
- label-mac-device = &dp2;
+ label-mac-device = &gmac1;
};
};
* ===============================================================
*/
-&switch {
+&uniphy0 {
status = "okay";
- switch_mac_mode = <MAC_MODE_SGMII_CHANNEL0>;
-
- qcom,port_phyinfo {
- // MAC0 -> GE Phy -> QCA8337 Phy4
- port@1 {
- port_id = <1>;
- mdiobus = <&mdio0>;
- phy_address = <7>;
- };
-
- // MAC1 ---SGMII---> QCA8337 SerDes
- port@2 {
- port_id = <2>;
- forced-speed = <1000>;
- forced-duplex = <1>;
- };
- };
+ assigned-clocks = <&uniphy0 UNIPHY_CLK_REF>;
+ assigned-clock-rates = <UNIPHY_REFCLK_25MHZ>;
};
// MAC1 ---SGMII---> QCA8337 SerDes
-&dp2 {
+&gmac1 {
status = "okay";
+ phy-mode = "sgmii";
+
nvmem-cells = <&hw_mac_addr 0>;
nvmem-cell-names = "mac-address";
reg = <6>;
label = "cpu";
phy-mode = "sgmii";
- ethernet = <&dp2>;
+ ethernet = <&gmac1>;
qca,sgmii-enable-pll;
fixed-link {
/dts-v1/;
#include "ipq5018.dtsi"
+#include "ipq5018-ess.dtsi"
#include "ipq5018-mx-base.dtsi"
#include "ipq5018-qcn6122.dtsi"
* =================================================================
*/
-&switch {
+&uniphy0 {
status = "okay";
- switch_mac_mode = <MAC_MODE_SGMII_CHANNEL0>;
-
- qcom,port_phyinfo {
- // MAC0 -> GE Phy -> MDI --> RJ45
- port@1 {
- port_id = <1>;
- mdiobus = <&mdio0>;
- phy_address = <7>;
- };
-
- // MAC1 ---SGMII---> MaxLinear PHY -> RJ45
- port@2 {
- port_id = <2>;
- mdiobus = <&mdio1>;
- phy_address = <15>;
- port_mac_sel = "QGMAC_PORT";
- };
- };
+ assigned-clocks = <&uniphy0 UNIPHY_CLK_REF>;
+ assigned-clock-rates = <UNIPHY_REFCLK_50MHZ>;
};
-// MAC0 ---MDI---> IPQ5018 GE PHY
-&dp1 {
+&gmac0 {
status = "okay";
label = "lan";
- phy-handle = <&ge_phy>;
+
nvmem-cells = <&hw_mac_addr 1>;
nvmem-cell-names = "mac-address";
};
-// MAC1 ---SGMII---> MXL Phy
-&dp2 {
+// MAC1 ---SGMII---> QCA8337 SerDes
+&gmac1 {
status = "okay";
- label = "wan";
phy-handle = <&gpy115c>;
+ phy-mode = "sgmii";
+
+ label = "wan";
+
nvmem-cells = <&hw_mac_addr 0>;
nvmem-cell-names = "mac-address";
};
// Maxlinear Ethernet GPY115C
gpy115c: ethernet-phy@f {
compatible = "ethernet-phy-id67c9.df10";
- reg = <15>;
+ reg = <0xf>;
};
};
led-failsafe = &led_lan;
led-running = &led_wan;
led-upgrade = &led_lan;
- label-mac-device = <&dp1>;
+ label-mac-device = <&gmac0>;
};
chosen {
};
};
-&switch {
+&uniphy0 {
status = "okay";
- switch_mac_mode = <MAC_MODE_SGMII_CHANNEL0>;
-
- qcom,port_phyinfo {
- // MAC0 -> GE Phy --- MDI --- QCA8337 Phy4(Port5)
- port@1 {
- port_id = <1>;
- mdiobus = <&mdio0>;
- phy_address = <7>;
- };
-
- // MAC1 -> Uniphy --- SGMII --- QCA8337 SerDes(Port6)
- port@2 {
- port_id = <2>;
- mdiobus = <&mdio1>;
- forced-speed = <1000>;
- forced-duplex = <1>;
- };
- };
+ assigned-clocks = <&uniphy0 UNIPHY_CLK_REF>;
+ assigned-clock-rates = <UNIPHY_REFCLK_25MHZ>;
};
// MAC0 -> GE Phy
-&dp1 {
+&gmac0 {
status = "okay";
nvmem-cells = <&hw_mac_addr 0>;
};
// MAC1 -> SGMII
-&dp2 {
+&gmac1 {
status = "okay";
+ phy-mode = "sgmii";
+
nvmem-cells = <&hw_mac_addr 1>;
nvmem-cell-names = "mac-address";
port@0 {
reg = <0>;
phy-mode = "sgmii";
- ethernet = <&dp2>;
+ ethernet = <&gmac1>;
qca,sgmii-enable-pll;
fixed-link {
reg = <5>;
phy-handle = <&qca8337_4>;
phy-mode = "gmii";
- ethernet = <&dp1>;
+ ethernet = <&gmac0>;
};
};
};
compatible = "xiaomi,redmi-ax5400", "qcom,ipq5018";
aliases {
- label-mac-device = &dp1;
+ label-mac-device = &gmac0;
led-boot = &led_system_blue;
led-failsafe = &led_system_yellow;
led-running = &led_system_blue;
#address-cells = <1>;
#size-cells = <1>;
- mac_addr_dp2: macaddr@0 {
+ mac_addr_gmac1: macaddr@0 {
reg = <0x0 0x6>;
};
- mac_addr_dp1: macaddr@6 {
+ mac_addr_gmac0: macaddr@6 {
reg = <0x6 0x6>;
};
};
* =================================================================
*/
-&switch {
+&uniphy0 {
status = "okay";
- switch_mac_mode = <MAC_MODE_SGMII_CHANNEL0>;
-
- qcom,port_phyinfo {
- // MAC0 -> GE Phy --- MDI --- QCA8337 PHY4
- port@1 {
- port_id = <1>;
- mdiobus = <&mdio0>;
- phy_address = <7>;
- phy_dac = <0x10 0x10>;
- };
-
- // MAC1 -> Uniphy --- SGMII --- QCA8337 MAC6
- port@2 {
- port_id = <2>;
- forced-speed = <1000>;
- forced-duplex = <1>;
- };
- };
+ assigned-clocks = <&uniphy0 UNIPHY_CLK_REF>;
+ assigned-clock-rates = <UNIPHY_REFCLK_25MHZ>;
};
// MAC0 -> GE Phy
-&dp1 {
+&gmac0 {
status = "okay";
- nvmem-cells = <&mac_addr_dp1 0>;
+ nvmem-cells = <&mac_addr_gmac0 0>;
nvmem-cell-names = "mac-address";
};
// MAC1 ---SGMII---> QCA8337
-&dp2 {
+&gmac1 {
status = "okay";
- nvmem-cells = <&mac_addr_dp2 0>;
+ phy-mode = "sgmii";
+
+ nvmem-cells = <&mac_addr_gmac1 0>;
nvmem-cell-names = "mac-address";
fixed-link {
label = "wan";
phy-handle = <&qca8337_0>;
- nvmem-cells = <&mac_addr_dp1 0>;
+ nvmem-cells = <&mac_addr_gmac0 0>;
nvmem-cell-names = "mac-address";
};
reg = <5>;
phy-handle = <&qca8337_4>;
phy-mode = "gmii";
- ethernet = <&dp1>;
+ ethernet = <&gmac0>;
};
port@6 {
reg = <6>;
phy-mode = "sgmii";
- ethernet = <&dp2>;
+ ethernet = <&gmac1>;
qca,sgmii-enable-pll;
fixed-link {
compatible ="zyxel,scr50axe", "qcom,ipq5018";
aliases {
- label-mac-device = &dp2;
+ label-mac-device = &gmac1;
led-boot = &led_power_blue;
led-failsafe = &led_power_red;
led-upgrade = &led_power_green;
};
};
-&switch {
+&uniphy0 {
status = "okay";
- switch_mac_mode = <MAC_MODE_SGMII_CHANNEL0>;
- qcom,port_phyinfo {
-
- port@1 {
- port_id = <1>;
- mdiobus = <&mdio0>;
- phy_address = <7>;
- };
-
- port@2 {
- port_id = <2>;
- forced-speed = <1000>;
- forced-duplex = <1>;
- };
- };
+ assigned-clocks = <&uniphy0 UNIPHY_CLK_REF>;
+ assigned-clock-rates = <UNIPHY_REFCLK_25MHZ>;
};
-&dp1 {
+&gmac0 {
status = "okay";
label = "wan";
+
nvmem-cells = <&macaddr_appsblenv_ethaddr 0>;
nvmem-cell-names = "mac-address";
};
-&dp2 {
+&gmac1 {
status = "okay";
+
+ phy-mode = "sgmii";
+
nvmem-cells = <&macaddr_appsblenv_ethaddr (-4)>;
nvmem-cell-names = "mac-address";
port@6 {
reg = <6>;
phy-mode = "sgmii";
- ethernet = <&dp2>;
+ ethernet = <&gmac1>;
qca,sgmii-enable-pll;
fixed-link {
/dts-v1/;
#include "ipq5018.dtsi"
+#include "ipq5018-ess.dtsi"
#include "ipq5018-mx-base.dtsi"
/ {
* =================================================================
*/
-&switch {
+&uniphy0 {
status = "okay";
- switch_mac_mode = <MAC_MODE_SGMII_CHANNEL0>;
-
- qcom,port_phyinfo {
- // MAC0 -> GE Phy --- MDI --- QCA8337 Switch
- port@1 {
- port_id = <1>;
- mdiobus = <&mdio0>;
- phy_address = <7>;
- phy_dac = <0x10 0x10>;
- };
-
- // MAC1 -> Uniphy --- SGMII --- QCA8081
- port@2 {
- port_id = <2>;
- mdiobus = <&mdio1>;
- phy_address = <28>;
- port_mac_sel = "QGMAC_PORT";
- };
- };
+ assigned-clocks = <&uniphy0 UNIPHY_CLK_REF>;
+ assigned-clock-rates = <UNIPHY_REFCLK_50MHZ>;
};
-// MAC0 -> GE Phy
-&dp1 {
+&gmac0 {
status = "okay";
nvmem-cells = <&hw_mac_addr 0>;
nvmem-cell-names = "mac-address";
};
-// MAC1 ---SGMII---> QCA8081
-&dp2 {
+// MAC1 ---SGMII---> QCA8337 SerDes
+&gmac1 {
status = "okay";
- label = "wan";
phy-handle = <&qca8081>;
+ phy-mode = "2500base-x";
+
+ label = "wan";
+
nvmem-cells = <&hw_mac_addr 0>;
nvmem-cell-names = "mac-address";
};
reg = <5>;
phy-handle = <&qca8337_4>;
phy-mode = "gmii";
- ethernet = <&dp1>;
+ ethernet = <&gmac0>;
};
};
};
led-boot = &led_status_green;
led-failsafe = &led_status_red;
led-upgrade = &led_status_green;
- label-mac-device = <&dp1>;
+ label-mac-device = <&gmac0>;
};
chosen {
};
};
-&switch {
+&uniphy0 {
status = "okay";
- switch_mac_mode = <MAC_MODE_SGMII_CHANNEL0>;
-
- qcom,port_phyinfo {
- port@1 {
- port_id = <1>;
- mdiobus = <&mdio0>;
- phy_address = <7>;
- };
-
- port@2 {
- port_id = <2>;
- forced-speed = <1000>;
- forced-duplex = <1>;
- };
- };
+ assigned-clocks = <&uniphy0 UNIPHY_CLK_REF>;
+ assigned-clock-rates = <UNIPHY_REFCLK_25MHZ>;
};
-&dp1 {
+&gmac0 {
status = "okay";
label = "wan";
+
nvmem-cells = <&macaddr_appsblenv_ethaddr 2>;
nvmem-cell-names = "mac-address";
};
-&dp2 {
+&gmac1 {
status = "okay";
+ phy-mode = "sgmii";
+
nvmem-cells = <&macaddr_appsblenv_ethaddr 0>;
nvmem-cell-names = "mac-address";
port@6 {
reg = <6>;
phy-mode = "sgmii";
- ethernet = <&dp2>;
+ ethernet = <&gmac1>;
qca,sgmii-enable-pll;
fixed-link {
led-failsafe = &led_power_red;
led-running = &led_power_green;
led-upgrade = &led_power_green;
- label-mac-device = <&dp1>;
+ label-mac-device = <&gmac0>;
};
chosen {
};
};
-&switch {
+&uniphy0 {
status = "okay";
- switch_mac_mode = <MAC_MODE_SGMII_CHANNEL0>;
-
- qcom,port_phyinfo {
- port@1 {
- port_id = <1>;
- mdiobus = <&mdio0>;
- phy_address = <7>;
- };
-
- port@2 {
- port_id = <2>;
- forced-speed = <1000>;
- forced-duplex = <1>;
- };
- };
+ assigned-clocks = <&uniphy0 UNIPHY_CLK_REF>;
+ assigned-clock-rates = <UNIPHY_REFCLK_25MHZ>;
};
-&dp1 {
+&gmac0 {
status = "okay";
label = "wan";
+
nvmem-cells = <&macaddr_appsblenv_ethaddr 3>;
nvmem-cell-names = "mac-address";
};
-&dp2 {
+&gmac1 {
status = "okay";
+ phy-mode = "sgmii";
+
nvmem-cells = <&macaddr_appsblenv_ethaddr 0>;
nvmem-cell-names = "mac-address";
port@6 {
reg = <6>;
phy-mode = "sgmii";
- ethernet = <&dp2>;
+ ethernet = <&gmac1>;
qca,sgmii-enable-pll;
fixed-link {
led-failsafe = &led_power_red;
led-running = &led_power_green;
led-upgrade = &led_power_green;
- label-mac-device = <&dp1>;
+ label-mac-device = <&gmac0>;
};
chosen {
};
};
-&switch {
+&uniphy0 {
status = "okay";
- switch_mac_mode = <MAC_MODE_SGMII_CHANNEL0>;
-
- qcom,port_phyinfo {
- port@1 {
- port_id = <1>;
- mdiobus = <&mdio0>;
- phy_address = <7>;
- };
-
- port@2 {
- port_id = <2>;
- forced-speed = <1000>;
- forced-duplex = <1>;
- };
- };
+ assigned-clocks = <&uniphy0 UNIPHY_CLK_REF>;
+ assigned-clock-rates = <UNIPHY_REFCLK_25MHZ>;
};
-&dp1 {
+&gmac0 {
status = "okay";
label = "wan";
nvmem-cell-names = "mac-address";
};
-&dp2 {
+&gmac1 {
status = "okay";
+ phy-mode = "sgmii";
nvmem-cells = <&macaddr_appsblenv_ethaddr 0>;
nvmem-cell-names = "mac-address";
port@6 {
reg = <6>;
phy-mode = "sgmii";
- ethernet = <&dp2>;
+ ethernet = <&gmac1>;
qca,sgmii-enable-pll;
fixed-link {
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-
-#ifndef _DT_BINDINGS_NET_QCOM_IPQ_ESS_H
-#define _DT_BINDINGS_NET_QCOM_IPQ_ESS_H
-
-#define ESS_PORT0 0x1
-#define ESS_PORT1 0x2
-#define ESS_PORT2 0x4
-#define ESS_PORT3 0x8
-#define ESS_PORT4 0x10
-#define ESS_PORT5 0x20
-#define ESS_PORT6 0x40
-#define ESS_PORT7 0x80
-
-/* SSDK MAC/UNIPHY modes */
-#define MAC_MODE_PSGMII 0x0
-#define MAC_MODE_PSGMII_RGMII5 0x1
-#define MAC_MODE_SGMII0_RGMII5 0x2
-#define MAC_MODE_SGMII1_RGMII5 0x3
-#define MAC_MODE_PSGMII_RMII0 0x4
-#define MAC_MODE_PSGMII_RMII1 0x5
-#define MAC_MODE_PSGMII_RMII0_RMII1 0x6
-#define MAC_MODE_PSGMII_RGMII4 0x7
-#define MAC_MODE_SGMII0_RGMII4 0x8
-#define MAC_MODE_SGMII1_RGMII4 0x9
-#define MAC_MODE_SGMII4_RGMII4 0xa
-#define MAC_MODE_QSGMII 0xb
-#define MAC_MODE_SGMII_PLUS 0xc
-#define MAC_MODE_USXGMII 0xd
-#define MAC_MODE_10GBASE_R 0xe
-#define MAC_MODE_SGMII_CHANNEL0 0xf
-#define MAC_MODE_SGMII_CHANNEL1 0x10
-#define MAC_MODE_SGMII_CHANNEL4 0x11
-#define MAC_MODE_RGMII 0x12
-#define MAC_MODE_PSGMII_FIBER 0x13
-#define MAC_MODE_SGMII_FIBER 0x14
-#define MAC_MODE_UQXGMII 0x15
-#define MAC_MODE_UDXGMII 0x16
-#define MAC_MODE_UQXGMII_3CHANNELS 0x17
-#define MAC_MODE_DISABLED 0xff
-
-#endif /* _DT_BINDINGS_NET_QCOM_IPQ_ESS_H */
+# CONFIG_DWMAC_GENERIC is not set
+CONFIG_DWMAC_IPQ5018=y
CONFIG_IPQ_CMN_PLL=y
CONFIG_IPQ_GCC_5018=y
CONFIG_LEDS_PWM=y
CONFIG_NET_DSA_QCA8K=y
CONFIG_NET_DSA_QCA8K_LEDS_SUPPORT=y
CONFIG_NET_DSA_TAG_QCA=y
+CONFIG_PCS_XPCS=y
CONFIG_PHY_QCOM_M31_USB=y
CONFIG_PHY_QCOM_UNIPHY_PCIE_28LP=y
CONFIG_PINCTRL_IPQ5018=y
CONFIG_QCOM_Q6V5_WCSS_SEC=y
CONFIG_QCOM_TMEL_QMP_MAILBOX=y
CONFIG_SPI_QPIC_SNAND=y
+CONFIG_STMMAC_ETH=y
+CONFIG_STMMAC_PLATFORM=y
SUBTARGET:=ipq50xx
BOARDNAME:=Qualcomm Atheros IPQ50xx
-DEFAULT_PACKAGES += kmod-qca-nss-dp
define Target/Description
Build firmware images for Qualcomm Atheros IPQ50xx based boards.
+++ /dev/null
-From ce9e56a436e486690097cfbdda2d0c11b60db4c2 Mon Sep 17 00:00:00 2001
-From: Ziyang Huang <hzyitc@outlook.com>
-Date: Sun, 8 Sep 2024 16:40:12 +0800
-Subject: [PATCH] clk: gcc-ipq5018: refer to UNIPHY rx and tx clk providers by name
-
-QCA-SSDK does not register the output clocks of the onboard uniphy so the
-GCC and DTS can't reference them by their index.
-The SSDK references them by name, so let's change the GCC driver
-accordingly.
-
-Signed-off-by: Ziyang Huang <hzyitc@outlook.com>
-Signed-off-by: George Moussalem <george.moussalem@outlook.com>
----
- drivers/clk/qcom/gcc-ipq5018.c | 16 ++++++++--------
- 1 file changed, 8 insertions(+), 8 deletions(-)
-
---- a/drivers/clk/qcom/gcc-ipq5018.c
-+++ b/drivers/clk/qcom/gcc-ipq5018.c
-@@ -368,8 +368,8 @@ static const struct parent_map gcc_xo_ge
-
- static const struct clk_parent_data gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0[] = {
- { .index = DT_XO },
-- { .index = DT_UNIPHY_RX_CLK },
-- { .index = DT_UNIPHY_TX_CLK },
-+ { .name = "uniphy_gcc_rx", .index = -1 },
-+ { .name = "uniphy_gcc_tx", .index = -1 },
- { .hw = &ubi32_pll.clkr.hw },
- { .hw = &gpll0.clkr.hw },
- };
-@@ -384,8 +384,8 @@ static const struct parent_map gcc_xo_un
-
- static const struct clk_parent_data gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0[] = {
- { .index = DT_XO },
-- { .index = DT_UNIPHY_TX_CLK },
-- { .index = DT_UNIPHY_RX_CLK },
-+ { .name = "uniphy_gcc_tx", .index = -1 },
-+ { .name = "uniphy_gcc_rx", .index = -1 },
- { .hw = &ubi32_pll.clkr.hw },
- { .hw = &gpll0.clkr.hw },
- };
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
-@@ -94,12 +94,6 @@
+@@ -95,12 +95,6 @@
compatible = "operating-points-v2";
opp-shared;