]> git.ipfire.org Git - thirdparty/u-boot.git/commitdiff
rockchip: sdram: Add fallback that fixup DRAM gaps on RK3588
authorJonas Karlman <jonas@kwiboo.se>
Tue, 6 Jan 2026 23:21:51 +0000 (23:21 +0000)
committerKever Yang <kever.yang@rock-chips.com>
Mon, 9 Mar 2026 14:47:15 +0000 (22:47 +0800)
RK3588 has two known memory gaps when using 16+ GiB DRAM,
[0x3fc000000, 0x3fc500000) and [0x3fff00000, 0x400000000).

The vendor TPL blob encodes this information in the DDR_MEM tag data
passed to later boot phases. U-Boot proper will normally use this
information to configure the DRAM banks.

When a DDR_MEM tag cannot be found the fallback is to use the entire
range above 4 GiB. Something that will cause issues when OS try to use
memory from the two known memory gaps.

Add a weak dram init banksize fixup function and implement it for RK3588
to fix issues observed when trying to RAM boot RK3588 boards with 16+
GiB DRAM into Linux.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
arch/arm/mach-rockchip/rk3588/rk3588.c
arch/arm/mach-rockchip/sdram.c

index 55d2caab4fecdf67e15841ace4a4a89b256df3a0..6324c6f12867fcc90dc9a75e0dffbb888f893e9b 100644 (file)
@@ -211,6 +211,33 @@ int arch_cpu_init(void)
 }
 #endif
 
+/*
+ * RK3588 has two known memory gaps when using 16+ GiB DRAM,
+ * [0x3fc000000, 0x3fc500000) and [0x3fff00000, 0x400000000).
+ *
+ * Remove the [0x3fc000000, 0x400000000) range to ensure OS does not
+ * use memory from these gaps when a DDR_MEM tag cannot be found.
+ */
+
+#define DRAM_GAP_START         0x3FC000000
+#define DRAM_GAP_END           0x400000000
+
+int rockchip_dram_init_banksize_fixup(struct bd_info *bd)
+{
+       size_t ram_top = bd->bi_dram[1].start + bd->bi_dram[1].size;
+
+       if (ram_top > DRAM_GAP_START) {
+               bd->bi_dram[1].size = DRAM_GAP_START - bd->bi_dram[1].start;
+
+               if (ram_top > DRAM_GAP_END && CONFIG_NR_DRAM_BANKS > 2) {
+                       bd->bi_dram[2].start = DRAM_GAP_END;
+                       bd->bi_dram[2].size = ram_top - bd->bi_dram[2].start;
+               }
+       }
+
+       return 0;
+}
+
 #define RK3588_OTP_CPU_CODE_OFFSET             0x02
 #define RK3588_OTP_SPECIFICATION_OFFSET                0x06
 
index d560f90e873d02e1a799ab0d7c1e085df0c1c54a..ea0e3621af72471b5922b7b819326b6da4adfe2b 100644 (file)
@@ -289,6 +289,11 @@ static int rockchip_dram_init_banksize(void)
 }
 #endif
 
+__weak int rockchip_dram_init_banksize_fixup(struct bd_info *bd)
+{
+       return 0;
+}
+
 int dram_init_banksize(void)
 {
        size_t ram_top = (unsigned long)(gd->ram_size + CFG_SYS_SDRAM_BASE);
@@ -342,7 +347,7 @@ int dram_init_banksize(void)
 #endif
 #endif
 
-       return 0;
+       return rockchip_dram_init_banksize_fixup(gd->bd);
 }
 
 u8 rockchip_sdram_type(phys_addr_t reg)