arm: armv8: Flush TLB before enabling MMU

Commit 9ebdbbc43e5f ("arm: armv8: invalidate dcache entries on
dcache_enable") broke Apple Silicon machines in certain scenarios.
If the MMU is currently not enabled we need to flush the TLB
before we enable it to prevent stale TLB entries from becoming
active again.  So move the __asm_invalidate_tlb_all() back
immediately before the mmu_setup() call.

Fixes: 9ebdbbc43e5f ("arm: armv8: invalidate dcache entries on dcache_enable")
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>

diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index 0309da6d3971af6f2a349ce0760507765da9af4f..39479df7b21fdd85b8ffea59d7c08985c68396f8 100644 (file)
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -878,15 +878,16 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
 void dcache_enable(void)
 {
        /* The data cache is not active unless the mmu is enabled */
-       if (!mmu_status())
+       if (!mmu_status()) {
+               __asm_invalidate_tlb_all();
                mmu_setup();
+       }
 
        /* Set up page tables only once (it is done also by mmu_setup()) */
        if (!gd->arch.tlb_fillptr)
                setup_all_pgtables();
 
        invalidate_dcache_all();
-       __asm_invalidate_tlb_all();
        set_sctlr(get_sctlr() | CR_C);
 }