--- /dev/null
+From af571133f7ae028ec9b5fdab78f483af13bf28d3 Mon Sep 17 00:00:00 2001
+From: William Qiu <william.qiu@starfivetech.com>
+Date: Fri, 22 Sep 2023 14:28:34 +0800
+Subject: riscv: dts: starfive: add assigned-clock* to limit frquency
+
+From: William Qiu <william.qiu@starfivetech.com>
+
+commit af571133f7ae028ec9b5fdab78f483af13bf28d3 upstream.
+
+In JH7110 SoC, we need to go by-pass mode, so we need add the
+assigned-clock* properties to limit clock frquency.
+
+Signed-off-by: William Qiu <william.qiu@starfivetech.com>
+Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
+Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
+Signed-off-by: WangYuli <wangyuli@uniontech.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
++++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+@@ -204,6 +204,8 @@
+
+ &mmc0 {
+ max-frequency = <100000000>;
++ assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
++ assigned-clock-rates = <50000000>;
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+@@ -220,6 +222,8 @@
+
+ &mmc1 {
+ max-frequency = <100000000>;
++ assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
++ assigned-clock-rates = <50000000>;
+ bus-width = <4>;
+ no-sdio;
+ no-mmc;
cifs-fix-signature-miscalculation.patch
pinctrl-meteorlake-add-arrow-lake-h-u-acpi-id.patch
asoc-meson-axg-card-fix-use-after-free.patch
+riscv-dts-starfive-add-assigned-clock-to-limit-frquency.patch