clk: qcom: dispcc-sc7180: Add missing MDSS resets

The MDSS resets have so far been left undescribed. Fix that.

Fixes: dd3d06622138 ("clk: qcom: Add display clock controller driver for SC7180")
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Tested-by: Val Packett <val@packett.cool> # sc7180-ecs-liva-qc710
Link: https://lore.kernel.org/r/20260120-topic-7180_dispcc_bcr-v1-2-0b1b442156c3@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/drivers/clk/qcom/dispcc-sc7180.c b/drivers/clk/qcom/dispcc-sc7180.c
index ab1a8d419863df28da852a7d3467f09fb5e9d8da..d7e37fbbe87ed3804554f1e55288e88dccf8db05 100644 (file)
--- a/drivers/clk/qcom/dispcc-sc7180.c
+++ b/drivers/clk/qcom/dispcc-sc7180.c
@@ -17,6 +17,7 @@
 #include "clk-regmap-divider.h"
 #include "common.h"
 #include "gdsc.h"
+#include "reset.h"
 
 enum {
        P_BI_TCXO,
@@ -636,6 +637,11 @@ static struct gdsc mdss_gdsc = {
        .flags = HW_CTRL,
 };
 
+static const struct qcom_reset_map disp_cc_sc7180_resets[] = {
+       [DISP_CC_MDSS_CORE_BCR] = { 0x2000 },
+       [DISP_CC_MDSS_RSCC_BCR] = { 0x4000 },
+};
+
 static struct gdsc *disp_cc_sc7180_gdscs[] = {
        [MDSS_GDSC] = &mdss_gdsc,
 };
@@ -687,6 +693,8 @@ static const struct qcom_cc_desc disp_cc_sc7180_desc = {
        .config = &disp_cc_sc7180_regmap_config,
        .clks = disp_cc_sc7180_clocks,
        .num_clks = ARRAY_SIZE(disp_cc_sc7180_clocks),
+       .resets = disp_cc_sc7180_resets,
+       .num_resets = ARRAY_SIZE(disp_cc_sc7180_resets),
        .gdscs = disp_cc_sc7180_gdscs,
        .num_gdscs = ARRAY_SIZE(disp_cc_sc7180_gdscs),
 };