--- /dev/null
+From ebfde1584d9f037b6309fc682c96e22dac7bcb7a Mon Sep 17 00:00:00 2001
+From: Vidya Sagar <vidyas@nvidia.com>
+Date: Mon, 19 Jun 2023 15:56:04 +0530
+Subject: Revert "PCI: tegra194: Enable support for 256 Byte payload"
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Vidya Sagar <vidyas@nvidia.com>
+
+commit ebfde1584d9f037b6309fc682c96e22dac7bcb7a upstream.
+
+After commit 4fb8e46c1bc4 ("PCI: tegra194: Enable support for 256 Byte
+payload"), we initialize MPS=256 for tegra194 Root Ports before enumerating
+the hierarchy.
+
+Consider an Endpoint that supports only MPS=128. In the default situation
+(CONFIG_PCIE_BUS_DEFAULT set and no "pci=pcie_bus_*" parameter), Linux
+tries to configure the MPS of every device to match the upstream bridge.
+If the Endpoint is directly below the Root Port, Linux can reduce the Root
+Port MPS to 128 to match the Endpoint. But if there's a switch in the
+middle, Linux doesn't reduce the Root Port MPS because other devices below
+the switch may already be configured with MPS larger than 128.
+
+This scenario results in uncorrectable Malformed TLP errors if the Root
+Port sends TLPs with payloads larger than 128 bytes. These errors can
+be avoided by using the "pci=pcie_bus_safe" parameter, but it doesn't
+seem to be a good idea to always have this parameter even for basic
+functionality to work.
+
+Revert commit 4fb8e46c1bc4 ("PCI: tegra194: Enable support for 256 Byte
+payload") so the Root Ports default to MPS=128, which all devices
+support.
+
+If peer-to-peer DMA is not required, one can use "pci=pcie_bus_perf" to
+get the benefit of larger MPS settings.
+
+[bhelgaas: commit log; kwilczynski: retain "u16 val_16" declaration at
+the top, add missing acked by tag]
+Fixes: 4fb8e46c1bc4 ("PCI: tegra194: Enable support for 256 Byte payload")
+Link: https://lore.kernel.org/linux-pci/20230619102604.3735001-1-vidyas@nvidia.com
+Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
+Signed-off-by: Krzysztof WilczyĆski <kwilczynski@kernel.org>
+Acked-by: Jon Hunter <jonathanh@nvidia.com>
+Cc: stable@vger.kernel.org # v6.0-rc1+
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/pci/controller/dwc/pcie-tegra194.c | 10 ----------
+ 1 file changed, 10 deletions(-)
+
+--- a/drivers/pci/controller/dwc/pcie-tegra194.c
++++ b/drivers/pci/controller/dwc/pcie-tegra194.c
+@@ -879,11 +879,6 @@ static int tegra_pcie_dw_host_init(struc
+ pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci,
+ PCI_CAP_ID_EXP);
+
+- val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL);
+- val_16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
+- val_16 |= PCI_EXP_DEVCTL_PAYLOAD_256B;
+- dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL, val_16);
+-
+ val = dw_pcie_readl_dbi(pci, PCI_IO_BASE);
+ val &= ~(IO_BASE_IO_DECODE | IO_BASE_IO_DECODE_BIT8);
+ dw_pcie_writel_dbi(pci, PCI_IO_BASE, val);
+@@ -1872,11 +1867,6 @@ static void pex_ep_event_pex_rst_deasser
+ pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci,
+ PCI_CAP_ID_EXP);
+
+- val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL);
+- val_16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
+- val_16 |= PCI_EXP_DEVCTL_PAYLOAD_256B;
+- dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL, val_16);
+-
+ /* Clear Slot Clock Configuration bit if SRNS configuration */
+ if (pcie->enable_srns) {
+ val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +