clk: sunxi-ng: sun5i: Fix mux width for csi clock

Mux for CSI clock is 3 bits, not 2.

Signed-off-by: Priit Laes <plaes@plaes.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

diff --git a/drivers/clk/sunxi-ng/ccu-sun5i.c b/drivers/clk/sunxi-ng/ccu-sun5i.c
index 06edaa523479ca82c81dc052806596707159bea2..5c476f966a7220c468799f5011b9994eb23c3ad4 100644 (file)
--- a/drivers/clk/sunxi-ng/ccu-sun5i.c
+++ b/drivers/clk/sunxi-ng/ccu-sun5i.c
@@ -469,7 +469,7 @@ static const char * const csi_parents[] = { "hosc", "pll-video0", "pll-video1",
 static const u8 csi_table[] = { 0, 1, 2, 5, 6 };
 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_clk, "csi",
                                       csi_parents, csi_table,
-                                      0x134, 0, 5, 24, 2, BIT(31), 0);
+                                      0x134, 0, 5, 24, 3, BIT(31), 0);
 
 static SUNXI_CCU_GATE(ve_clk,          "ve",           "pll-ve",
                      0x13c, BIT(31), CLK_SET_RATE_PARENT);