clk: meson: s4: fix fixed_pll_dco clock

[ Upstream commit c1380adf2e8680a00dedaf1b25c19beadbbe5bbd ]

The fixed_pll_dco output frequency is not accurate,
add frac factor for fixed_pll_dco clk to fix it.

Fixes: 57b55c76aaf1 ("clk: meson: S4: add support for Amlogic S4 SoC peripheral clock controller")
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Link: https://lore.kernel.org/r/20240603-s4_fixedpll-v1-1-2b2a98630841@amlogic.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/clk/meson/s4-pll.c b/drivers/clk/meson/s4-pll.c
index d2650d96400cff2fb3f5633bfeacf5e965c7f92e..707c107a5291830a80ad4c529573982844f15aa9 100644 (file)
--- a/drivers/clk/meson/s4-pll.c
+++ b/drivers/clk/meson/s4-pll.c
@@ -38,6 +38,11 @@ static struct clk_regmap s4_fixed_pll_dco = {
                        .shift   = 0,
                        .width   = 8,
                },
+               .frac = {
+                       .reg_off = ANACTRL_FIXPLL_CTRL1,
+                       .shift   = 0,
+                       .width   = 17,
+               },
                .n = {
                        .reg_off = ANACTRL_FIXPLL_CTRL0,
                        .shift   = 10,