#define ZYNQ_SDHCI_BASEADDR0 0xFF160000
#define ZYNQ_SDHCI_BASEADDR1 0xFF170000
+#define ARASAN_NAND_BASEADDR 0xFF100000
+
#define ZYNQMP_SATA_BASEADDR 0xFD0C0000
#define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000
#define COUNTER_FREQUENCY 4000000
/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 0x400000)
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 0x800000)
/* Serial setup */
#define CONFIG_ZYNQ_SERIAL_UART0
#define CONFIG_ZYNQMP_QSPI
#define CONFIG_ZYNQ_SDHCI0
+#define CONFIG_NAND_ZYNQMP
#define CONFIG_CONS_INDEX 0
#define CONFIG_BAUDRATE 115200
# define CONFIG_CMD_SF
#endif
+/* NAND */
+#ifdef CONFIG_NAND_ZYNQMP
+# define CONFIG_CMD_NAND
+# define CONFIG_CMD_NAND_LOCK_UNLOCK
+# define CONFIG_SYS_MAX_NAND_DEVICE 1
+# define CONFIG_SYS_NAND_SELF_INIT
+# define CONFIG_SYS_NAND_ONFI_DETECTION
+# define CONFIG_MTD_DEVICE
+#endif
+
#if defined(CONFIG_ZYNQ_SDHCI0) || defined(CONFIG_ZYNQ_SDHCI1)
# define CONFIG_MMC
# define CONFIG_GENERIC_MMC