Merge branch 'pci/controller/rzg3s-host'

- Assert (not deassert) resets in probe error path (John Madieu)

- Assert resets in suspend path in reverse order they were deasserted
  during probe (John Madieu)

- Rework inbound window algorithm to prevent mapping more than intended
  region and enforce alignment on size, to prepare for RZ/G3E support (John
  Madieu)

- Fix renesas,r9a08g045s33-pcie 'serr_cor' typo and convert properties from
  'description' to 'const' for better validation (John Madieu)

- Add RZ/G3E to DT binding and to driver (John Madieu)

* pci/controller/rzg3s-host:
  PCI: rzg3s-host: Add support for RZ/G3E PCIe controller
  PCI: rzg3s-host: Add PCIe Gen3 (8.0 GT/s) link speed support
  PCI: rzg3s-host: Explicitly set class code for RZ/G3E compatibility
  PCI: rzg3s-host: Add SoC-specific configuration and initialization callbacks
  PCI: rzg3s-host: Make configuration reset lines optional
  PCI: rzg3s-host: Make SYSC register offsets SoC-specific
  dt-bindings: PCI: renesas,r9a08g045s33-pcie: Document RZ/G3E SoC
  dt-bindings: PCI: renesas,r9a08g045s33-pcie: Fix naming properties
  PCI: rzg3s-host: Rework inbound window algorithm for supporting RZ/G3E SoC
  PCI: rzg3s-host: Reorder reset assertion during suspend
  PCI: rzg3s-host: Fix reset handling in probe error path

# Conflicts:
#	drivers/pci/controller/pcie-rzg3s-host.c

diff --cc drivers/pci/controller/pcie-rzg3s-host.c
index 00a11f98611711c035ab71041486bb37b2bcd5b7,bfc210e696ed2055c6e2059c79d7f6a45eb61ad4..d86e7516dcc296507012544f3db52c3e9a782f6b
--- 1/drivers/pci/controller/pcie-rzg3s-host.c
--- 2/drivers/pci/controller/pcie-rzg3s-host.c
+++ b/drivers/pci/controller/pcie-rzg3s-host.c
@@@ -966,7 -1039,22 +1039,22 @@@ static int rzg3s_pcie_set_max_link_spee
        ls = readw_relaxed(host->pcie + pcie_cap + PCI_EXP_LNKSTA);
        cs2 = readl_relaxed(host->axi + RZG3S_PCI_PCSTAT2);
  
-       switch (pcie_get_link_speed(host->max_link_speed)) {
+       /* Read hardware supported link speed from Link Capabilities Register */
+       lnkcap = readl_relaxed(host->pcie + pcie_cap + PCI_EXP_LNKCAP);
+       hw_max_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, lnkcap);
+ 
+       /*
+        * Use DT max-link-speed only as a limit. If specified and lower
+        * than hardware capability, cap to that value.
+        */
+       if (host->max_link_speed > 0 && host->max_link_speed < hw_max_speed)
+               hw_max_speed = host->max_link_speed;
+ 
 -      switch (pcie_link_speed[hw_max_speed]) {
++      switch (pcie_get_link_speed(hw_max_speed)) {
+       case PCIE_SPEED_8_0GT:
+               max_supported_link_speeds = GENMASK(PCI_EXP_LNKSTA_CLS_8_0GB - 1, 0);
+               link_speed = PCI_EXP_LNKCTL2_TLS_8_0GT;
+               break;
        case PCIE_SPEED_5_0GT:
                max_supported_link_speeds = GENMASK(PCI_EXP_LNKSTA_CLS_5_0GB - 1, 0);
                link_speed = PCI_EXP_LNKCTL2_TLS_5_0GT;