drm/i915/display: Use braces for if-ladder in intel_bw_init_hw()

Looking at the current if-ladder in intel_bw_init_hw(), we see that
Xe2_HPD contains two entries, differing only for ECC memories.  Let's
improve readability by using braces and allowing adding extra conditions
for each case.

v2:
  - Tweaked commit message, since we are not going to add the ECC case
    for Xe3p_LPD anymore.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patch.msgid.link/20251103-xe3p_lpd-basic-enabling-v3-3-00e87b510ae7@intel.com
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 3033c53e61d1906d23ae1b26ac33f764047845ee..1358af209591eca7dc5d43fbfdcaf75f5c23f27e 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -802,29 +802,30 @@ void intel_bw_init_hw(struct intel_display *display)
        if (!HAS_DISPLAY(display))
                return;
 
-       if (DISPLAY_VERx100(display) >= 3002)
+       if (DISPLAY_VERx100(display) >= 3002) {
                tgl_get_bw_info(display, dram_info, &xe3lpd_3002_sa_info);
-       else if (DISPLAY_VER(display) >= 30)
+       } else if (DISPLAY_VER(display) >= 30) {
                tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info);
-       else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx &&
-                dram_info->type == INTEL_DRAM_GDDR_ECC)
-               xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_ecc_sa_info);
-       else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx)
-               xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_sa_info);
-       else if (DISPLAY_VER(display) >= 14)
+       } else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
+               if (dram_info->type == INTEL_DRAM_GDDR_ECC)
+                       xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_ecc_sa_info);
+               else
+                       xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_sa_info);
+       } else if (DISPLAY_VER(display) >= 14) {
                tgl_get_bw_info(display, dram_info, &mtl_sa_info);
-       else if (display->platform.dg2)
+       } else if (display->platform.dg2) {
                dg2_get_bw_info(display);
-       else if (display->platform.alderlake_p)
+       } else if (display->platform.alderlake_p) {
                tgl_get_bw_info(display, dram_info, &adlp_sa_info);
-       else if (display->platform.alderlake_s)
+       } else if (display->platform.alderlake_s) {
                tgl_get_bw_info(display, dram_info, &adls_sa_info);
-       else if (display->platform.rocketlake)
+       } else if (display->platform.rocketlake) {
                tgl_get_bw_info(display, dram_info, &rkl_sa_info);
-       else if (DISPLAY_VER(display) == 12)
+       } else if (DISPLAY_VER(display) == 12) {
                tgl_get_bw_info(display, dram_info, &tgl_sa_info);
-       else if (DISPLAY_VER(display) == 11)
+       } else if (DISPLAY_VER(display) == 11) {
                icl_get_bw_info(display, dram_info, &icl_sa_info);
+       }
 }
 
 static unsigned int intel_bw_num_active_planes(struct intel_display *display,