least.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@3061
demangle/libdemangle.a \
${VG_PLATFORM}/libplatform.a \
${VG_ARCH}/libarch.a \
- ${VG_OS}/libos.a
+ ${VG_OS}/libos.a \
+ @VEX_DIR@/libvex.a
## Test repeated in both arms of the if-then-else because older versions of
## automake don't seem to like having += within an if-then-else.
extern Int VG_(fd_soft_limit);
extern Int VG_(fd_hard_limit);
+/* Vex iropt control */
+extern VexControl VG_(clo_vex_control);
/* Should we stop collecting errors if too many appear? default: YES */
extern Bool VG_(clo_error_limit);
/* Enquire about whether to attach to a debugger at errors? default: NO */
Exports of vg_from_ucode.c
------------------------------------------------------------------ */
-extern UChar* VG_(emit_code) ( UCodeBlock* cb, Int* nbytes, UShort jumps[VG_MAX_JUMPS] );
-
extern void VG_(print_ccall_stats) ( void );
extern void VG_(print_UInstr_histogram) ( void );
Bool VG_(cpu_has_feature)(UInt feat);
-extern Int VG_(disBB) ( UCodeBlock* cb, Addr ip0 );
/* ---------------------------------------------------------------------
Exports of vg_translate.c
------------------------------------------------------------------ */
-/* Expandable arrays of uinstrs. */
-struct _UCodeBlock {
- Addr orig_eip;
- Int used;
- Int size;
- UInstr* instrs;
- Int nextTemp;
-};
-
extern Bool VG_(translate) ( ThreadId tid, Addr orig_addr, Bool debugging );
-extern void VG_(sanity_check_UInstr) ( UInt n, UInstr* u );
-
-extern void VG_(print_reg_alloc_stats) ( void );
/* ---------------------------------------------------------------------
Exports of vg_execontext.c.
#undef GEN_SYSCALL_WRAPPER
// Macros used in syscall wrappers
+/* PRRAn == "pre-register-read-argument"
+ PRRSN == "pre-register-read-syscall"
+*/
#define PRRSN \
TL_(pre_reg_read)(Vg_CoreSysCall, tid, "(syscallno)", \
#define POST_MEM_WRITE(zzaddr, zzlen) \
VG_TRACK( post_mem_write, zzaddr, zzlen)
-
-
-/*--------------------------------------------------------------------*/
-/*--- end vg_syscalls.c ---*/
-/*--------------------------------------------------------------------*/
-
/* ---------------------------------------------------------------------
Exports of vg_transtab.c
------------------------------------------------------------------ */
extern void VG_(init_tt_tc) ( void );
extern void VG_(add_to_trans_tab) ( Addr orig_addr, Int orig_size,
- Addr trans_addr, Int trans_size,
- UShort jumps[VG_MAX_JUMPS]);
+ Addr trans_addr, Int trans_size );
extern Addr VG_(search_transtab) ( Addr original_addr );
extern void VG_(invalidate_translations) ( Addr start, UInt range,
extern void VGA_(load_state) ( arch_thread_t*, ThreadId tid );
extern void VGA_(save_state) ( arch_thread_t*, ThreadId tid );
+// Register state access
+extern void VGA_(set_thread_shadow_archreg) ( ThreadId tid, UInt archreg, UInt val );
+extern UInt VGA_(get_thread_shadow_archreg) ( ThreadId tid, UInt archreg );
+extern UInt VGA_(get_shadow_archreg) ( UInt archreg );
+
// Thread stuff
extern void VGA_(clear_thread) ( arch_thread_t* );
extern void VGA_(init_thread) ( arch_thread_t* );
// Making coredumps
extern void VGA_(fill_elfregs_from_BB) ( struct vki_user_regs_struct* regs );
extern void VGA_(fill_elfregs_from_tst) ( struct vki_user_regs_struct* regs,
- const arch_thread_t* arch );
+ arch_thread_t* arch );
extern void VGA_(fill_elffpregs_from_BB) ( vki_elf_fpregset_t* fpu );
extern void VGA_(fill_elffpregs_from_tst) ( vki_elf_fpregset_t* fpu,
const arch_thread_t* arch );
## always results in the same output, because basic blocks can be
## retranslated. Unless you're doing something really strange...
## 'orig_addr' is the address of the first instruction in the block.
-UCodeBlock*, instrument, UCodeBlock* cb, Addr orig_addr
+IRBB*, instrument, IRBB* bb, VexGuestLayout* layout, IRType hWordTy
## Finish up, print out any results, etc. `exitcode' is program's exit
## code. The shadow (if the `shadow_regs' need is set) can be found with
Bool, handle_client_request, ThreadId tid, UWord* arg_block, UWord* ret
-## ------------------------------------------------------------------
-## VG_(needs).extends_UCode
-
-## 'X' prefix indicates eXtended UCode.
-Int, get_Xreg_usage, UInstr* u, Tag tag, Int* regs, Bool* isWrites
-void, emit_XUInstr, UInstr* u, RRegSet regs_live_before
-Bool, sane_XUInstr, Bool beforeRA, Bool beforeLiveness, UInstr* u
-Char *, name_XUOpcode, Opcode opc
-void, pp_XUInstr, UInstr* u
-
-
## ------------------------------------------------------------------
## VG_(needs).syscall_wrapper
{
if (VG_(is_running_thread)(tid)) {
/* thread currently in baseblock */
- *ip = VG_(baseBlock)[VGOFF_INSTR_PTR];
- *fp = VG_(baseBlock)[VGOFF_FRAME_PTR];
- *sp = VG_(baseBlock)[VGOFF_STACK_PTR];
+ *ip = BASEBLOCK_INSTR_PTR;
+ *fp = BASEBLOCK_FRAME_PTR;
+ *sp = BASEBLOCK_STACK_PTR;
*stack_highest_word = VG_(threads)[tid].stack_highest_word;
} else {
/* thread in thread table */
Addr ret;
if (VG_(is_running_thread)(tid))
- ret = VG_(baseBlock)[VGOFF_INSTR_PTR];
+ ret = BASEBLOCK_INSTR_PTR;
else
ret = ARCH_INSTR_PTR(VG_(threads)[ tid ].arch);
The GNU General Public License is contained in the file COPYING.
*/
-#include "core.h"
-
-
-/*------------------------------------------------------------*/
-/*--- Renamings of frequently-used global functions. ---*/
-/*------------------------------------------------------------*/
-
-#define dis VG_(print_codegen)
-
-/*------------------------------------------------------------*/
-/*--- Instruction emission -- turning final uinstrs back ---*/
-/*--- into x86 code. ---*/
-/*------------------------------------------------------------*/
-
-/* [2001-07-08 This comment is now somewhat out of date.]
-
- This is straightforward but for one thing: to facilitate generating
- code in a single pass, we generate position-independent code. To
- do this, calls and jmps to fixed addresses must specify the address
- by first loading it into a register, and jump to/call that
- register. Fortunately, the only jump to a literal is the jump back
- to vg_dispatch, and only %eax is live then, conveniently. UCode
- call insns may only have a register as target anyway, so there's no
- need to do anything fancy for them.
-
- The emit_* routines constitute the lowest level of instruction
- emission. They simply emit the sequence of bytes corresponding to
- the relevant instruction, with no further ado. In particular there
- is no checking about whether uses of byte registers makes sense,
- nor whether shift insns have their first operand in %cl, etc.
-
- These issues are taken care of by the level above, the synth_*
- routines. These detect impossible operand combinations and turn
- them into sequences of legal instructions. Finally, emitUInstr is
- phrased in terms of the synth_* abstraction layer. */
-
-/* Static state for the current basic block */
-static UChar* emitted_code;
-static Int emitted_code_used;
-static Int emitted_code_size;
-
-/* offset (in bytes into the basic block) */
-static UShort jumps[VG_MAX_JUMPS];
-static Int jumpidx;
-
-static enum _eflags_state {
- UPD_Simd, /* baseblock copy is up to date */
- UPD_Real, /* CPU copy is up to date */
- UPD_Both, /* both are current */
-} eflags_state;
-
-/* ia32 static prediction is very simple. Other implementations are
- more complex, so we get the condition anyway. */
-static JumpPred static_pred(Condcode cond, Int forward)
-{
- if (cond == CondAlways)
- return JP_TAKEN;
-
- return forward ? JP_NOT_TAKEN : JP_TAKEN;
-}
-
-static const Char *predstr(JumpPred p)
-{
- if (!VG_(clo_branchpred))
- return "";
-
- switch(p) {
- default:
- case JP_NONE: return "";
- case JP_TAKEN: return ",pt";
- case JP_NOT_TAKEN: return ",pn";
- }
-}
-
-/* single site for resetting state */
-static void reset_state(void)
-{
- emitted_code_used = 0;
- emitted_code_size = 500; /* reasonable initial size */
- emitted_code = VG_(arena_malloc)(VG_AR_JITTER, emitted_code_size);
- jumpidx = 0;
- eflags_state = UPD_Simd;
-}
-
-
-/* Statistics about C functions called from generated code. */
-static UInt ccalls = 0;
-static UInt ccall_reg_saves = 0;
-static UInt ccall_args = 0;
-static UInt ccall_arg_setup_instrs = 0;
-static UInt ccall_stack_clears = 0;
-static UInt ccall_retvals = 0;
-static UInt ccall_retval_movs = 0;
-
-/* Statistics about frequency of each UInstr */
-typedef
- struct {
- UInt counts;
- UInt size;
- } Histogram;
-
-/* Automatically zeroed because it's static. */
-static Histogram histogram[100];
-
-void VG_(print_ccall_stats)(void)
-{
- VG_(message)(Vg_DebugMsg,
- " ccalls: %u C calls, %u%% saves+restores avoided"
- " (%d bytes)",
- ccalls,
- 100-(UInt)(ccall_reg_saves/(double)(ccalls*3)*100),
- ((ccalls*3) - ccall_reg_saves)*2);
- VG_(message)(Vg_DebugMsg,
- " %u args, avg 0.%d setup instrs each (%d bytes)",
- ccall_args,
- (UInt)(ccall_arg_setup_instrs/(double)ccall_args*100),
- (ccall_args - ccall_arg_setup_instrs)*2);
- VG_(message)(Vg_DebugMsg,
- " %d%% clear the stack (%d bytes)",
- (UInt)(ccall_stack_clears/(double)ccalls*100),
- (ccalls - ccall_stack_clears)*3);
- VG_(message)(Vg_DebugMsg,
- " %u retvals, %u%% of reg-reg movs avoided (%d bytes)",
- ccall_retvals,
- ( ccall_retvals == 0
- ? 100
- : 100-(UInt)(ccall_retval_movs /
- (double)ccall_retvals*100)),
- (ccall_retvals-ccall_retval_movs)*2);
-}
-
-void VG_(print_UInstr_histogram)(void)
-{
- Int i, j;
- UInt total_counts = 0;
- UInt total_size = 0;
-
- for (i = 0; i < 100; i++) {
- total_counts += histogram[i].counts;
- total_size += histogram[i].size;
- }
-
- VG_(printf)("-- UInstr frequencies -----------\n");
- for (i = 0; i < 100; i++) {
- if (0 != histogram[i].counts) {
-
- UInt count_pc =
- (UInt)(histogram[i].counts/(double)total_counts*100 + 0.5);
- UInt size_pc =
- (UInt)(histogram[i].size /(double)total_size *100 + 0.5);
- UInt avg_size =
- (UInt)(histogram[i].size / (double)histogram[i].counts + 0.5);
-
- VG_(printf)("%-7s:%8u (%2u%%), avg %2dB (%2u%%) |",
- VG_(name_UOpcode)(True, i),
- histogram[i].counts, count_pc,
- avg_size, size_pc);
-
- for (j = 0; j < (Int)size_pc; j++) VG_(printf)("O");
- VG_(printf)("\n");
-
- } else {
- vg_assert(0 == histogram[i].size);
- }
- }
-
- VG_(printf)("total UInstrs %u, total size %u\n", total_counts, total_size);
-}
-
-static void expandEmittedCode ( void )
-{
- Int i;
- UChar *tmp = VG_(arena_malloc)(VG_AR_JITTER, 2 * emitted_code_size);
- /* VG_(printf)("expand to %d\n", 2 * emitted_code_size); */
- for (i = 0; i < emitted_code_size; i++)
- tmp[i] = emitted_code[i];
- VG_(arena_free)(VG_AR_JITTER, emitted_code);
- emitted_code = tmp;
- emitted_code_size *= 2;
-}
-
-/* Local calls will be inlined, cross-module ones not */
-__inline__ void VG_(emitB) ( UInt b )
-{
- if (dis) {
- if (b < 16) VG_(printf)("0%x ", b); else VG_(printf)("%2x ", b);
- }
- if (emitted_code_used == emitted_code_size)
- expandEmittedCode();
-
- emitted_code[emitted_code_used] = (UChar)b;
- emitted_code_used++;
-}
-
-__inline__ void VG_(emitW) ( UInt l )
-{
- VG_(emitB) ( (l) & 0x000000FF );
- VG_(emitB) ( (l >> 8) & 0x000000FF );
-}
-
-/* __inline__ */
-void VG_(emitL) ( UInt l )
-{
- VG_(emitB) ( (l) & 0x000000FF );
- VG_(emitB) ( (l >> 8) & 0x000000FF );
- VG_(emitB) ( (l >> 16) & 0x000000FF );
- VG_(emitB) ( (l >> 24) & 0x000000FF );
-}
-
-/* This bit is ORd onto the size to indicate that it's a client
- pointer which needs bounds checking. */
-#define DO_BOUNDSCHECK (1<<8)
-
-/* If the user asks for it, generate bounds checks on application
- pointer dereferences, in the form of a segment override. */
-static __inline__ void boundscheck()
-{
- if (VG_(clo_pointercheck))
- VG_(emitB)(0x64); /* %fs prefix - see vg_dispatch.S */
-}
-
-
-static void emit_get_eflags ( void )
-{
- Int off = 4 * VGOFF_(m_eflags);
- vg_assert(off >= 0 && off < 128);
-
- if (dis)
- VG_(printf)("\t %4d: ", emitted_code_used );
-
- VG_(emitB) ( 0xFF ); /* PUSHL off(%ebp) */
- VG_(emitB) ( 0x75 );
- VG_(emitB) ( off );
- VG_(emitB) ( 0x9D ); /* POPFL */
- if (dis)
- VG_(printf)( "\n\t\tpushl %d(%%ebp) ; popfl\n", off );
-}
-
-static void emit_put_eflags ( void )
-{
- Int off = 4 * VGOFF_(m_eflags);
- vg_assert(off >= 0 && off < 128);
-
- if (dis)
- VG_(printf)("\t %4d: ", emitted_code_used );
-
- VG_(emitB) ( 0x9C ); /* PUSHFL */
- VG_(emitB) ( 0x8F ); /* POPL vg_m_state.m_eflags */
- VG_(emitB) ( 0x45 );
- VG_(emitB) ( off );
- if (dis)
- VG_(printf)( "\n\t\tpushfl ; popl %d(%%ebp)\n", off );
-}
-
-static void maybe_emit_put_eflags( void )
-{
- if (eflags_state == UPD_Real) {
- eflags_state = UPD_Both;
- emit_put_eflags();
- }
-}
-
-
-/* evidently unused */
-#if 0
-static void maybe_emit_get_eflags( void )
-{
- if (eflags_state == UPD_Simd) {
- eflags_state = UPD_Both;
- emit_get_eflags();
- }
-}
-#endif
-
-
-#if 0
-/* begin UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED */
-/* An alternative implementation of new_emit in which the
- state space is explicitly enumerated. */
-__inline__
-void VG_(new_emit) ( Bool upds_simd_flags,
- FlagSet use_flags, FlagSet set_flags )
-{
- Bool simd = upds_simd_flags;
- enum _eflags_state where = eflags_state;
-
- enum { WNone, WSome, WAll } ww;
- Bool rr;
-
-#define DIS_HEADER \
- if (dis) \
- VG_(printf)("\t %4d: ", emitted_code_used );
-
- if (use_flags == FlagsEmpty) {
- rr = False;
- } else {
- rr = True;
- }
-
- if (set_flags == FlagsEmpty) {
- ww = WNone;
- } else
- if (set_flags == FlagsOSZACP) {
- ww = WAll;
- } else {
- ww = WSome;
- }
-
- /* If we're not wanting to interact with simd flags, and the simd
- flags are not in the real flags, then do nothing. */
- if (simd == False && where == UPD_Simd)
- goto noaction;
-
- if (simd == True && where == UPD_Simd && rr == False && ww == WAll) {
- /* We're going to generate a complete new simd flag state without
- consulting the old one first, so just deem this insn to create
- the state in the real flags. */
- eflags_state = UPD_Real;
- DIS_HEADER;
- return;
- }
-
- if (simd == True && where == UPD_Simd && rr == False && ww == WSome) {
- /* Want to partially update the flags state, but is in simd. So
- fetch it first, then declare that the real state is the most
- recent. */
- emit_get_eflags();
- eflags_state = UPD_Real;
- DIS_HEADER;
- return;
- }
-
- if (simd == True && where == UPD_Simd && rr == True && ww == WNone) {
- /* want to read simd flags, but not in real -> copy to real. */
- emit_get_eflags();
- eflags_state = UPD_Both;
- DIS_HEADER;
- return;
- }
-
- if (simd == True && where == UPD_Simd && rr == True && ww == WAll) {
- /* want to read and write simd flags, but not in real -> copy to
- real. State is then Real since they get updated. */
- emit_get_eflags();
- eflags_state = UPD_Real;
- DIS_HEADER;
- return;
- }
-
- if (simd == True && where == UPD_Simd && rr == False && ww == WNone) {
- /* Doesn't really make sense. Want to interact with simd flags,
- but insn doesn't modify them. So don't do anything. ??? */
- goto noaction;
- }
-
- if (simd == True && where == UPD_Real && rr == False && ww == WNone) {
- /* Doesn't really make sense. Want to interact with simd flags,
- but insn doesn't modify them. So don't do anything. ??? */
- goto noaction;
- }
-
- if (simd == True && where == UPD_Real && rr == True && ww == WNone) {
- /* simd is in real. Insn reads real but does not change. --> do
- nothing. */
- goto noaction;
- }
-
- if (simd == True && where == UPD_Real && rr == True && ww == WAll) {
- /* simd is in real. we want to capture changes made by it. -->
- do nothing */
- goto noaction;
- }
-
- if (simd == True && where == UPD_Real && rr == False && ww == WAll) {
- /* simd is in real. Insn creates new simd state. --> leave in
- real */
- goto noaction;
- }
-
- if (simd == True && where == UPD_Both && rr == False && ww == WAll) {
- /* simd is in both. Insn creates new simd state. --> change
- state to Real. */
- narrow_Both_to_Real:
- eflags_state = UPD_Real;
- DIS_HEADER;
- return;
- }
-
- if (simd == True && where == UPD_Both && rr == False && ww == WSome) {
- /* simd is in both. Insn creates partial new simd state. -->
- change state to Real. No need to get, since Both holds. */
- goto narrow_Both_to_Real;
- }
-
- if (simd == True && where == UPD_Real && rr == False && ww == WSome) {
- /* simd is in real. Insn creates new simd state. --> leave in
- real */
- goto noaction;
- }
-
- if (simd == True && where == UPD_Both && rr == True && ww == WNone)
- /* want to read the simd flags, but already have a copy in real,
- and not planning to modify it --> do nothing. */
- goto noaction;
-
- ////////////////
-
- if (simd == False && where == UPD_Real && rr == False && ww == WNone)
- /* simd state is in real, but insn doesn't touch it --> do nothing */
- goto noaction;
-
- if (simd == False && where == UPD_Both && rr == False && ww == WNone)
- /* simd state is in both, insn doesn't touch it --> do nothing */
- goto noaction;
-
- if (simd == False && where == UPD_Both && rr == False && ww == WAll) {
- /* simd state is in both. insn trashes real, therefore declare
- simd state only in simd. */
- narrow_Both_to_Simd:
- eflags_state = UPD_Simd;
- DIS_HEADER;
- return;
- }
-
- if (simd == False && where == UPD_Both && rr == False && ww == WSome) {
- /* simd state is in both. insn trashes real, therefore declare
- simd state only in simd. */
- goto narrow_Both_to_Simd;
- }
-
- if (simd == False && where == UPD_Real && rr == False && ww == WAll) {
- /* simd state is in real; we don't want simd state changed, but
- insn writes the flags. Therefore have to copy back first. */
- put_flags_and_continue:
- emit_put_eflags();
- eflags_state = UPD_Simd;
- DIS_HEADER;
- return;
- }
-
- if (simd == False && where == UPD_Real && rr == False && ww == WSome) {
- /* simd state is in real; we don't want simd state changed, but
- insn writes the flags. Therefore have to copy back first. */
- goto put_flags_and_continue;
- }
-
- goto unhandled;
-
- noaction:
- DIS_HEADER;
- return;
-
- // if (simd == False && where == UPD_Simd && FL_NONE(rrr) && FL_SOME(www)) {
- // return;
- //}
-
- unhandled:
- VG_(printf)("simd %s, where %s, read %s, write %s\n",
- simd ? "True " : "False",
- (eflags_state == UPD_Simd ? "Simd" : (eflags_state == UPD_Real
- ? "Real" : "Both")),
- rr ? "True " : "False",
- ww == WNone ? "None" : ww == WSome ? "Some" : "All "
- );
-
- VG_(core_panic)("new_emit");
-}
-/* end UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED */
-#endif
-
-
-/* Call this before emitting each instruction.
-
- Arguments are:
- interacts_with_simd_flags:
- if true, this instruction wants to interact (read and/or write)
- the simulated %EFLAGS state,
- otherwise it doesn't want to.
- use_flags: set of (real) flags the instruction uses
- set_flags: set of (real) flags the instruction sets
-*/
-void VG_(new_emit) ( Bool interacts_with_simd_flags,
- FlagSet use_flags, FlagSet set_flags )
-{
- Bool use, set;
-
- use = use_flags != FlagsEmpty
- || (set_flags != FlagsEmpty && set_flags != FlagsOSZACP);
- set = set_flags != FlagsEmpty;
-
- if (0)
- VG_(printf)(
- "new_emit: state=%d interacts_with_simd_flags=%d "
- "use_flags=%x set_flags=%x\n",
- eflags_state, interacts_with_simd_flags, use_flags, set_flags);
-
- if (interacts_with_simd_flags) {
- if (use && eflags_state == UPD_Simd) {
- /* we need the CPU flags set, but they're not already */
- eflags_state = UPD_Both;
- emit_get_eflags();
- }
- if (set) {
- /* if we're setting the flags, then the CPU will have the
- only good copy */
- eflags_state = UPD_Real;
- }
- } else {
- /* presume that if non-simd code is using flags, it knows what
- it's doing (ie, it just set up the flags). */
- if (set) {
- /* This instruction is going to trash the flags, so we'd
- better save them away and say that they're only in the
- simulated state. */
- maybe_emit_put_eflags();
- eflags_state = UPD_Simd;
- }
- }
-
- if (dis)
- VG_(printf)("\t %4d: ", emitted_code_used );
-}
-
-
-/*----------------------------------------------------*/
-/*--- Addressing modes ---*/
-/*----------------------------------------------------*/
-
-static __inline__ UChar mkModRegRM ( UChar mod, UChar reg, UChar regmem )
-{
- return ((mod & 3) << 6) | ((reg & 7) << 3) | (regmem & 7);
-}
-
-static __inline__ UChar mkSIB ( Int scale, Int regindex, Int regbase )
-{
- Int shift;
- switch (scale) {
- case 1: shift = 0; break;
- case 2: shift = 1; break;
- case 4: shift = 2; break;
- case 8: shift = 3; break;
- default: VG_(core_panic)( "mkSIB" );
- }
- return ((shift & 3) << 6) | ((regindex & 7) << 3) | (regbase & 7);
-}
-
-static __inline__ void emit_amode_litmem_reg ( Addr addr, Int reg )
-{
- /* ($ADDR), reg */
- VG_(emitB) ( mkModRegRM(0, reg, 5) );
- VG_(emitL) ( addr );
-}
-
-static __inline__ void emit_amode_regmem_reg ( Int regmem, Int reg )
-{
- /* (regmem), reg */
- if (regmem == R_ESP)
- VG_(core_panic)("emit_amode_regmem_reg");
- if (regmem == R_EBP) {
- VG_(emitB) ( mkModRegRM(1, reg, 5) );
- VG_(emitB) ( 0x00 );
- } else {
- VG_(emitB)( mkModRegRM(0, reg, regmem) );
- }
-}
-
-void VG_(emit_amode_offregmem_reg) ( Int off, Int regmem, Int reg )
-{
- if (regmem == R_ESP)
- VG_(core_panic)("emit_amode_offregmem_reg(ESP)");
- if (off < -128 || off > 127) {
- /* Use a large offset */
- /* d32(regmem), reg */
- VG_(emitB) ( mkModRegRM(2, reg, regmem) );
- VG_(emitL) ( off );
- } else {
- /* d8(regmem), reg */
- VG_(emitB) ( mkModRegRM(1, reg, regmem) );
- VG_(emitB) ( off & 0xFF );
- }
-}
-
-static __inline__ void emit_amode_sib_reg ( Int off, Int scale, Int regbase,
- Int regindex, Int reg )
-{
- if (regindex == R_ESP)
- VG_(core_panic)("emit_amode_sib_reg(ESP)");
- if (off < -128 || off > 127) {
- /* Use a 32-bit offset */
- VG_(emitB) ( mkModRegRM(2, reg, 4) ); /* SIB with 32-bit displacement */
- VG_(emitB) ( mkSIB( scale, regindex, regbase ) );
- VG_(emitL) ( off );
- } else {
- /* Use an 8-bit offset */
- VG_(emitB) ( mkModRegRM(1, reg, 4) ); /* SIB with 8-bit displacement */
- VG_(emitB) ( mkSIB( scale, regindex, regbase ) );
- VG_(emitB) ( off & 0xFF );
- }
-}
-
-void VG_(emit_amode_ereg_greg) ( Int e_reg, Int g_reg )
-{
- /* other_reg, reg */
- VG_(emitB) ( mkModRegRM(3, g_reg, e_reg) );
-}
-
-static __inline__ void emit_amode_greg_ereg ( Int g_reg, Int e_reg )
-{
- /* other_reg, reg */
- VG_(emitB) ( mkModRegRM(3, g_reg, e_reg) );
-}
-
-
-/*----------------------------------------------------*/
-/*--- Opcode translation ---*/
-/*----------------------------------------------------*/
-
-static __inline__ Int mkGrp1opcode ( Opcode opc )
-{
- switch (opc) {
- case ADD: return 0;
- case OR: return 1;
- case ADC: return 2;
- case SBB: return 3;
- case AND: return 4;
- case SUB: return 5;
- case XOR: return 6;
- default: VG_(core_panic)("mkGrp1opcode");
- }
-}
-
-static __inline__ FlagSet nonshiftop_use(Opcode opc)
-{
- switch(opc) {
- case ADC:
- case SBB:
- return FlagC;
-
- case ADD:
- case OR:
- case AND:
- case SUB:
- case XOR:
- return FlagsEmpty;
-
- default:
- VG_(core_panic)("nonshiftop_use");
- }
-}
-
-static __inline__ FlagSet nonshiftop_set(Opcode opc)
-{
- switch(opc) {
- case ADC:
- case SBB:
- case ADD:
- case OR:
- case AND:
- case SUB:
- case XOR:
- return FlagsOSZACP;
-
- default:
- VG_(core_panic)("nonshiftop_set");
- }
-}
-
-static __inline__ Int mkGrp2opcode ( Opcode opc )
-{
- switch (opc) {
- case ROL: return 0;
- case ROR: return 1;
- case RCL: return 2;
- case RCR: return 3;
- case SHL: return 4;
- case SHR: return 5;
- case SAR: return 7;
- default: VG_(core_panic)("mkGrp2opcode");
- }
-}
-
-static __inline__ FlagSet shiftop_use(Opcode opc)
-{
- switch(opc) {
- case ROR:
- case ROL:
- case SHL:
- case SHR:
- case SAR:
- return FlagsEmpty;
-
- case RCL:
- case RCR:
- return FlagC;
-
- default:
- VG_(core_panic)("shiftop_use");
- }
-}
-
-static __inline__ FlagSet shiftop_set(Opcode opc)
-{
- switch(opc) {
- case ROR:
- case ROL:
- case RCL:
- case RCR:
- return FlagsOC;
-
- case SHL:
- case SHR:
- case SAR:
- return FlagsOSZACP;
-
- default:
- VG_(core_panic)("shiftop_set");
- }
-}
-
-static __inline__ Int mkGrp3opcode ( Opcode opc )
-{
- switch (opc) {
- case NOT: return 2;
- case NEG: return 3;
- default: VG_(core_panic)("mkGrp3opcode");
- }
-}
-
-static __inline__ Int mkGrp4opcode ( Opcode opc )
-{
- switch (opc) {
- case INC: return 0;
- case DEC: return 1;
- default: VG_(core_panic)("mkGrp4opcode");
- }
-}
-
-static __inline__ Int mkGrp5opcode ( Opcode opc )
-{
- switch (opc) {
- case CALLM: return 2;
- case JMP: return 4;
- default: VG_(core_panic)("mkGrp5opcode");
- }
-}
-
-static __inline__ UChar mkPrimaryOpcode ( Opcode opc )
-{
- switch (opc) {
- case ADD: return 0x00;
- case ADC: return 0x10;
- case AND: return 0x20;
- case XOR: return 0x30;
- case OR: return 0x08;
- case SBB: return 0x18;
- case SUB: return 0x28;
- default: VG_(core_panic)("mkPrimaryOpcode");
- }
-}
-
-/*----------------------------------------------------*/
-/*--- v-size (4, or 2 with OSO) insn emitters ---*/
-/*----------------------------------------------------*/
-
-void VG_(emit_movv_offregmem_reg) ( Int sz, Int off, Int areg, Int reg )
-{
- VG_(new_emit)(False, FlagsEmpty, FlagsEmpty);
- if (sz == 2) VG_(emitB) ( 0x66 );
- VG_(emitB) ( 0x8B ); /* MOV Ev, Gv */
- VG_(emit_amode_offregmem_reg) ( off, areg, reg );
- if (dis)
- VG_(printf)( "\n\t\tmov%c\t0x%x(%s), %s\n",
- nameISize(sz), off, nameIReg(4,areg), nameIReg(sz,reg));
-}
-
-void VG_(emit_movv_reg_offregmem) ( Int sz, Int reg, Int off, Int areg )
-{
- VG_(new_emit)(False, FlagsEmpty, FlagsEmpty);
-
- if (sz & DO_BOUNDSCHECK) {
- boundscheck();
- sz &= ~DO_BOUNDSCHECK;
- }
-
- if (sz == 2) VG_(emitB) ( 0x66 );
- VG_(emitB) ( 0x89 ); /* MOV Gv, Ev */
- VG_(emit_amode_offregmem_reg) ( off, areg, reg );
- if (dis)
- VG_(printf)( "\n\t\tmov%c\t%s, 0x%x(%s)\n",
- nameISize(sz), nameIReg(sz,reg), off, nameIReg(4,areg));
-}
-
-static void emit_movv_regmem_reg ( Int sz, Int reg1, Int reg2 )
-{
- VG_(new_emit)(False, FlagsEmpty, FlagsEmpty);
-
- if (sz & DO_BOUNDSCHECK) {
- boundscheck();
- sz &= ~DO_BOUNDSCHECK;
- }
-
- if (sz == 2) VG_(emitB) ( 0x66 );
- VG_(emitB) ( 0x8B ); /* MOV Ev, Gv */
- emit_amode_regmem_reg ( reg1, reg2 );
- if (dis)
- VG_(printf)( "\n\t\tmov%c\t(%s), %s\n",
- nameISize(sz), nameIReg(4,reg1), nameIReg(sz,reg2));
-}
-
-static void emit_movv_reg_regmem ( Int sz, Int reg1, Int reg2 )
-{
- VG_(new_emit)(False, FlagsEmpty, FlagsEmpty);
-
- if (sz & DO_BOUNDSCHECK) {
- boundscheck();
- sz &= ~DO_BOUNDSCHECK;
- }
-
- if (sz == 2) VG_(emitB) ( 0x66 );
- VG_(emitB) ( 0x89 ); /* MOV Gv, Ev */
- emit_amode_regmem_reg ( reg2, reg1 );
- if (dis)
- VG_(printf)( "\n\t\tmov%c\t%s, (%s)\n",
- nameISize(sz), nameIReg(sz,reg1), nameIReg(4,reg2));
-}
-
-void VG_(emit_movv_reg_reg) ( Int sz, Int reg1, Int reg2 )
-{
- VG_(new_emit)(False, FlagsEmpty, FlagsEmpty);
- if (sz == 2) VG_(emitB) ( 0x66 );
- VG_(emitB) ( 0x89 ); /* MOV Gv, Ev */
- VG_(emit_amode_ereg_greg) ( reg2, reg1 );
- if (dis)
- VG_(printf)( "\n\t\tmov%c\t%s, %s\n",
- nameISize(sz), nameIReg(sz,reg1), nameIReg(sz,reg2));
-}
-
-void VG_(emit_nonshiftopv_lit_reg) ( Bool simd_flags,
- Int sz, Opcode opc,
- UInt lit, Int reg )
-{
- VG_(new_emit)(simd_flags, nonshiftop_use(opc), nonshiftop_set(opc));
-
- if (sz == 2) VG_(emitB) ( 0x66 );
- if (lit == VG_(extend_s_8to32)(lit & 0x000000FF)) {
- /* short form OK */
- VG_(emitB) ( 0x83 ); /* Grp1 Ib,Ev */
- VG_(emit_amode_ereg_greg) ( reg, mkGrp1opcode(opc) );
- VG_(emitB) ( lit & 0x000000FF );
- } else {
- VG_(emitB) ( 0x81 ); /* Grp1 Iv,Ev */
- VG_(emit_amode_ereg_greg) ( reg, mkGrp1opcode(opc) );
- if (sz == 2) VG_(emitW) ( lit ); else VG_(emitL) ( lit );
- }
- if (dis)
- VG_(printf)( "\n\t\t%s%c\t$0x%x, %s\n",
- VG_(name_UOpcode)(False,opc), nameISize(sz),
- lit, nameIReg(sz,reg));
-}
-
-void VG_(emit_nonshiftopv_lit_offregmem) ( Bool simd_flags, Int sz,
- Opcode opc, UInt lit,
- Int off, Int regmem )
-{
- VG_(new_emit)(simd_flags, nonshiftop_use(opc), nonshiftop_set(opc));
- if (sz == 2) VG_(emitB) ( 0x66 );
- if (lit == VG_(extend_s_8to32)(lit & 0x000000FF)) {
- /* short form OK */
- VG_(emitB) ( 0x83 ); /* Grp1 Ib,Ev */
- VG_(emit_amode_offregmem_reg) ( off, regmem, mkGrp1opcode(opc) );
- VG_(emitB) ( lit & 0x000000FF );
- } else {
- VG_(emitB) ( 0x81 ); /* Grp1 Iv,Ev */
- VG_(emit_amode_offregmem_reg) ( off, regmem, mkGrp1opcode(opc) );
- if (sz == 2) VG_(emitW) ( lit ); else VG_(emitL) ( lit );
- }
- if (dis)
- VG_(printf)( "\n\t\t%s%c\t$0x%x, 0x%x(%s)\n",
- VG_(name_UOpcode)(False,opc), nameISize(sz),
- lit, off, nameIReg(sz,regmem));
-}
-
-void VG_(emit_shiftopv_lit_reg) ( Bool simd_flags,
- Int sz, Opcode opc,
- UInt lit, Int reg )
-{
- VG_(new_emit)(simd_flags, shiftop_use(opc), shiftop_set(opc));
-
- if (sz == 2) VG_(emitB) ( 0x66 );
- VG_(emitB) ( 0xC1 ); /* Grp2 Ib,Ev */
- VG_(emit_amode_ereg_greg) ( reg, mkGrp2opcode(opc) );
- VG_(emitB) ( lit );
- if (dis)
- VG_(printf)( "\n\t\t%s%c\t$%d, %s\n",
- VG_(name_UOpcode)(False,opc), nameISize(sz),
- lit, nameIReg(sz,reg));
-}
-
-static void emit_shiftopv_cl_stack0 ( Bool simd_flags, Int sz, Opcode opc )
-{
- VG_(new_emit)(simd_flags, shiftop_use(opc), shiftop_set(opc));
- if (sz == 2) VG_(emitB) ( 0x66 );
- VG_(emitB) ( 0xD3 ); /* Grp2 CL,Ev */
- VG_(emitB) ( mkModRegRM ( 1, mkGrp2opcode(opc), 4 ) );
- VG_(emitB) ( 0x24 ); /* a SIB, I think `d8(%esp)' */
- VG_(emitB) ( 0x00 ); /* the d8 displacement */
- if (dis)
- VG_(printf)("\n\t\t%s%c %%cl, 0(%%esp)\n",
- VG_(name_UOpcode)(False,opc), nameISize(sz) );
-}
-
-static void emit_shiftopb_cl_stack0 ( Bool simd_flags, Opcode opc )
-{
- VG_(new_emit)(simd_flags, shiftop_use(opc), shiftop_set(opc));
- VG_(emitB) ( 0xD2 ); /* Grp2 CL,Eb */
- VG_(emitB) ( mkModRegRM ( 1, mkGrp2opcode(opc), 4 ) );
- VG_(emitB) ( 0x24 ); /* a SIB, I think `d8(%esp)' */
- VG_(emitB) ( 0x00 ); /* the d8 displacement */
- if (dis)
- VG_(printf)("\n\t\t%s%c %%cl, 0(%%esp)\n",
- VG_(name_UOpcode)(False,opc), nameISize(1) );
-}
-
-static void emit_nonshiftopv_offregmem_reg ( Bool simd_flags, Int sz,
- Opcode opc,
- Int off, Int areg, Int reg )
-{
- VG_(new_emit)(simd_flags, nonshiftop_use(opc), nonshiftop_set(opc));
- if (sz == 2) VG_(emitB) ( 0x66 );
- VG_(emitB) ( 3 + mkPrimaryOpcode(opc) ); /* op Ev, Gv */
- VG_(emit_amode_offregmem_reg) ( off, areg, reg );
- if (dis)
- VG_(printf)( "\n\t\t%s%c\t0x%x(%s), %s\n",
- VG_(name_UOpcode)(False,opc), nameISize(sz),
- off, nameIReg(4,areg), nameIReg(sz,reg));
-}
-
-#if 0
-/* evidently unused */
-static void emit_nonshiftopv_reg_offregmem ( Bool simd_flags, Int sz, Opcode opc,
- Int off, Int areg, Int reg )
-{
- VG_(new_emit)(simd_flags, nonshiftop_use(opc), nonshiftop_set(opc));
- if (sz == 2) VG_(emitB) ( 0x66 );
- VG_(emitB) ( 1 + mkPrimaryOpcode(opc) ); /* op Gv, Ev */
- VG_(emit_amode_offregmem_reg) ( off, areg, reg );
- if (dis)
- VG_(printf)( "\n\t\t%s%c\t0x%s, %x(%s),\n",
- VG_(name_UOpcode)(False,opc), nameISize(sz),
- nameIReg(sz,reg), off, nameIReg(4,areg));
-}
-#endif
-
-void VG_(emit_nonshiftopv_reg_reg) ( Bool simd_flags, Int sz, Opcode opc,
- Int reg1, Int reg2 )
-{
- VG_(new_emit)(simd_flags, nonshiftop_use(opc), nonshiftop_set(opc));
- if (sz == 2) VG_(emitB) ( 0x66 );
-# if 0
- /* Perfectly correct, but the GNU assembler uses the other form.
- Therefore we too use the other form, to aid verification. */
- VG_(emitB) ( 3 + mkPrimaryOpcode(opc) ); /* op Ev, Gv */
- VG_(emit_amode_ereg_greg) ( reg1, reg2 );
-# else
- VG_(emitB) ( 1 + mkPrimaryOpcode(opc) ); /* op Gv, Ev */
- emit_amode_greg_ereg ( reg1, reg2 );
-# endif
- if (dis)
- VG_(printf)( "\n\t\t%s%c\t%s, %s\n",
- VG_(name_UOpcode)(False,opc), nameISize(sz),
- nameIReg(sz,reg1), nameIReg(sz,reg2));
-}
-
-void VG_(emit_movv_lit_reg) ( Int sz, UInt lit, Int reg )
-{
-#if 0
- if (lit == 0 && eflags_state != UPD_Real) {
- /* Only emit this for zeroing if it won't stomp flags */
- VG_(emit_nonshiftopv_reg_reg) ( False, sz, XOR, reg, reg );
- return;
- }
-#endif
- VG_(new_emit)(False, FlagsEmpty, FlagsEmpty);
- if (sz == 2) VG_(emitB) ( 0x66 );
- VG_(emitB) ( 0xB8+reg ); /* MOV imm, Gv */
- if (sz == 2) VG_(emitW) ( lit ); else VG_(emitL) ( lit );
- if (dis)
- VG_(printf)( "\n\t\tmov%c\t$0x%x, %s\n",
- nameISize(sz), lit, nameIReg(sz,reg));
-}
-
-void VG_(emit_unaryopv_reg) ( Bool simd_flags, Int sz, Opcode opc, Int reg )
-{
- switch (opc) {
- case NEG:
- VG_(new_emit)(simd_flags, FlagsEmpty, FlagsOSZACP);
- if (sz == 2) VG_(emitB) ( 0x66 );
- VG_(emitB) ( 0xF7 );
- VG_(emit_amode_ereg_greg) ( reg, mkGrp3opcode(NEG) );
- if (dis)
- VG_(printf)( "\n\t\tneg%c\t%s\n",
- nameISize(sz), nameIReg(sz,reg));
- break;
- case NOT:
- VG_(new_emit)(simd_flags, FlagsEmpty, FlagsEmpty);
- if (sz == 2) VG_(emitB) ( 0x66 );
- VG_(emitB) ( 0xF7 );
- VG_(emit_amode_ereg_greg) ( reg, mkGrp3opcode(NOT) );
- if (dis)
- VG_(printf)( "\n\t\tnot%c\t%s\n",
- nameISize(sz), nameIReg(sz,reg));
- break;
- case DEC:
- VG_(new_emit)(simd_flags, FlagsEmpty, FlagsOSZAP);
- if (sz == 2) VG_(emitB) ( 0x66 );
- VG_(emitB) ( 0x48 + reg );
- if (dis)
- VG_(printf)( "\n\t\tdec%c\t%s\n",
- nameISize(sz), nameIReg(sz,reg));
- break;
- case INC:
- VG_(new_emit)(simd_flags, FlagsEmpty, FlagsOSZAP);
- if (sz == 2) VG_(emitB) ( 0x66 );
- VG_(emitB) ( 0x40 + reg );
- if (dis)
- VG_(printf)( "\n\t\tinc%c\t%s\n",
- nameISize(sz), nameIReg(sz,reg));
- break;
- default:
- VG_(core_panic)("VG_(emit_unaryopv_reg)");
- }
-}
-
-void VG_(emit_pushv_reg) ( Int sz, Int reg )
-{
- VG_(new_emit)(False, FlagsEmpty, FlagsEmpty);
- if (sz == 2) {
- VG_(emitB) ( 0x66 );
- } else {
- vg_assert(sz == 4);
- }
- VG_(emitB) ( 0x50 + reg );
- if (dis)
- VG_(printf)("\n\t\tpush%c %s\n", nameISize(sz), nameIReg(sz,reg));
-}
-
-void VG_(emit_popv_reg) ( Int sz, Int reg )
-{
- VG_(new_emit)(False, FlagsEmpty, FlagsEmpty);
- if (sz == 2) {
- VG_(emitB) ( 0x66 );
- } else {
- vg_assert(sz == 4);
- }
- VG_(emitB) ( 0x58 + reg );
- if (dis)
- VG_(printf)("\n\t\tpop%c %s\n", nameISize(sz), nameIReg(sz,reg));
-}
-
-void VG_(emit_pushl_lit32) ( UInt int32 )
-{
- VG_(new_emit)(False, FlagsEmpty, FlagsEmpty);
- VG_(emitB) ( 0x68 );
- VG_(emitL) ( int32 );
- if (dis)
- VG_(printf)("\n\t\tpushl $0x%x\n", int32 );
-}
-
-void VG_(emit_pushl_lit8) ( Int lit8 )
-{
- vg_assert(lit8 >= -128 && lit8 < 128);
- VG_(new_emit)(False, FlagsEmpty, FlagsEmpty);
- VG_(emitB) ( 0x6A );
- VG_(emitB) ( (UChar)((UInt)lit8) );
- if (dis)
- VG_(printf)("\n\t\tpushl $%d\n", lit8 );
-}
-
-void VG_(emit_cmpl_zero_reg) ( Bool simd_flags, Int reg )
-{
- VG_(new_emit)(simd_flags, False, FlagsOSZACP);
- VG_(emitB) ( 0x83 );
- VG_(emit_amode_ereg_greg) ( reg, 7 /* Grp 3 opcode for CMP */ );
- VG_(emitB) ( 0x00 );
- if (dis)
- VG_(printf)("\n\t\tcmpl $0, %s\n", nameIReg(4,reg));
-}
-
-static void emit_swapl_reg_ECX ( Int reg )
-{
- VG_(new_emit)(False, FlagsEmpty, FlagsEmpty);
- VG_(emitB) ( 0x87 ); /* XCHG Gv,Ev */
- VG_(emit_amode_ereg_greg) ( reg, R_ECX );
- if (dis)
- VG_(printf)("\n\t\txchgl %%ecx, %s\n", nameIReg(4,reg));
-}
-
-void VG_(emit_swapl_reg_EAX) ( Int reg )
-{
- VG_(new_emit)(False, FlagsEmpty, FlagsEmpty);
- VG_(emitB) ( 0x90 + reg ); /* XCHG Gv,eAX */
- if (dis)
- VG_(printf)("\n\t\txchgl %%eax, %s\n", nameIReg(4,reg));
-}
-
-static void emit_swapl_reg_reg ( Int reg1, Int reg2 )
-{
- VG_(new_emit)(False, FlagsEmpty, FlagsEmpty);
- VG_(emitB) ( 0x87 ); /* XCHG Gv,Ev */
- VG_(emit_amode_ereg_greg) ( reg1, reg2 );
- if (dis)
- VG_(printf)("\n\t\txchgl %s, %s\n", nameIReg(4,reg1),
- nameIReg(4,reg2));
-}
-
-static void emit_bswapl_reg ( Int reg )
-{
- VG_(new_emit)(False, FlagsEmpty, FlagsEmpty);
- VG_(emitB) ( 0x0F );
- VG_(emitB) ( 0xC8 + reg ); /* BSWAP r32 */
- if (dis)
- VG_(printf)("\n\t\tbswapl %s\n", nameIReg(4,reg));
-}
-
-static void emit_movl_reg_reg ( Int regs, Int regd )
-{
- VG_(new_emit)(False, FlagsEmpty, FlagsEmpty);
- VG_(emitB) ( 0x89 ); /* MOV Gv,Ev */
- VG_(emit_amode_ereg_greg) ( regd, regs );
- if (dis)
- VG_(printf)("\n\t\tmovl %s, %s\n", nameIReg(4,regs), nameIReg(4,regd));
-}
-
-void VG_(emit_movv_lit_offregmem) ( Int sz, UInt lit, Int off, Int memreg )
-{
- VG_(new_emit)(False, FlagsEmpty, FlagsEmpty);
- if (sz == 2) {
- VG_(emitB) ( 0x66 );
- } else {
- vg_assert(sz == 4);
- }
- VG_(emitB) ( 0xC7 ); /* Grp11 Ev */
- VG_(emit_amode_offregmem_reg) ( off, memreg, 0 /* Grp11 subopcode for MOV */ );
- if (sz == 2) VG_(emitW) ( lit ); else VG_(emitL) ( lit );
- if (dis)
- VG_(printf)( "\n\t\tmov%c\t$0x%x, 0x%x(%s)\n",
- nameISize(sz), lit, off, nameIReg(4,memreg) );
-}
-
-
-/*----------------------------------------------------*/
-/*--- b-size (1 byte) instruction emitters ---*/
-/*----------------------------------------------------*/
-
-/* There is some doubt as to whether C6 (Grp 11) is in the
- 486 insn set. ToDo: investigate. */
-void VG_(emit_movb_lit_offregmem) ( UInt lit, Int off, Int memreg )
-{
- VG_(new_emit)(False, FlagsEmpty, FlagsEmpty);
- VG_(emitB) ( 0xC6 ); /* Grp11 Eb */
- VG_(emit_amode_offregmem_reg) ( off, memreg, 0 /* Grp11 subopcode for MOV */ );
- VG_(emitB) ( lit );
- if (dis)
- VG_(printf)( "\n\t\tmovb\t$0x%x, 0x%x(%s)\n",
- lit, off, nameIReg(4,memreg) );
-}
-
-static void emit_nonshiftopb_offregmem_reg ( Bool simd_flags, Opcode opc,
- Int off, Int areg, Int reg )
-{
- VG_(new_emit)(simd_flags, nonshiftop_use(opc), nonshiftop_set(opc));
- VG_(emitB) ( 2 + mkPrimaryOpcode(opc) ); /* op Eb, Gb */
- VG_(emit_amode_offregmem_reg) ( off, areg, reg );
- if (dis)
- VG_(printf)( "\n\t\t%sb\t0x%x(%s), %s\n",
- VG_(name_UOpcode)(False,opc), off, nameIReg(4,areg),
- nameIReg(1,reg));
-}
-
-static void emit_nonshiftopb_lit_offregmem ( Bool simd_flags, Opcode opc,
- UInt lit, Int off, Int areg )
-{
- VG_(new_emit)(simd_flags, nonshiftop_use(opc), nonshiftop_set(opc));
- VG_(emitB) ( 0x80 );
- VG_(emit_amode_offregmem_reg) ( off, areg, mkGrp1opcode(opc) );
- VG_(emitB) ( lit );
- if (dis)
- VG_(printf)( "\n\t\t%sb\t$0x%x, 0x%x(%s)\n",
- VG_(name_UOpcode)(False,opc), lit, off, nameIReg(4,areg));
-}
-
-#if 0
-/* evidently unused */
-static void emit_nonshiftopb_reg_offregmem ( Bool simd_flags, Opcode opc,
- Int off, Int areg, Int reg )
-{
- VG_(new_emit)(simd_flags, nonshiftop_use(opc), nonshiftop_set(opc));
- VG_(emitB) ( 0 + mkPrimaryOpcode(opc) ); /* op Gb, Eb */
- VG_(emit_amode_offregmem_reg) ( off, areg, reg );
- if (dis)
- VG_(printf)( "\n\t\t%sb\t0x%s , %x(%s)\n",
- VG_(name_UOpcode)(False,opc),
- nameIReg(1,reg),
- off, nameIReg(4,areg));
-}
-#endif
-
-void VG_(emit_movb_reg_offregmem) ( Int reg, Int off, Int areg )
-{
- /* Could do better when reg == %al. */
- VG_(new_emit)(False, FlagsEmpty, FlagsEmpty);
- VG_(emitB) ( 0x88 ); /* MOV G1, E1 */
- VG_(emit_amode_offregmem_reg) ( off, areg, reg );
- if (dis)
- VG_(printf)( "\n\t\tmovb\t%s, 0x%x(%s)\n",
- nameIReg(1,reg), off, nameIReg(4,areg));
-}
-
-static void emit_nonshiftopb_reg_reg ( Bool simd_flags, Opcode opc,
- Int reg1, Int reg2 )
-{
- VG_(new_emit)(simd_flags, nonshiftop_use(opc), nonshiftop_set(opc));
- VG_(emitB) ( 2 + mkPrimaryOpcode(opc) ); /* op Eb, Gb */
- VG_(emit_amode_ereg_greg) ( reg1, reg2 );
- if (dis)
- VG_(printf)( "\n\t\t%sb\t%s, %s\n",
- VG_(name_UOpcode)(False,opc),
- nameIReg(1,reg1), nameIReg(1,reg2));
-}
-
-static void emit_movb_reg_regmem ( Bool bounds, Int reg1, Int reg2 )
-{
- VG_(new_emit)(False, FlagsEmpty, FlagsEmpty);
-
- if (bounds)
- boundscheck();
-
- VG_(emitB) ( 0x88 ); /* MOV G1, E1 */
- emit_amode_regmem_reg ( reg2, reg1 );
- if (dis)
- VG_(printf)( "\n\t\tmovb\t%s, (%s)\n", nameIReg(1,reg1),
- nameIReg(4,reg2));
-}
-
-static void emit_nonshiftopb_lit_reg ( Bool simd_flags, Opcode opc,
- UInt lit, Int reg )
-{
- VG_(new_emit)(simd_flags, nonshiftop_use(opc), nonshiftop_set(opc));
- VG_(emitB) ( 0x80 ); /* Grp1 Ib,Eb */
- VG_(emit_amode_ereg_greg) ( reg, mkGrp1opcode(opc) );
- VG_(emitB) ( lit & 0x000000FF );
- if (dis)
- VG_(printf)( "\n\t\t%sb\t$0x%x, %s\n", VG_(name_UOpcode)(False,opc),
- lit, nameIReg(1,reg));
-}
-
-static void emit_shiftopb_lit_reg ( Bool simd_flags, Opcode opc,
- UInt lit, Int reg )
-{
- VG_(new_emit)(simd_flags, shiftop_use(opc), shiftop_set(opc));
- VG_(emitB) ( 0xC0 ); /* Grp2 Ib,Eb */
- VG_(emit_amode_ereg_greg) ( reg, mkGrp2opcode(opc) );
- VG_(emitB) ( lit );
- if (dis)
- VG_(printf)( "\n\t\t%sb\t$%d, %s\n",
- VG_(name_UOpcode)(False,opc),
- lit, nameIReg(1,reg));
-}
-
-void VG_(emit_unaryopb_reg) ( Bool simd_flags, Opcode opc, Int reg )
-{
- switch (opc) {
- case INC:
- VG_(new_emit)(simd_flags, FlagsEmpty, FlagsOSZAP);
- VG_(emitB) ( 0xFE );
- VG_(emit_amode_ereg_greg) ( reg, mkGrp4opcode(INC) );
- if (dis)
- VG_(printf)( "\n\t\tincb\t%s\n", nameIReg(1,reg));
- break;
- case DEC:
- VG_(new_emit)(simd_flags, FlagsEmpty, FlagsOSZAP);
- VG_(emitB) ( 0xFE );
- VG_(emit_amode_ereg_greg) ( reg, mkGrp4opcode(DEC) );
- if (dis)
- VG_(printf)( "\n\t\tdecb\t%s\n", nameIReg(1,reg));
- break;
- case NOT:
- VG_(new_emit)(simd_flags, FlagsEmpty, FlagsEmpty);
- VG_(emitB) ( 0xF6 );
- VG_(emit_amode_ereg_greg) ( reg, mkGrp3opcode(NOT) );
- if (dis)
- VG_(printf)( "\n\t\tnotb\t%s\n", nameIReg(1,reg));
- break;
- case NEG:
- VG_(new_emit)(simd_flags, FlagsEmpty, FlagsOSZACP);
- VG_(emitB) ( 0xF6 );
- VG_(emit_amode_ereg_greg) ( reg, mkGrp3opcode(NEG) );
- if (dis)
- VG_(printf)( "\n\t\tnegb\t%s\n", nameIReg(1,reg));
- break;
- default:
- VG_(core_panic)("VG_(emit_unaryopb_reg)");
- }
-}
-
-void VG_(emit_testb_lit_reg) ( Bool simd_flags, UInt lit, Int reg )
-{
- VG_(new_emit)(simd_flags, FlagsEmpty, FlagsOSZACP);
- VG_(emitB) ( 0xF6 ); /* Grp3 Eb */
- VG_(emit_amode_ereg_greg) ( reg, 0 /* Grp3 subopcode for TEST */ );
- VG_(emitB) ( lit );
- if (dis)
- VG_(printf)("\n\t\ttestb $0x%x, %s\n", lit, nameIReg(1,reg));
-}
-
-/*----------------------------------------------------*/
-/*--- zero-extended load emitters ---*/
-/*----------------------------------------------------*/
-
-void VG_(emit_movzbl_offregmem_reg) ( Bool bounds, Int off, Int regmem, Int reg )
-{
- VG_(new_emit)(False, FlagsEmpty, FlagsEmpty);
- if (bounds)
- boundscheck();
- VG_(emitB) ( 0x0F ); VG_(emitB) ( 0xB6 ); /* MOVZBL */
- VG_(emit_amode_offregmem_reg) ( off, regmem, reg );
- if (dis)
- VG_(printf)( "\n\t\tmovzbl\t0x%x(%s), %s\n",
- off, nameIReg(4,regmem), nameIReg(4,reg));
-}
-
-static void emit_movzbl_regmem_reg ( Bool bounds, Int reg1, Int reg2 )
-{
- VG_(new_emit)(False, FlagsEmpty, FlagsEmpty);
-
- if (bounds)
- boundscheck();
-
- VG_(emitB) ( 0x0F ); VG_(emitB) ( 0xB6 ); /* MOVZBL */
- emit_amode_regmem_reg ( reg1, reg2 );
- if (dis)
- VG_(printf)( "\n\t\tmovzbl\t(%s), %s\n", nameIReg(4,reg1),
- nameIReg(4,reg2));
-}
-
-void VG_(emit_movzwl_offregmem_reg) ( Bool bounds, Int off, Int areg, Int reg )
-{
- VG_(new_emit)(False, FlagsEmpty, FlagsEmpty);
-
- if (bounds)
- boundscheck();
-
- VG_(emitB) ( 0x0F ); VG_(emitB) ( 0xB7 ); /* MOVZWL */
- VG_(emit_amode_offregmem_reg) ( off, areg, reg );
- if (dis)
- VG_(printf)( "\n\t\tmovzwl\t0x%x(%s), %s\n",
- off, nameIReg(4,areg), nameIReg(4,reg));
-}
-
-void VG_( emit_movzwl_regmem_reg ) ( Bool bounds, Int reg1, Int reg2 )
-{
- VG_(new_emit)(False, FlagsEmpty, FlagsEmpty);
-
- if (bounds)
- boundscheck();
-
- VG_(emitB) ( 0x0F ); VG_(emitB) ( 0xB7 ); /* MOVZWL */
- emit_amode_regmem_reg ( reg1, reg2 );
- if (dis)
- VG_(printf)( "\n\t\tmovzwl\t(%s), %s\n", nameIReg(4,reg1),
- nameIReg(4,reg2));
-}
-
-/*----------------------------------------------------*/
-/*--- FPU instruction emitters ---*/
-/*----------------------------------------------------*/
-
-static void emit_get_sse_state ( void )
-{
- Int off = 4 * VGOFF_(m_ssestate);
- if (VG_(have_ssestate)) {
- VG_(new_emit)(False, FlagsEmpty, FlagsEmpty);
- VG_(emitB) ( 0x0F );
- VG_(emitB) ( 0xAE ); VG_(emitB) ( 0x8D ); /* fxrstor d32(%ebp) */
- VG_(emitL) ( off );
- if (dis)
- VG_(printf)("\n\t\tfxrstor\t%d(%%ebp)\n", off );
- } else {
- /* Not a SSE-capable CPU. Just do frstor. */
- VG_(new_emit)(False, FlagsEmpty, FlagsEmpty);
- VG_(emitB) ( 0xDD ); VG_(emitB) ( 0xA5 ); /* frstor d32(%ebp) */
- VG_(emitL) ( off );
- if (dis)
- VG_(printf)("\n\t\tfrstor\t%d(%%ebp)\n", off );
- }
-}
-
-static void emit_put_sse_state ( void )
-{
- Int off = 4 * VGOFF_(m_ssestate);
- if (VG_(have_ssestate)) {
- VG_(new_emit)(False, FlagsEmpty, FlagsEmpty);
- VG_(emitB) ( 0x0F );
- VG_(emitB) ( 0xAE ); VG_(emitB) ( 0x85 ); /* fxsave d32(%ebp) */
- VG_(emitL) ( off );
- if (dis)
- VG_(printf)("\n\t\tfxsave\t%d(%%ebp)\n", off );
- } else {
- /* Not a SSE-capable CPU. Just do fnsave. */
- VG_(new_emit)(False, FlagsEmpty, FlagsEmpty);
- VG_(emitB) ( 0xDD ); VG_(emitB) ( 0xB5 ); /* fnsave d32(%ebp) */
- VG_(emitL) ( off );
- if (dis)
- VG_(printf)("\n\t\tfnsave\t%d(%%ebp)\n", off );
- }
-}
-
-static void emit_fpu_no_mem ( FlagSet uses_sflags,
- FlagSet sets_sflags,
- UChar first_byte,
- UChar second_byte )
-{
- VG_(new_emit)(True, uses_sflags, sets_sflags);
- VG_(emitB) ( first_byte );
- VG_(emitB) ( second_byte );
- if (dis)
- VG_(printf)("\n\t\tfpu-0x%x:0x%x\n",
- (UInt)first_byte, (UInt)second_byte );
-}
-
-static void emit_fpu_regmem ( FlagSet uses_sflags,
- FlagSet sets_sflags,
- UChar first_byte,
- UChar second_byte_masked,
- Int reg )
-{
- VG_(new_emit)(True, uses_sflags, sets_sflags);
-
- boundscheck(); /* assume all FPU ops are the client's */
-
- VG_(emitB) ( first_byte );
- emit_amode_regmem_reg ( reg, second_byte_masked >> 3 );
- if (dis)
- VG_(printf)("\n\t\tfpu-0x%x:0x%x-(%s)\n",
- (UInt)first_byte, (UInt)second_byte_masked,
- nameIReg(4,reg) );
-}
-
-static void emit_MMX2_regmem ( FlagSet uses_sflags,
- FlagSet sets_sflags,
- UChar first_byte,
- UChar second_byte,
- Int ireg )
-{
- VG_(new_emit)(True, uses_sflags, sets_sflags);
-
- boundscheck();
-
- VG_(emitB) ( 0x0F );
- VG_(emitB) ( first_byte );
- second_byte &= 0x38; /* mask out mod and rm fields */
- emit_amode_regmem_reg ( ireg, second_byte >> 3 );
- if (dis)
- VG_(printf)("\n\t\tmmx2-0x%x:0x%x-(%s)\n",
- (UInt)first_byte, (UInt)second_byte,
- nameIReg(4,ireg) );
-}
-
-static void emit_MMX2a1 ( FlagSet uses_sflags,
- FlagSet sets_sflags,
- UChar first_byte,
- UChar second_byte,
- UChar third_byte,
- Int ireg )
-{
- VG_(new_emit)(True, uses_sflags, sets_sflags);
-
- boundscheck();
-
- VG_(emitB) ( 0x0F );
- VG_(emitB) ( first_byte );
- second_byte &= 0x38; /* mask out mod and rm fields */
- emit_amode_regmem_reg ( ireg, second_byte >> 3 );
- VG_(emitB) ( third_byte );
- if (dis)
- VG_(printf)("\n\t\tmmx2a1-0x%x:0x%x:0x%x-(%s)\n",
- (UInt)first_byte, (UInt)second_byte, (UInt)third_byte,
- nameIReg(4,ireg) );
-}
-
-static void emit_SSE2a ( FlagSet uses_sflags,
- FlagSet sets_sflags,
- UChar first_byte,
- UChar second_byte,
- UChar third_byte,
- Int ireg )
-{
- VG_(new_emit)(True, uses_sflags, sets_sflags);
-
- boundscheck();
-
- VG_(emitB) ( first_byte );
- VG_(emitB) ( second_byte );
- third_byte &= 0x38; /* mask out mod and rm fields */
- emit_amode_regmem_reg ( ireg, third_byte >> 3 );
- if (dis)
- VG_(printf)("\n\t\tsse2a-0x%x:0x%x:0x%x-(%s)\n",
- (UInt)first_byte, (UInt)second_byte, (UInt)third_byte,
- nameIReg(4,ireg) );
-}
-
-static void emit_SSE2e1 ( FlagSet uses_sflags,
- FlagSet sets_sflags,
- UChar first_byte,
- UChar second_byte,
- UChar third_byte,
- UChar fourth_byte,
- Int ireg )
-{
- VG_(new_emit)(True, uses_sflags, sets_sflags);
- VG_(emitB) ( first_byte );
- VG_(emitB) ( second_byte );
- third_byte &= 0x38; /* mask out mod and rm fields */
- third_byte |= 0xC0; /* set top two bits: mod = 11b */
- third_byte |= (ireg & 7); /* patch in our ireg */
- VG_(emitB) ( third_byte );
- VG_(emitB) ( fourth_byte );
- if (dis)
- VG_(printf)(
- "\n\t\tsse2e1--0x%x:0x%x:0x%x:0x%x-(%s)\n",
- (UInt)first_byte, (UInt)second_byte,
- (UInt)third_byte, (UInt)fourth_byte,
- nameIReg(4,ireg)
- );
-}
-
-static void emit_SSE2g1 ( FlagSet uses_sflags,
- FlagSet sets_sflags,
- UChar first_byte,
- UChar second_byte,
- UChar third_byte,
- UChar fourth_byte,
- Int ireg )
-{
- VG_(new_emit)(True, uses_sflags, sets_sflags);
- VG_(emitB) ( first_byte );
- VG_(emitB) ( second_byte );
- third_byte &= 0xC7; /* mask out reg field */
- third_byte |= 0xC0; /* set top two bits: mod = 11b */
- third_byte |= ((ireg & 7) << 3); /* patch in our ireg */
- VG_(emitB) ( third_byte );
- VG_(emitB) ( fourth_byte );
- if (dis)
- VG_(printf)(
- "\n\t\tsse2g1_reg_wr--0x%x:0x%x:0x%x:0x%x-(%s)\n",
- (UInt)first_byte, (UInt)second_byte,
- (UInt)third_byte, (UInt)fourth_byte,
- nameIReg(4,ireg)
- );
-}
-
-static void emit_SSE2g ( FlagSet uses_sflags,
- FlagSet sets_sflags,
- UChar first_byte,
- UChar second_byte,
- UChar third_byte,
- Int ireg )
-{
- VG_(new_emit)(True, uses_sflags, sets_sflags);
- VG_(emitB) ( first_byte );
- VG_(emitB) ( second_byte );
- third_byte &= 0xC7; /* mask out reg field */
- third_byte |= 0xC0; /* set top two bits: mod = 11b */
- third_byte |= ((ireg & 7) << 3); /* patch in our ireg */
- VG_(emitB) ( third_byte );
- if (dis)
- VG_(printf)(
- "\n\t\tsse2g--0x%x:0x%x:0x%x-(%s)\n",
- (UInt)first_byte, (UInt)second_byte, (UInt)third_byte,
- nameIReg(4,ireg)
- );
-}
-
-static void emit_SSE2a1 ( FlagSet uses_sflags,
- FlagSet sets_sflags,
- UChar first_byte,
- UChar second_byte,
- UChar third_byte,
- UChar fourth_byte,
- Int ireg )
-{
- VG_(new_emit)(True, uses_sflags, sets_sflags);
-
- boundscheck();
-
- VG_(emitB) ( first_byte );
- VG_(emitB) ( second_byte );
- third_byte &= 0x38; /* mask out mod and rm fields */
- emit_amode_regmem_reg ( ireg, third_byte >> 3 );
- VG_(emitB) ( fourth_byte );
- if (dis)
- VG_(printf)("\n\t\tsse2a1-0x%x:0x%x:0x%x:0x%x-(%s)\n",
- (UInt)first_byte, (UInt)second_byte,
- (UInt)third_byte, (UInt)fourth_byte,
- nameIReg(4,ireg) );
-}
-
-static void emit_SSE3a ( FlagSet uses_sflags,
- FlagSet sets_sflags,
- UChar first_byte,
- UChar second_byte,
- UChar third_byte,
- UChar fourth_byte,
- Int ireg )
-{
- VG_(new_emit)(True, uses_sflags, sets_sflags);
-
- boundscheck();
-
- VG_(emitB) ( first_byte );
- VG_(emitB) ( second_byte );
- VG_(emitB) ( third_byte );
- fourth_byte &= 0x38; /* mask out mod and rm fields */
- emit_amode_regmem_reg ( ireg, fourth_byte >> 3 );
- if (dis)
- VG_(printf)("\n\t\tsse3a-0x%x:0x%x:0x%x:0x%x-(%s)\n",
- (UInt)first_byte, (UInt)second_byte,
- (UInt)third_byte, (UInt)fourth_byte,
- nameIReg(4,ireg) );
-}
-
-static void emit_SSE3e ( FlagSet uses_sflags,
- FlagSet sets_sflags,
- UChar first_byte,
- UChar second_byte,
- UChar third_byte,
- UChar fourth_byte,
- Int ireg )
-{
- VG_(new_emit)(True, uses_sflags, sets_sflags);
- VG_(emitB) ( first_byte );
- VG_(emitB) ( second_byte );
- VG_(emitB) ( third_byte );
- fourth_byte &= 0x38; /* mask out mod and rm fields */
- fourth_byte |= 0xC0; /* set top two bits: mod = 11b */
- fourth_byte |= (ireg & 7); /* patch in our ireg */
- VG_(emitB) ( fourth_byte );
- if (dis)
- VG_(printf)(
- "\n\t\tsse3e--0x%x:0x%x:0x%x:0x%x-(%s)\n",
- (UInt)first_byte, (UInt)second_byte,
- (UInt)third_byte, (UInt)fourth_byte,
- nameIReg(4,ireg)
- );
-}
-
-static void emit_SSE3e1 ( FlagSet uses_sflags,
- FlagSet sets_sflags,
- UChar first_byte,
- UChar second_byte,
- UChar third_byte,
- UChar fourth_byte,
- UChar fifth_byte,
- Int ireg )
-{
- VG_(new_emit)(True, uses_sflags, sets_sflags);
- VG_(emitB) ( first_byte );
- VG_(emitB) ( second_byte );
- VG_(emitB) ( third_byte );
- fourth_byte &= 0x38; /* mask out mod and rm fields */
- fourth_byte |= 0xC0; /* set top two bits: mod = 11b */
- fourth_byte |= (ireg & 7); /* patch in our ireg */
- VG_(emitB) ( fourth_byte );
- VG_(emitB) ( fifth_byte );
- if (dis)
- VG_(printf)(
- "\n\t\tsse3e1--0x%x:0x%x:0x%x:0x%x:0x%x-(%s)\n",
- (UInt)first_byte, (UInt)second_byte,
- (UInt)third_byte, (UInt)fourth_byte, (UInt)fifth_byte,
- nameIReg(4,ireg)
- );
-}
-
-static void emit_SSE3g1 ( FlagSet uses_sflags,
- FlagSet sets_sflags,
- UChar first_byte,
- UChar second_byte,
- UChar third_byte,
- UChar fourth_byte,
- UChar fifth_byte,
- Int ireg )
-{
- VG_(new_emit)(True, uses_sflags, sets_sflags);
- VG_(emitB) ( first_byte );
- VG_(emitB) ( second_byte );
- VG_(emitB) ( third_byte );
- fourth_byte &= 0xC7; /* mask out reg field */
- fourth_byte |= 0xC0; /* set top two bits: mod = 11b */
- fourth_byte |= ((ireg & 7) << 3); /* patch in our ireg */
- VG_(emitB) ( fourth_byte );
- VG_(emitB) ( fifth_byte );
- if (dis)
- VG_(printf)(
- "\n\t\tsse3g1_reg_wr--0x%x:0x%x:0x%x:0x%x:0x%x-(%s)\n",
- (UInt)first_byte, (UInt)second_byte,
- (UInt)third_byte, (UInt)fourth_byte, (UInt)fifth_byte,
- nameIReg(4,ireg)
- );
-}
-
-static void emit_SSE3g ( FlagSet uses_sflags,
- FlagSet sets_sflags,
- UChar first_byte,
- UChar second_byte,
- UChar third_byte,
- UChar fourth_byte,
- Int ireg )
-{
- VG_(new_emit)(True, uses_sflags, sets_sflags);
- VG_(emitB) ( first_byte );
- VG_(emitB) ( second_byte );
- VG_(emitB) ( third_byte );
- fourth_byte &= 0xC7; /* mask out reg field */
- fourth_byte |= 0xC0; /* set top two bits: mod = 11b */
- fourth_byte |= ((ireg & 7) << 3); /* patch in our ireg */
- VG_(emitB) ( fourth_byte );
- if (dis)
- VG_(printf)(
- "\n\t\tsse3g--0x%x:0x%x:0x%x:0x%x-(%s)\n",
- (UInt)first_byte, (UInt)second_byte,
- (UInt)third_byte, (UInt)fourth_byte,
- nameIReg(4,ireg)
- );
-}
-
-static void emit_SSE3a1 ( FlagSet uses_sflags,
- FlagSet sets_sflags,
- UChar first_byte,
- UChar second_byte,
- UChar third_byte,
- UChar fourth_byte,
- UChar fifth_byte,
- Int ireg )
-{
- VG_(new_emit)(True, uses_sflags, sets_sflags);
-
- boundscheck();
-
- VG_(emitB) ( first_byte );
- VG_(emitB) ( second_byte );
- VG_(emitB) ( third_byte );
- fourth_byte &= 0x38; /* mask out mod and rm fields */
- emit_amode_regmem_reg ( ireg, fourth_byte >> 3 );
- VG_(emitB) ( fifth_byte );
- if (dis)
- VG_(printf)("\n\t\tsse3a1-0x%x:0x%x:0x%x:0x%x:0x%x-(%s)\n",
- (UInt)first_byte, (UInt)second_byte,
- (UInt)third_byte, (UInt)fourth_byte,
- (UInt)fifth_byte,
- nameIReg(4,ireg) );
-}
-
-static void emit_SSE4 ( FlagSet uses_sflags,
- FlagSet sets_sflags,
- UChar first_byte,
- UChar second_byte,
- UChar third_byte,
- UChar fourth_byte )
-{
- VG_(new_emit)(True, uses_sflags, sets_sflags);
- VG_(emitB) ( first_byte );
- VG_(emitB) ( second_byte );
- VG_(emitB) ( third_byte );
- VG_(emitB) ( fourth_byte );
- if (dis)
- VG_(printf)("\n\t\tsse4-0x%x:0x%x:0x%x:0x%x\n",
- (UInt)first_byte, (UInt)second_byte,
- (UInt)third_byte, (UInt)fourth_byte );
-}
-
-static void emit_SSE5 ( FlagSet uses_sflags,
- FlagSet sets_sflags,
- UChar first_byte,
- UChar second_byte,
- UChar third_byte,
- UChar fourth_byte,
- UChar fifth_byte )
-{
- VG_(new_emit)(True, uses_sflags, sets_sflags);
- VG_(emitB) ( first_byte );
- VG_(emitB) ( second_byte );
- VG_(emitB) ( third_byte );
- VG_(emitB) ( fourth_byte );
- VG_(emitB) ( fifth_byte );
- if (dis)
- VG_(printf)("\n\t\tsse5-0x%x:0x%x:0x%x:0x%x:0x%x\n",
- (UInt)first_byte, (UInt)second_byte,
- (UInt)third_byte, (UInt)fourth_byte,
- (UInt)fifth_byte );
-}
-
-static void emit_SSE3 ( FlagSet uses_sflags,
- FlagSet sets_sflags,
- UChar first_byte,
- UChar second_byte,
- UChar third_byte )
-{
- VG_(new_emit)(True, uses_sflags, sets_sflags);
- VG_(emitB) ( first_byte );
- VG_(emitB) ( second_byte );
- VG_(emitB) ( third_byte );
- if (dis)
- VG_(printf)("\n\t\tsse3-0x%x:0x%x:0x%x\n",
- (UInt)first_byte, (UInt)second_byte,
- (UInt)third_byte );
-}
-
-static void emit_SSE3ag_MemRd_RegWr ( FlagSet uses_sflags,
- FlagSet sets_sflags,
- UChar first_byte,
- UChar second_byte,
- UChar third_byte,
- Int addr_reg,
- Int dest_reg )
-{
- VG_(new_emit)(True, uses_sflags, sets_sflags);
- VG_(emitB) ( first_byte );
- VG_(emitB) ( second_byte );
- VG_(emitB) ( third_byte );
- /* 4th byte can be completely synthesised from addr_reg and
- dest_reg. */
- emit_amode_regmem_reg ( addr_reg, dest_reg );
- if (dis)
- VG_(printf)("\n\t\tsse3ag_mem_rd_reg_wr-0x%x:0x%x:0x%x(addr=%s, dest=%s)\n",
- (UInt)first_byte, (UInt)second_byte,
- (UInt)third_byte, nameIReg(4, addr_reg),
- nameIReg(4, dest_reg));
-}
-
-static void emit_MMX2_reg_to_mmxreg ( FlagSet uses_sflags,
- FlagSet sets_sflags,
- UChar first_byte,
- UChar second_byte,
- Int ireg )
-{
- VG_(new_emit)(True, uses_sflags, sets_sflags);
- VG_(emitB) ( 0x0F );
- VG_(emitB) ( first_byte );
- second_byte &= 0x38; /* mask out mod and rm fields */
- second_byte |= 0xC0; /* set top two bits: mod = 11b */
- second_byte |= (ireg & 7); /* patch in our ireg */
- VG_(emitB) ( second_byte );
- if (dis)
- VG_(printf)("\n\t\tmmx2:reg-to-mmxreg--0x%x:0x%x-(%s)\n",
- (UInt)first_byte, (UInt)second_byte,
- nameIReg(4,ireg) );
-}
-
-static void emit_MMX2_mmxreg_to_reg ( FlagSet uses_sflags,
- FlagSet sets_sflags,
- UChar first_byte,
- UChar second_byte,
- Int ireg )
-{
- VG_(new_emit)(True, uses_sflags, sets_sflags);
- VG_(emitB) ( 0x0F );
- VG_(emitB) ( first_byte );
- second_byte &= 0x38; /* mask out mod and rm fields */
- second_byte |= 0xC0; /* set top two bits: mod = 11b */
- second_byte |= (ireg & 7); /* patch in our ireg */
- VG_(emitB) ( second_byte );
- if (dis)
- VG_(printf)("\n\t\tmmx2:mmxreg-to-reg--0x%x:0x%x-(%s)\n",
- (UInt)first_byte, (UInt)second_byte,
- nameIReg(4,ireg) );
-}
-
-static void emit_MMX3_no_mem ( FlagSet uses_sflags,
- FlagSet sets_sflags,
- UChar first_byte,
- UChar second_byte,
- UChar third_byte )
-{
- VG_(new_emit)(True, uses_sflags, sets_sflags);
- VG_(emitB) ( 0x0F );
- VG_(emitB) ( first_byte );
- VG_(emitB) ( second_byte );
- VG_(emitB) ( third_byte );
- if (dis)
- VG_(printf)("\n\t\tmmx3-0x%x:0x%x:0x%x\n",
- (UInt)first_byte, (UInt)second_byte, (UInt)third_byte );
-}
-
-static void emit_MMX2_no_mem ( FlagSet uses_sflags,
- FlagSet sets_sflags,
- UChar first_byte,
- UChar second_byte )
-{
- VG_(new_emit)(True, uses_sflags, sets_sflags);
- VG_(emitB) ( 0x0F );
- VG_(emitB) ( first_byte );
- VG_(emitB) ( second_byte );
- if (dis)
- VG_(printf)("\n\t\tmmx2-0x%x:0x%x\n",
- (UInt)first_byte, (UInt)second_byte );
-}
-
-static void emit_MMX1_no_mem ( FlagSet uses_sflags,
- FlagSet sets_sflags,
- UChar first_byte )
-{
- VG_(new_emit)(True, uses_sflags, sets_sflags);
- VG_(emitB) ( 0x0F );
- VG_(emitB) ( first_byte );
- if (dis)
- VG_(printf)("\n\t\tmmx1-0x%x\n",
- (UInt)first_byte );
-}
-
-
-/*----------------------------------------------------*/
-/*--- misc instruction emitters ---*/
-/*----------------------------------------------------*/
-
-void VG_(emit_call_reg) ( Int reg )
-{
- VG_(new_emit)(False, FlagsEmpty, FlagsOSZACP); /* XXX */
- VG_(emitB) ( 0xFF ); /* Grp5 */
- VG_(emit_amode_ereg_greg) ( reg, mkGrp5opcode(CALLM) );
- if (dis)
- VG_(printf)( "\n\t\tcall\t*%s\n", nameIReg(4,reg) );
-}
-
-static
-void emit_call_star_EBP_off ( Bool simd_flags, Int byte_off,
- FlagSet use_flag, FlagSet set_flag )
-{
- /* Used for helpers which expect to see Simd flags in Real flags */
- VG_(new_emit)(simd_flags, use_flag, set_flag);
-
- if (byte_off < -128 || byte_off > 127) {
- VG_(emitB) ( 0xFF );
- VG_(emitB) ( 0x95 );
- VG_(emitL) ( byte_off );
- } else {
- VG_(emitB) ( 0xFF );
- VG_(emitB) ( 0x55 );
- VG_(emitB) ( byte_off );
- }
- if (dis)
- VG_(printf)( "\n\t\tcall * %d(%%ebp)\n", byte_off );
-}
-
-#if 0
-/* evidently unused */
-static void emit_addlit8_offregmem ( Int lit8, Int regmem, Int off )
-{
- vg_assert(lit8 >= -128 && lit8 < 128);
- VG_(new_emit)(True, FlagsEmpty, FlagsOSZACP);
- VG_(emitB) ( 0x83 ); /* Grp1 Ib,Ev */
- VG_(emit_amode_offregmem_reg) ( off, regmem,
- 0 /* Grp1 subopcode for ADD */ );
- VG_(emitB) ( lit8 & 0xFF );
- if (dis)
- VG_(printf)( "\n\t\taddl $%d, %d(%s)\n", lit8, off,
- nameIReg(4,regmem));
-}
-#endif
-
-void VG_(emit_add_lit_to_esp) ( Int lit )
-{
- if (lit < -128 || lit > 127) VG_(core_panic)("VG_(emit_add_lit_to_esp)");
- VG_(new_emit)(False, FlagsEmpty, FlagsEmpty);
- VG_(emitB) ( 0x8D );
- VG_(emitB) ( 0x64 );
- VG_(emitB) ( 0x24 );
- VG_(emitB) ( lit & 0xFF );
- if (dis)
- VG_(printf)( "\n\t\tlea\t%d(%%esp), %%esp\n", lit );
-}
-
-
-static void emit_movb_AL_zeroESPmem ( void )
-{
- /* movb %al, 0(%esp) */
- /* 88442400 movb %al, 0(%esp) */
- VG_(new_emit)(False, FlagsEmpty, FlagsEmpty);
- VG_(emitB) ( 0x88 );
- VG_(emitB) ( 0x44 );
- VG_(emitB) ( 0x24 );
- VG_(emitB) ( 0x00 );
- if (dis)
- VG_(printf)( "\n\t\tmovb %%al, 0(%%esp)\n" );
-}
-
-static void emit_movb_zeroESPmem_AL ( void )
-{
- /* movb 0(%esp), %al */
- /* 8A442400 movb 0(%esp), %al */
- VG_(new_emit)(False, FlagsEmpty, FlagsEmpty);
- VG_(emitB) ( 0x8A );
- VG_(emitB) ( 0x44 );
- VG_(emitB) ( 0x24 );
- VG_(emitB) ( 0x00 );
- if (dis)
- VG_(printf)( "\n\t\tmovb 0(%%esp), %%al\n" );
-}
-
-/* Jump target states */
-#define TGT_UNDEF (1 << 16)
-#define TGT_FORWARD (2 << 16)
-#define TGT_BACKWARD (3 << 16)
-
-static inline Int tgt_state(Int tgt)
-{
- return tgt & 0xffff0000;
-}
-
-static inline Int tgt_addr(Int tgt)
-{
- return tgt & 0x0000ffff;
-}
-
-static inline Int mk_tgt(Int state, Int addr)
-{
- vg_assert(state == TGT_UNDEF ||
- state == TGT_FORWARD ||
- state == TGT_BACKWARD);
- vg_assert((addr & 0xffff0000) == 0);
-
- return state | addr;
-}
-
-void VG_(init_target) ( Int *tgt )
-{
- *tgt = TGT_UNDEF;
-}
-
-void VG_(target_back) ( Int *tgt )
-{
- vg_assert(tgt_state(*tgt) == TGT_UNDEF);
-
- *tgt = mk_tgt(TGT_BACKWARD, emitted_code_used);
-}
-
-void VG_(target_forward) ( Int *tgt )
-{
- Int delta;
-
- vg_assert(tgt_state(*tgt) == TGT_FORWARD ||
- tgt_state(*tgt) == TGT_UNDEF);
-
- if (tgt_state(*tgt) == TGT_UNDEF)
- return; /* target not used */
-
- delta = emitted_code_used - (tgt_addr(*tgt) + 1);
- vg_assert(delta >= -128 && delta <= 127);
- vg_assert(tgt_addr(*tgt) >= 0);
- vg_assert(tgt_addr(*tgt) < emitted_code_used);
- emitted_code[tgt_addr(*tgt)] = delta;
- if (dis)
- VG_(printf)("(target to jump site %d; delta: %d)\n",
- tgt_addr(*tgt), delta);
-}
-
-void VG_(emit_target_delta) ( Int *tgt )
-{
- vg_assert(tgt_state(*tgt) == TGT_UNDEF ||
- tgt_state(*tgt) == TGT_BACKWARD);
-
- if (tgt_state(*tgt) == TGT_UNDEF) {
- /* forward jump */
- *tgt = mk_tgt(TGT_FORWARD, emitted_code_used);
- VG_(emitB) (0x00);
- } else {
- /* backward jump */
- Int delta = emitted_code_used - (tgt_addr(*tgt) + 1);
- vg_assert(delta >= -128 && delta <= 127);
- VG_(emitB) (delta);
- }
-}
-
-
-/* Emit a jump short with an 8-bit signed offset. Note that the
- offset is that which should be added to %eip once %eip has been
- advanced over this insn. */
-void VG_(emit_jcondshort_delta) ( Bool simd_flags, Condcode cond, Int delta, JumpPred pred )
-{
- vg_assert(delta >= -128 && delta <= 127);
- VG_(new_emit)(simd_flags, FlagsOSZCP, FlagsEmpty);
-
- if (VG_(clo_branchpred) &&
- pred != JP_NONE &&
- pred != static_pred(cond, delta > 0))
- VG_(emitB)(pred == JP_TAKEN ? 0x3e : 0x2e);
-
- VG_(emitB) ( 0x70 + (UInt)cond );
- VG_(emitB) ( (UChar)delta );
- if (dis)
- VG_(printf)( "\n\t\tj%s-8%s\t%%eip+%d\n",
- VG_(name_UCondcode)(cond), predstr(pred), delta );
-}
-
-/* Same as above, but defers emitting the delta */
-void VG_(emit_jcondshort_target) ( Bool simd, Condcode cond, Int *tgt, JumpPred pred )
-{
- VG_(new_emit)(simd, FlagsOSZCP, FlagsEmpty);
-
- if (VG_(clo_branchpred) &&
- pred != JP_NONE &&
- pred != static_pred(cond, tgt_state(*tgt) != TGT_BACKWARD))
- VG_(emitB)(pred == JP_TAKEN ? 0x3e : 0x2e);
-
- VG_(emitB) ( 0x70 + (UInt)cond );
- VG_(emit_target_delta) (tgt);
- if (dis)
- VG_(printf)( "\n\t\tj%s-8%s\t%%eip+(%d)\n",
- VG_(name_UCondcode)(cond), predstr(pred), tgt_addr(*tgt) );
-}
-
-
-
-static void emit_setb_reg ( Bool simd, Int reg, Condcode cond )
-{
- VG_(new_emit)(simd, FlagsOSZCP, FlagsEmpty);
- VG_(emitB) ( 0x0F ); VG_(emitB) ( 0x90 + (UChar)cond );
- VG_(emit_amode_ereg_greg) ( reg, 0 );
- if (dis)
- VG_(printf)("\n\t\tset%s %s\n",
- VG_(name_UCondcode)(cond), nameIReg(1,reg));
-}
-
-static void emit_ret ( void )
-{
- maybe_emit_put_eflags(); /* make sure flags are stored */
- VG_(new_emit)(False, FlagsEmpty, FlagsEmpty);
- VG_(emitB) ( 0xC3 ); /* RET */
- if (dis)
- VG_(printf)("\n\t\tret\n");
-}
-
-/* Predicate used in sanity checks elsewhere - returns true if any
- jump-site is an actual chained jump */
-__attribute__((unused))
-static Bool is_chained_jumpsite(Addr a)
-{
- UChar *cp = (UChar *)a;
-
- return (*cp == 0xE9); /* 0xE9 -- jmp */
-}
-
-static
-Bool is_fresh_jumpsite(UChar *cp)
-{
- return
- cp[0] == 0x0F && /* UD2 */
- cp[1] == 0x0B &&
- cp[2] == 0x0F && /* UD2 */
- cp[3] == 0x0B &&
- cp[4] == 0x90; /* NOP */
-}
-
-/* Predicate used in sanity checks elsewhere - returns true if all
- jump-sites are calls to VG_(patch_me) */
-static Bool is_unchained_jumpsite(Addr a)
-{
- UChar *cp = (UChar *)a;
- Int delta = ((Addr)&VG_(patch_me)) - (a + VG_PATCHME_CALLSZ);
- Int idelta;
-
- if (*cp++ != 0xE8) /* 0xE8 == call */
- return False;
-
- idelta = (*cp++) << 0;
- idelta |= (*cp++) << 8;
- idelta |= (*cp++) << 16;
- idelta |= (*cp++) << 24;
-
- return idelta == delta;
-}
-
-/* Return target address for a direct jmp */
-Addr VG_(get_jmp_dest)(Addr a)
-{
- Int delta;
- UChar *cp = (UChar *)a;
-
- if (*cp++ != 0xE9) /* 0xE9 == jmp */
- return 0;
-
- delta = (*cp++) << 0;
- delta |= (*cp++) << 8;
- delta |= (*cp++) << 16;
- delta |= (*cp++) << 24;
-
- return a + VG_PATCHME_JMPSZ + delta;
-}
-
-/* unchain a BB by generating a call to VG_(patch_me) */
-void VG_(unchain_jumpsite)(Addr a)
-{
- Int delta = ((Addr)&VG_(patch_me)) - (a + VG_PATCHME_CALLSZ);
- UChar *cp = (UChar *)a;
-
- if (is_unchained_jumpsite(a))
- return; /* don't write unnecessarily */
-
- if (!is_fresh_jumpsite(cp))
- VG_(bb_dechain_count)++; /* update stats */
-
- *cp++ = 0xE8; /* call */
- *cp++ = (delta >> 0) & 0xff;
- *cp++ = (delta >> 8) & 0xff;
- *cp++ = (delta >> 16) & 0xff;
- *cp++ = (delta >> 24) & 0xff;
-}
-
-/* This doesn't actually generate a call to VG_(patch_me), but
- reserves enough space in the instruction stream for it to happen
- and records the offset into the jump table. This is because call
- is a relative jump, and so will be affected when this code gets
- moved about. The translation table will "unchain" this basic block
- on insertion (with VG_(unchain_BB)()), and thereby generate a
- proper call instruction. */
-static void emit_call_patchme( void )
-{
- vg_assert(VG_PATCHME_CALLSZ == 5);
-
- maybe_emit_put_eflags(); /* save flags before end of BB */
- VG_(new_emit)(False, FlagsEmpty, FlagsEmpty);
-
- if (jumpidx >= VG_MAX_JUMPS) {
- /* If there too many jumps in this basic block, fall back to
- dispatch loop. We still need to keep it the same size as the
- call sequence. */
- VG_(emitB) ( 0xC3 ); /* ret */
- VG_(emitB) ( 0x8d ); /* 4 byte nop (lea 0x0(%esi,1),%esi) */
- VG_(emitB) ( 0x74 );
- VG_(emitB) ( 0x26 );
- VG_(emitB) ( 0x00 );
-
- if (dis)
- VG_(printf)("\n\t\tret; nop4\n");
-
- if (0 && VG_(clo_verbosity))
- VG_(message)(Vg_DebugMsg, "too many chained jumps in basic-block");
- } else {
- jumps[jumpidx++] = emitted_code_used;
-
- VG_(emitB) ( 0x0F ); /* UD2 - undefined instruction */
- VG_(emitB) ( 0x0B );
- VG_(emitB) ( 0x0F ); /* UD2 - undefined instruction */
- VG_(emitB) ( 0x0B );
- VG_(emitB) ( 0x90 ); /* NOP */
-
- if (dis)
- VG_(printf)("\n\t\tud2; ud2; nop /* call VG_(patch_me) */\n");
- }
-}
-
-void VG_(emit_pushal) ( void )
-{
- VG_(new_emit)(False, FlagsEmpty, FlagsEmpty);
- VG_(emitB) ( 0x60 ); /* PUSHAL */
- if (dis)
- VG_(printf)("\n\t\tpushal\n");
-}
-
-void VG_(emit_popal) ( void )
-{
- VG_(new_emit)(False, FlagsEmpty, FlagsEmpty);
- VG_(emitB) ( 0x61 ); /* POPAL */
- if (dis)
- VG_(printf)("\n\t\tpopal\n");
-}
-
-static void emit_lea_litreg_reg ( UInt lit, Int regmem, Int reg )
-{
- VG_(new_emit)(False, FlagsEmpty, FlagsEmpty);
- VG_(emitB) ( 0x8D ); /* LEA M,Gv */
- VG_(emit_amode_offregmem_reg) ( (Int)lit, regmem, reg );
- if (dis)
- VG_(printf)("\n\t\tleal 0x%x(%s), %s\n",
- lit, nameIReg(4,regmem), nameIReg(4,reg) );
-}
-
-static void emit_lea_sib_reg ( UInt lit, Int scale,
- Int regbase, Int regindex, Int reg )
-{
- VG_(new_emit)(False, FlagsEmpty, FlagsEmpty);
- VG_(emitB) ( 0x8D ); /* LEA M,Gv */
- emit_amode_sib_reg ( (Int)lit, scale, regbase, regindex, reg );
- if (dis)
- VG_(printf)("\n\t\tleal 0x%x(%s,%s,%d), %s\n",
- lit, nameIReg(4,regbase),
- nameIReg(4,regindex), scale,
- nameIReg(4,reg) );
-}
-
-void VG_(emit_AMD_prefetch_reg) ( Int reg )
-{
- VG_(new_emit)(False, FlagsEmpty, FlagsEmpty);
- VG_(emitB) ( 0x0F );
- VG_(emitB) ( 0x0D );
- emit_amode_regmem_reg ( reg, 1 /* 0 is prefetch; 1 is prefetchw */ );
- if (dis)
- VG_(printf)("\n\t\tamd-prefetch (%s)\n", nameIReg(4,reg) );
-}
-
-/*----------------------------------------------------*/
-/*--- Instruction synthesisers ---*/
-/*----------------------------------------------------*/
-
-static Condcode invertCondition ( Condcode cond )
-{
- return (Condcode)(1 ^ (UInt)cond);
-}
-
-
-/* Synthesise a call to *baseBlock[offset], ie,
- call * (4 x offset)(%ebp).
-*/
-void VG_(synth_call) ( Bool ensure_shortform, Int word_offset,
- Bool simd_flags, FlagSet use_flags, FlagSet set_flags )
-{
- vg_assert(word_offset >= 0);
- vg_assert(word_offset < VG_BASEBLOCK_WORDS);
- if (ensure_shortform) {
- vg_assert(word_offset < 32);
- }
- emit_call_star_EBP_off ( simd_flags, 4 * word_offset, use_flags, set_flags );
-}
-
-static void maybe_emit_movl_reg_reg ( UInt src, UInt dst )
-{
- if (src != dst) {
- VG_(emit_movv_reg_reg) ( 4, src, dst );
- ccall_arg_setup_instrs++;
- }
-}
-
-/* 'maybe' because it is sometimes skipped eg. for "movl %eax,%eax" */
-static void maybe_emit_movl_litOrReg_reg ( UInt litOrReg, Tag tag, UInt reg )
-{
- if (RealReg == tag) {
- maybe_emit_movl_reg_reg ( litOrReg, reg );
- } else if (Literal == tag) {
- VG_(emit_movv_lit_reg) ( 4, litOrReg, reg );
- ccall_arg_setup_instrs++;
- }
- else
- VG_(core_panic)("emit_movl_litOrReg_reg: unexpected tag");
-}
-
-static
-void emit_swapl_arg_regs ( UInt reg1, UInt reg2 )
-{
- if (R_EAX == reg1) {
- VG_(emit_swapl_reg_EAX) ( reg2 );
- } else if (R_EAX == reg2) {
- VG_(emit_swapl_reg_EAX) ( reg1 );
- } else {
- emit_swapl_reg_reg ( reg1, reg2 );
- }
- ccall_arg_setup_instrs++;
-}
-
-static
-void emit_two_regs_args_setup ( UInt src1, UInt src2, UInt dst1, UInt dst2)
-{
- if (dst1 != src2) {
- maybe_emit_movl_reg_reg ( src1, dst1 );
- maybe_emit_movl_reg_reg ( src2, dst2 );
-
- } else if (dst2 != src1) {
- maybe_emit_movl_reg_reg ( src2, dst2 );
- maybe_emit_movl_reg_reg ( src1, dst1 );
-
- } else {
- /* swap to break cycle */
- emit_swapl_arg_regs ( dst1, dst2 );
- }
-}
-
-static
-void emit_three_regs_args_setup ( UInt src1, UInt src2, UInt src3,
- UInt dst1, UInt dst2, UInt dst3)
-{
- if (dst1 != src2 && dst1 != src3) {
- maybe_emit_movl_reg_reg ( src1, dst1 );
- emit_two_regs_args_setup ( src2, src3, dst2, dst3 );
-
- } else if (dst2 != src1 && dst2 != src3) {
- maybe_emit_movl_reg_reg ( src2, dst2 );
- emit_two_regs_args_setup ( src1, src3, dst1, dst3 );
-
- } else if (dst3 != src1 && dst3 != src2) {
- maybe_emit_movl_reg_reg ( src3, dst3 );
- emit_two_regs_args_setup ( src1, src2, dst1, dst2 );
-
- } else {
- /* break cycle */
- if (dst1 == src2 && dst2 == src3 && dst3 == src1) {
- emit_swapl_arg_regs ( dst1, dst2 );
- emit_swapl_arg_regs ( dst1, dst3 );
-
- } else if (dst1 == src3 && dst2 == src1 && dst3 == src2) {
- emit_swapl_arg_regs ( dst1, dst3 );
- emit_swapl_arg_regs ( dst1, dst2 );
-
- } else {
- VG_(core_panic)("impossible 3-cycle");
- }
- }
-}
-
-static
-void emit_two_regs_or_lits_args_setup ( UInt argv[], Tag tagv[],
- UInt src1, UInt src2,
- UInt dst1, UInt dst2)
-{
- /* If either are lits, order doesn't matter */
- if (Literal == tagv[src1] || Literal == tagv[src2]) {
- maybe_emit_movl_litOrReg_reg ( argv[src1], tagv[src1], dst1 );
- maybe_emit_movl_litOrReg_reg ( argv[src2], tagv[src2], dst2 );
-
- } else {
- emit_two_regs_args_setup ( argv[src1], argv[src2], dst1, dst2 );
- }
-}
-
-static
-void emit_three_regs_or_lits_args_setup ( UInt argv[], Tag tagv[],
- UInt src1, UInt src2, UInt src3,
- UInt dst1, UInt dst2, UInt dst3)
-{
- // SSS: fix this eventually -- make STOREV use two RealRegs?
- /* Not supporting literals for 3-arg C functions -- they're only used
- by STOREV which has 2 args */
- vg_assert(RealReg == tagv[src1] &&
- RealReg == tagv[src2] &&
- RealReg == tagv[src3]);
- emit_three_regs_args_setup ( argv[src1], argv[src2], argv[src3],
- dst1, dst2, dst3 );
-}
-
-/* Synthesise a call to a C function `fn' (which must be registered in
- baseBlock) doing all the reg saving and arg handling work.
-
- WARNING: a UInstr should *not* be translated with synth_ccall followed
- by some other x86 assembly code; vg_liveness_analysis() doesn't expect
- such behaviour and everything will fall over.
- */
-void VG_(synth_ccall) ( Addr fn, Int argc, Int regparms_n, UInt argv[],
- Tag tagv[], Int ret_reg,
- RRegSet regs_live_before, RRegSet regs_live_after )
-{
- Int i;
- Int stack_used = 0;
- Bool preserve_eax, preserve_ecx, preserve_edx;
-
- vg_assert(0 <= regparms_n && regparms_n <= 3);
-
- ccalls++;
-
- /* If %e[acd]x is live before and after the C call, save/restore it.
- Unless the return values clobbers the reg; in this case we must not
- save/restore the reg, because the restore would clobber the return
- value. (Before and after the UInstr really constitute separate live
- ranges, but you miss this if you don't consider what happens during
- the UInstr.) */
-# define PRESERVE_REG(realReg) \
- (IS_RREG_LIVE(VG_(realreg_to_rank)(realReg), regs_live_before) && \
- IS_RREG_LIVE(VG_(realreg_to_rank)(realReg), regs_live_after) && \
- ret_reg != realReg)
-
- preserve_eax = PRESERVE_REG(R_EAX);
- preserve_ecx = PRESERVE_REG(R_ECX);
- preserve_edx = PRESERVE_REG(R_EDX);
-
-# undef PRESERVE_REG
-
- /* Save caller-save regs as required */
- if (preserve_eax) { VG_(emit_pushv_reg) ( 4, R_EAX ); ccall_reg_saves++; }
- if (preserve_ecx) { VG_(emit_pushv_reg) ( 4, R_ECX ); ccall_reg_saves++; }
- if (preserve_edx) { VG_(emit_pushv_reg) ( 4, R_EDX ); ccall_reg_saves++; }
-
- /* Args are passed in two groups: (a) via stack (b) via regs. regparms_n
- is the number of args passed in regs (maximum 3 for GCC on x86). */
-
- ccall_args += argc;
-
- /* First push stack args (RealRegs or Literals) in reverse order. */
- for (i = argc-1; i >= regparms_n; i--) {
- switch (tagv[i]) {
- case RealReg:
- VG_(emit_pushv_reg) ( 4, argv[i] );
- break;
- case Literal:
- /* Use short form of pushl if possible. */
- if (argv[i] == VG_(extend_s_8to32) ( argv[i] ))
- VG_(emit_pushl_lit8) ( VG_(extend_s_8to32)(argv[i]) );
- else
- VG_(emit_pushl_lit32)( argv[i] );
- break;
- default:
- VG_(printf)("tag=%d\n", tagv[i]);
- VG_(core_panic)("VG_(synth_ccall): bad tag");
- }
- stack_used += 4;
- ccall_arg_setup_instrs++;
- }
-
- /* Then setup args in registers (arg[123] --> %e[adc]x; note order!).
- If moving values between registers, be careful not to clobber any on
- the way. Happily we can use xchgl to swap registers.
- */
- switch (regparms_n) {
-
- /* Trickiest. Args passed in %eax, %edx, and %ecx. */
- case 3:
- emit_three_regs_or_lits_args_setup ( argv, tagv, 0, 1, 2,
- R_EAX, R_EDX, R_ECX );
- break;
-
- /* Less-tricky. Args passed in %eax and %edx. */
- case 2:
- emit_two_regs_or_lits_args_setup ( argv, tagv, 0, 1, R_EAX, R_EDX );
- break;
-
- /* Easy. Just move arg1 into %eax (if not already in there). */
- case 1:
- maybe_emit_movl_litOrReg_reg ( argv[0], tagv[0], R_EAX );
- break;
-
- case 0:
- break;
-
- default:
- VG_(core_panic)("VG_(synth_call): regparms_n value not in range 0..3");
- }
-
- /* Call the function - may trash all flags */
- VG_(synth_call) ( False, VG_(helper_offset) ( fn ), False,
- FlagsEmpty, FlagsOSZACP );
-
- /* Clear any args from stack */
- if (0 != stack_used) {
- VG_(emit_add_lit_to_esp) ( stack_used );
- ccall_stack_clears++;
- }
-
- /* Move return value into ret_reg if necessary and not already there */
- if (INVALID_REALREG != ret_reg) {
- ccall_retvals++;
- if (R_EAX != ret_reg) {
- VG_(emit_movv_reg_reg) ( 4, R_EAX, ret_reg );
- ccall_retval_movs++;
- }
- }
-
- /* Restore live caller-save regs as required */
- if (preserve_edx) VG_(emit_popv_reg) ( 4, R_EDX );
- if (preserve_ecx) VG_(emit_popv_reg) ( 4, R_ECX );
- if (preserve_eax) VG_(emit_popv_reg) ( 4, R_EAX );
-}
-
-static void load_ebp_from_JmpKind ( JmpKind jmpkind )
-{
- switch (jmpkind) {
- case JmpBoring:
- break;
- case JmpRet:
- break;
- case JmpCall:
- break;
- case JmpSyscall:
- VG_(emit_movv_lit_reg) ( 4, VG_TRC_EBP_JMP_SYSCALL, R_EBP );
- break;
- case JmpClientReq:
- VG_(emit_movv_lit_reg) ( 4, VG_TRC_EBP_JMP_CLIENTREQ, R_EBP );
- break;
- case JmpYield:
- VG_(emit_movv_lit_reg) ( 4, VG_TRC_EBP_JMP_YIELD, R_EBP );
- break;
- default:
- VG_(core_panic)("load_ebp_from_JmpKind");
- }
-}
-
-/* Jump to the next translation, by loading its original addr into
- %eax and returning to the scheduler. Signal special requirements
- by loading a special value into %ebp first.
-*/
-static void synth_jmp_reg ( Int reg, JmpKind jmpkind )
-{
- maybe_emit_put_eflags(); /* save flags here */
- load_ebp_from_JmpKind ( jmpkind );
- if (reg != R_EAX)
- VG_(emit_movv_reg_reg) ( 4, reg, R_EAX );
- emit_ret();
-}
-
-static void synth_mov_reg_offregmem ( Int size, Int reg, Int off, Int areg );
-
-/* Same deal as synth_jmp_reg. */
-static void synth_jmp_lit ( Addr addr, JmpKind jmpkind )
-{
- maybe_emit_put_eflags(); /* save flags here */
-
- VG_(emit_movv_lit_reg) ( 4, addr, R_EAX );
-
- if (VG_(clo_chain_bb) && (jmpkind == JmpBoring || jmpkind == JmpCall)) {
- synth_mov_reg_offregmem(4, R_EAX, 4*VGOFF_(m_eip), R_EBP); /* update EIP */
- emit_call_patchme();
- } else {
- load_ebp_from_JmpKind ( jmpkind );
- emit_ret();
- }
-}
-
-
-static void synth_mov_offregmem_reg ( Int size, Int off, Int areg, Int reg );
-static void synth_nonshiftop_lit_reg ( Bool simd_flags,
- Opcode opcode, Int size,
- UInt lit, Int reg );
-
-static void synth_jcond_lit ( Condcode cond,
- Addr addr,
- Bool eax_trashable )
-{
- UInt mask;
- Bool simd;
- Int tgt, tgt2, tgt_jump;
-
- VG_(init_target)(&tgt);
- VG_(init_target)(&tgt2);
- VG_(init_target)(&tgt_jump);
-
- /* Ensure simulated %EFLAGS are up-to-date, by copying back %eflags
- if need be */
- maybe_emit_put_eflags();
- vg_assert(eflags_state == UPD_Both || eflags_state == UPD_Simd);
-
- if (eflags_state == UPD_Both) {
- /* The flags are already set up, so we just use them as is. */
- simd = True;
- cond = invertCondition(cond);
- } else {
- Bool parity = False; /* test Z or P */
-
- /* The simd state contains the most recent version, so we emit a
- sequence to calculate the relevant condition directly out of
- the simd flags. This is much cheaper (on P3/P4/Athlon) than
- copying them back to the real flags via popf. Notice that
- some of these sequences trash %eax, but that should be free
- now since this is the end of a bb and therefore all regs are
- dead. */
- simd = False;
-
- switch (cond) {
-
- case CondLE: /* Z || S != O -> S || !P */
- case CondNLE: /* !Z && S == O -> !S && P */
- vg_assert(eax_trashable);
-
- VG_(emit_movv_offregmem_reg)
- ( 4, VGOFF_(m_eflags) * 4, R_EBP, R_EAX );
- /* eax == %EFLAGS */
-
- VG_(emit_nonshiftopv_lit_reg)
- ( False, 4, AND, EFlagO|EFlagS|EFlagZ, R_EAX );
- /* eax just contains OF, SF and ZF */
-
- VG_(emit_shiftopv_lit_reg)( False, 4, ROR, 7, R_EAX );
- /* eax has OF and SF in lower 8 bits, and ZF in MSB */
-
- /* actually set the real cpu flags, since ROR changes
- neither P nor Z */
- VG_(emit_nonshiftopv_reg_reg)( False, 4, OR, R_EAX, R_EAX );
-
- if (cond == CondLE) {
- /* test Z */
- VG_(emit_jcondshort_target)(False, CondS, &tgt_jump, JP_NONE);
- /* test OF != SF */
- cond = CondP;
- } else {
- /* test Z */
- VG_(emit_jcondshort_target)(False, CondS, &tgt2, JP_NONE);
- /* test OF == SF */
- cond = CondNP;
- }
- break;
-
- case CondL:
- case CondNL:
- vg_assert(eax_trashable);
-
- VG_(emit_movv_offregmem_reg)
- ( 4, VGOFF_(m_eflags) * 4, R_EBP, R_EAX );
- /* eax == %EFLAGS */
-
- VG_(emit_shiftopv_lit_reg)( False, 4, SHR, 7, R_EAX );
- /* eax has OF and SF in lower byte */
-
- VG_(emit_testb_lit_reg) ( False, 0x11, R_EAX);
- /* PF = OF == SF */
-
- /* Testing P now is OK since SHR sets it */
- if (cond == CondL) cond = CondP; else cond = CondNP;
- break;
-
- case CondB:
- case CondNB:
- mask = EFlagC; goto simple; /* C=1 */
-
- case CondZ:
- case CondNZ:
- mask = EFlagZ; goto simple; /* Z=1 */
-
- case CondBE:
- case CondNBE:
- mask = EFlagC | EFlagZ; goto simple; /* C=1 || Z=1 */
-
- case CondS:
- case CondNS:
- mask = EFlagS; goto simple; /* S=1 */
-
- case CondP:
- case CondNP:
- mask = EFlagP; goto simple; /* P=1 */
-
- case CondO:
- case CondNO:
- mask = EFlagO; goto simple; /* O=1 */
-
- default:
- VG_(printf)("synth_jcond_lit: unhandled simd case %d (%s)\n",
- (Int)cond, VG_(name_UCondcode)(cond) );
- VG_(core_panic)("synth_jcond_lit: unhandled simd case");
-
- simple:
- VG_(new_emit)(False, False, FlagsOSZACP);
- if ((mask & 0xff) == mask) {
- VG_(emitB) ( 0xF6 ); /* Grp3 */
- VG_(emit_amode_offregmem_reg)(
- VGOFF_(m_eflags) * 4, R_EBP, 0 /* subcode for TEST */);
- VG_(emitB) (mask);
- if (dis)
- VG_(printf)("\n\t\ttestb $0x%x, %d(%%ebp)\n",
- mask, VGOFF_(m_eflags) * 4);
- } else {
- /* all cond codes are in lower 16 bits */
- vg_assert((mask & 0xffff) == mask);
-
- VG_(emitB) ( 0x66 );
- VG_(emitB) ( 0xF7 );
- VG_(emit_amode_offregmem_reg)(
- VGOFF_(m_eflags) * 4, R_EBP, 0 /* subcode for TEST */);
- VG_(emitW) (mask);
- if (dis)
- VG_(printf)("\n\t\ttestl $0x%x, %d(%%ebp)\n",
- mask, VGOFF_(m_eflags) * 4);
- }
-
- cond = (parity ? CondP : CondZ) | (cond & 1);
- break;
- }
- }
-
- VG_(emit_jcondshort_target) ( simd, cond, &tgt, JP_NONE );
-
- VG_(target_forward)(&tgt_jump);
- synth_jmp_lit ( addr, JmpBoring );
-
- VG_(target_forward)(&tgt);
- VG_(target_forward)(&tgt2);
-}
-
-
-
-static void synth_jmp_ifzero_reg_lit ( Int reg, Addr addr )
-{
- Int tgt;
-
- VG_(init_target)(&tgt);
-
- VG_(emit_cmpl_zero_reg) ( False, reg );
-
- VG_(emit_jcondshort_target) ( False, CondNZ, &tgt, JP_NONE );
- synth_jmp_lit ( addr, JmpBoring );
-
- VG_(target_forward)(&tgt);
-}
-
-
-static void synth_mov_lit_reg ( Int size, UInt lit, Int reg )
-{
- /* Load the zero-extended literal into reg, at size l,
- regardless of the request size. */
- VG_(emit_movv_lit_reg) ( 4, lit, reg );
-}
-
-
-static void synth_mov_regmem_reg ( Int size, Int reg1, Int reg2 )
-{
- switch (size & ~DO_BOUNDSCHECK) {
- case 4: emit_movv_regmem_reg ( size, reg1, reg2 ); break;
- case 2: VG_(emit_movzwl_regmem_reg) ( size & DO_BOUNDSCHECK, reg1, reg2 ); break;
- case 1: emit_movzbl_regmem_reg ( size & DO_BOUNDSCHECK, reg1, reg2 ); break;
- default: VG_(core_panic)("synth_mov_regmem_reg");
- }
-}
-
-
-static void synth_mov_offregmem_reg ( Int size, Int off, Int areg, Int reg )
-{
- switch (size & ~DO_BOUNDSCHECK) {
- case 4: VG_(emit_movv_offregmem_reg) ( 4, off, areg, reg ); break;
- case 2: VG_(emit_movzwl_offregmem_reg) ( size & DO_BOUNDSCHECK, off, areg, reg ); break;
- case 1: VG_(emit_movzbl_offregmem_reg) ( size & DO_BOUNDSCHECK, off, areg, reg ); break;
- default: VG_(core_panic)("synth_mov_offregmem_reg");
- }
-}
-
-
-static void synth_mov_reg_offregmem ( Int size, Int reg,
- Int off, Int areg )
-{
- switch (size) {
- case 4: VG_(emit_movv_reg_offregmem) ( 4, reg, off, areg ); break;
- case 2: VG_(emit_movv_reg_offregmem) ( 2, reg, off, areg ); break;
- case 1: if (reg < 4) {
- VG_(emit_movb_reg_offregmem) ( reg, off, areg );
- }
- else {
- VG_(emit_swapl_reg_EAX) ( reg );
- VG_(emit_movb_reg_offregmem) ( R_AL, off, areg );
- VG_(emit_swapl_reg_EAX) ( reg );
- }
- break;
- default: VG_(core_panic)("synth_mov_reg_offregmem");
- }
-}
-
-
-static void synth_mov_reg_memreg ( Int size, Int reg1, Int reg2 )
-{
- Int s1;
- switch (size & ~DO_BOUNDSCHECK) {
- case 4:
- case 2: emit_movv_reg_regmem ( size, reg1, reg2 ); break;
- case 1: if (reg1 < 4) {
- emit_movb_reg_regmem ( size & DO_BOUNDSCHECK, reg1, reg2 );
- }
- else {
- /* Choose a swap reg which is < 4 and not reg1 or reg2. */
- for (s1 = 0; s1 == reg1 || s1 == reg2; s1++) ;
- emit_swapl_reg_reg ( s1, reg1 );
- emit_movb_reg_regmem ( size & DO_BOUNDSCHECK, s1, reg2 );
- emit_swapl_reg_reg ( s1, reg1 );
- }
- break;
- default: VG_(core_panic)("synth_mov_reg_litmem");
- }
-}
-
-
-static void synth_unaryop_reg ( Bool simd_flags,
- Opcode opcode, Int size,
- Int reg )
-{
- /* NB! opcode is a uinstr opcode, not an x86 one! */
- switch (size) {
- case 4: VG_(emit_unaryopv_reg) ( simd_flags, 4, opcode, reg );
- break;
- case 2: VG_(emit_unaryopv_reg) ( simd_flags, 2, opcode, reg );
- break;
- case 1: if (reg < 4) {
- VG_(emit_unaryopb_reg) ( simd_flags, opcode, reg );
- } else {
- VG_(emit_swapl_reg_EAX) ( reg );
- VG_(emit_unaryopb_reg) ( simd_flags, opcode, R_AL );
- VG_(emit_swapl_reg_EAX) ( reg );
- }
- break;
- default: VG_(core_panic)("synth_unaryop_reg");
- }
-}
-
-
-
-static void synth_nonshiftop_reg_reg ( Bool simd_flags,
- Opcode opcode, Int size,
- Int reg1, Int reg2 )
-{
- /* NB! opcode is a uinstr opcode, not an x86 one! */
- switch (size) {
- case 4: VG_(emit_nonshiftopv_reg_reg) ( simd_flags, 4, opcode, reg1, reg2 );
- break;
- case 2: VG_(emit_nonshiftopv_reg_reg) ( simd_flags, 2, opcode, reg1, reg2 );
- break;
- case 1: { /* Horrible ... */
- Int s1, s2;
- /* Choose s1 and s2 to be x86 regs which we can talk about the
- lowest 8 bits, ie either %eax, %ebx, %ecx or %edx. Make
- sure s1 != s2 and that neither of them equal either reg1 or
- reg2. Then use them as temporaries to make things work. */
- if (reg1 < 4 && reg2 < 4) {
- emit_nonshiftopb_reg_reg(simd_flags, opcode, reg1, reg2);
- break;
- }
- for (s1 = 0; s1 == reg1 || s1 == reg2; s1++) ;
- if (reg1 >= 4 && reg2 < 4) {
- emit_swapl_reg_reg ( reg1, s1 );
- emit_nonshiftopb_reg_reg(simd_flags, opcode, s1, reg2);
- emit_swapl_reg_reg ( reg1, s1 );
- break;
- }
- for (s2 = 0; s2 == reg1 || s2 == reg2 || s2 == s1; s2++) ;
- if (reg1 < 4 && reg2 >= 4) {
- emit_swapl_reg_reg ( reg2, s2 );
- emit_nonshiftopb_reg_reg(simd_flags, opcode, reg1, s2);
- emit_swapl_reg_reg ( reg2, s2 );
- break;
- }
- if (reg1 >= 4 && reg2 >= 4 && reg1 != reg2) {
- emit_swapl_reg_reg ( reg1, s1 );
- emit_swapl_reg_reg ( reg2, s2 );
- emit_nonshiftopb_reg_reg(simd_flags, opcode, s1, s2);
- emit_swapl_reg_reg ( reg1, s1 );
- emit_swapl_reg_reg ( reg2, s2 );
- break;
- }
- if (reg1 >= 4 && reg2 >= 4 && reg1 == reg2) {
- emit_swapl_reg_reg ( reg1, s1 );
- emit_nonshiftopb_reg_reg(simd_flags, opcode, s1, s1);
- emit_swapl_reg_reg ( reg1, s1 );
- break;
- }
- VG_(core_panic)("synth_nonshiftopb_reg_reg");
- }
- default: VG_(core_panic)("synth_nonshiftop_reg_reg");
- }
-}
-
-#if 0
-/* evidently unused */
-static void synth_nonshiftop_reg_offregmem (
- Bool simd_flags,
- Opcode opcode, Int size,
- Int off, Int areg, Int reg )
-{
- switch (size) {
- case 4:
- emit_nonshiftopv_reg_offregmem ( simd_flags, 4, opcode, off, areg, reg );
- break;
- case 2:
- emit_nonshiftopv_reg_offregmem ( simd_flags, 2, opcode, off, areg, reg );
- break;
- case 1:
- if (reg < 4) {
- emit_nonshiftopb_reg_offregmem ( simd_flags, opcode, off, areg, reg );
- } else {
- VG_(emit_swapl_reg_EAX) ( reg );
- emit_nonshiftopb_reg_offregmem ( simd_flags, opcode, off, areg, R_AL );
- VG_(emit_swapl_reg_EAX) ( reg );
- }
- break;
- default:
- VG_(core_panic)("synth_nonshiftop_reg_offregmem");
- }
-}
-#endif
-
-static void synth_nonshiftop_offregmem_reg (
- Bool simd_flags,
- Opcode opcode, Int size,
- Int off, Int areg, Int reg )
-{
- switch (size) {
- case 4:
- emit_nonshiftopv_offregmem_reg ( simd_flags, 4, opcode, off, areg, reg );
- break;
- case 2:
- emit_nonshiftopv_offregmem_reg ( simd_flags, 2, opcode, off, areg, reg );
- break;
- case 1:
- if (reg < 4) {
- emit_nonshiftopb_offregmem_reg ( simd_flags, opcode, off, areg, reg );
- } else {
- VG_(emit_swapl_reg_EAX) ( reg );
- emit_nonshiftopb_offregmem_reg ( simd_flags, opcode, off, areg, R_AL );
- VG_(emit_swapl_reg_EAX) ( reg );
- }
- break;
- default:
- VG_(core_panic)("synth_nonshiftop_offregmem_reg");
- }
-}
-
-
-static void synth_nonshiftop_lit_reg ( Bool simd_flags,
- Opcode opcode, Int size,
- UInt lit, Int reg )
-{
- switch (size) {
- case 4: VG_(emit_nonshiftopv_lit_reg) ( simd_flags, 4, opcode, lit, reg );
- break;
- case 2: VG_(emit_nonshiftopv_lit_reg) ( simd_flags, 2, opcode, lit, reg );
- break;
- case 1: if (reg < 4) {
- emit_nonshiftopb_lit_reg ( simd_flags, opcode, lit, reg );
- } else {
- VG_(emit_swapl_reg_EAX) ( reg );
- emit_nonshiftopb_lit_reg ( simd_flags, opcode, lit, R_AL );
- VG_(emit_swapl_reg_EAX) ( reg );
- }
- break;
- default: VG_(core_panic)("synth_nonshiftop_lit_reg");
- }
-}
-
-static void synth_nonshiftop_lit_offregmem ( Bool simd_flags,
- Opcode opcode, Int size,
- UInt lit, Int off, Int regmem )
-{
- switch (size) {
- case 4: VG_(emit_nonshiftopv_lit_offregmem) ( simd_flags, 4, opcode, lit, off, regmem );
- break;
- case 2: VG_(emit_nonshiftopv_lit_offregmem) ( simd_flags, 2, opcode, lit, off, regmem );
- break;
- case 1: emit_nonshiftopb_lit_offregmem ( simd_flags, opcode, lit, off, regmem );
- break;
- default: VG_(core_panic)("synth_nonshiftop_lit_offregmem");
- }
-}
-
-
-static void synth_mul_reg_reg ( Bool upd_cc,
- Opcode opcode, Int size,
- Int reg1, Int reg2 )
-{
- VG_(new_emit)(upd_cc, FlagsEmpty, FlagsOSZACP);
-
- switch (size) {
- case 2:
- VG_(emitB)(0x66);
- /* FALLTHROUGH */
- case 4:
- VG_(emitB)(0x0F);
- VG_(emitB)(0xAF);
- VG_(emit_amode_ereg_greg)(reg1, reg2);
- break;
-
- case 1:
- VG_(core_panic)("can't do byte mul");
- break;
- }
- if (dis)
- VG_(printf)("\n\t\timul%c\t%s, %s\n",
- nameISize(size),
- nameIReg(size, reg1),
- nameIReg(size, reg2));
-}
-
-static void synth_mul_lit_reg ( Bool upd_cc,
- Opcode opcode, Int size,
- UInt lit, Int reg )
-{
- VG_(new_emit)(upd_cc, FlagsEmpty, FlagsOSZACP);
-
- switch (size) {
- case 2:
- VG_(emitB)(0x66);
- /* FALLTHROUGH */
- case 4:
- VG_(emitB)(0x69);
- VG_(emit_amode_ereg_greg)(reg, 0);
- if (size == 2)
- VG_(emitW)(lit);
- else
- VG_(emitL)(lit);
- break;
-
- case 1:
- VG_(core_panic)("can't do byte mul");
- break;
- }
- if (dis)
- VG_(printf)("\n\t\timul%c\t%d, %s\n",
- nameISize(size),
- lit,
- nameIReg(size, reg));
-}
-
-static void synth_mul_offregmem_reg (
- Bool upd_cc,
- Opcode opcode, Int size,
- Int off, Int areg, Int reg )
-{
- VG_(new_emit)(upd_cc, FlagsEmpty, FlagsOSZACP);
-
- switch(size) {
- case 2:
- VG_(emitB)(0x66);
- /* FALLTHROUGH */
- case 4:
- VG_(emitB)(0x0F);
- VG_(emitB)(0xAF);
- VG_(emit_amode_offregmem_reg)(off, areg, reg);
- break;
-
- case 1:
- VG_(core_panic)("can't do byte mul");
- }
-
- if (dis)
- VG_(printf)("\n\t\timul%c\t0x%x(%s), %s\n",
- nameISize(size), off, nameIReg(4,areg),nameIReg(size,reg));
-
-}
-
-
-static void synth_push_reg ( Int size, Int reg )
-{
- switch (size) {
- case 4:
- VG_(emit_pushv_reg) ( 4, reg );
- break;
- case 2:
- VG_(emit_pushv_reg) ( 2, reg );
- break;
- /* Pray that we don't have to generate this really cruddy bit of
- code very often. Could do better, but can I be bothered? */
- case 1:
- vg_assert(reg != R_ESP); /* duh */
- VG_(emit_add_lit_to_esp)(-1);
- if (reg != R_EAX) VG_(emit_swapl_reg_EAX) ( reg );
- emit_movb_AL_zeroESPmem();
- if (reg != R_EAX) VG_(emit_swapl_reg_EAX) ( reg );
- break;
- default:
- VG_(core_panic)("synth_push_reg");
- }
-}
-
-
-static void synth_pop_reg ( Int size, Int reg )
-{
- switch (size) {
- case 4:
- VG_(emit_popv_reg) ( 4, reg );
- break;
- case 2:
- VG_(emit_popv_reg) ( 2, reg );
- break;
- case 1:
- /* Same comment as above applies. */
- vg_assert(reg != R_ESP); /* duh */
- if (reg != R_EAX) VG_(emit_swapl_reg_EAX) ( reg );
- emit_movb_zeroESPmem_AL();
- if (reg != R_EAX) VG_(emit_swapl_reg_EAX) ( reg );
- VG_(emit_add_lit_to_esp)(1);
- break;
- default: VG_(core_panic)("synth_pop_reg");
- }
-}
-
-
-static void synth_shiftop_reg_reg ( Bool simd_flags,
- Opcode opcode, Int size,
- Int regs, Int regd )
-{
- synth_push_reg ( size, regd );
- if (regs != R_ECX) emit_swapl_reg_ECX ( regs );
- switch (size) {
- case 4: emit_shiftopv_cl_stack0 ( simd_flags, 4, opcode ); break;
- case 2: emit_shiftopv_cl_stack0 ( simd_flags, 2, opcode ); break;
- case 1: emit_shiftopb_cl_stack0 ( simd_flags, opcode ); break;
- default: VG_(core_panic)("synth_shiftop_reg_reg");
- }
- if (regs != R_ECX) emit_swapl_reg_ECX ( regs );
- synth_pop_reg ( size, regd );
-}
-
-
-static void synth_shiftop_lit_reg ( Bool simd_flags,
- Opcode opcode, Int size,
- UInt lit, Int reg )
-{
- switch (size) {
- case 4: VG_(emit_shiftopv_lit_reg) ( simd_flags, 4, opcode, lit, reg );
- break;
- case 2: VG_(emit_shiftopv_lit_reg) ( simd_flags, 2, opcode, lit, reg );
- break;
- case 1: if (reg < 4) {
- emit_shiftopb_lit_reg ( simd_flags, opcode, lit, reg );
- } else {
- VG_(emit_swapl_reg_EAX) ( reg );
- emit_shiftopb_lit_reg ( simd_flags, opcode, lit, R_AL );
- VG_(emit_swapl_reg_EAX) ( reg );
- }
- break;
- default: VG_(core_panic)("synth_shiftop_lit_reg");
- }
-}
-
-
-static void synth_setb_reg ( Bool simd, Int reg, Condcode cond )
-{
- if (reg < 4) {
- emit_setb_reg ( simd, reg, cond );
- } else {
- VG_(emit_swapl_reg_EAX) ( reg );
- emit_setb_reg ( simd, R_AL, cond );
- VG_(emit_swapl_reg_EAX) ( reg );
- }
-}
-
-
-static void synth_MMX2_regmem ( Bool uses_flags, Bool sets_flags,
- UChar first_byte,
- UChar second_byte,
- Int ireg )
-{
- emit_MMX2_regmem ( uses_flags, sets_flags,
- first_byte, second_byte, ireg );
-}
-
-
-static void synth_MMX2a1 ( Bool uses_flags, Bool sets_flags,
- UChar first_byte,
- UChar second_byte,
- UChar third_byte,
- Int ireg )
-{
- emit_MMX2a1 ( uses_flags, sets_flags,
- first_byte, second_byte, third_byte, ireg );
-}
-
-
-static void synth_MMX2_reg_to_mmxreg ( Bool uses_flags, Bool sets_flags,
- UChar first_byte,
- UChar second_byte,
- Int ireg )
-{
- emit_MMX2_reg_to_mmxreg ( uses_flags, sets_flags,
- first_byte, second_byte, ireg );
-}
-
-static void synth_MMX2_mmxreg_to_reg ( Bool uses_flags, Bool sets_flags,
- UChar first_byte,
- UChar second_byte,
- Int ireg )
-{
- emit_MMX2_mmxreg_to_reg ( uses_flags, sets_flags,
- first_byte, second_byte, ireg );
-}
-
-static void synth_MMX2_no_mem ( Bool uses_flags, Bool sets_flags,
- UChar first_byte,
- UChar second_byte )
-{
- emit_MMX2_no_mem ( uses_flags, sets_flags, first_byte, second_byte );
-}
-
-
-static void synth_MMX3_no_mem ( Bool uses_flags, Bool sets_flags,
- UChar first_byte,
- UChar second_byte,
- UChar third_byte )
-{
- emit_MMX3_no_mem ( uses_flags, sets_flags,
- first_byte, second_byte, third_byte );
-}
-
-
-static void synth_MMX1_no_mem ( Bool uses_flags, Bool sets_flags,
- UChar first_byte )
-{
- emit_MMX1_no_mem ( uses_flags, sets_flags, first_byte );
-}
-
-
-static void synth_fpu_regmem ( Bool uses_flags, Bool sets_flags,
- UChar first_byte,
- UChar second_byte_masked,
- Int reg )
-{
- emit_fpu_regmem ( uses_flags, sets_flags,
- first_byte, second_byte_masked, reg );
-}
-
-
-static void synth_fpu_no_mem ( Bool uses_flags, Bool sets_flags,
- UChar first_byte,
- UChar second_byte )
-{
- emit_fpu_no_mem ( uses_flags, sets_flags, first_byte, second_byte );
-}
-
-
-static void synth_movl_reg_reg ( Int src, Int dst )
-{
- emit_movl_reg_reg ( src, dst );
-}
-
-static void synth_cmovl_reg_reg ( Condcode cond, Int src, Int dst )
-{
- Int tgt;
-
- VG_(init_target)(&tgt);
-
- VG_(emit_jcondshort_target) ( True, invertCondition(cond), &tgt, JP_NONE);
- emit_movl_reg_reg ( src, dst );
-
- VG_(target_forward)(&tgt);
-}
-
-
-/*----------------------------------------------------*/
-/*--- Top level of the uinstr -> x86 translation. ---*/
-/*----------------------------------------------------*/
-
-/* Return the byte offset from %ebp (ie, into baseBlock)
- for the specified ArchReg or SpillNo. */
-static Int spillOrArchOffset ( Int size, Tag tag, UInt value )
-{
- if (tag == SpillNo) {
- vg_assert(size == 4);
- vg_assert(value >= 0 && value < VG_MAX_SPILLSLOTS);
- return 4 * (value + VGOFF_(spillslots));
- }
- if (tag == ArchReg) {
- switch (value) {
- case R_EAX: return 4 * VGOFF_(m_eax);
- case R_ECX: return 4 * VGOFF_(m_ecx);
- case R_EDX: return 4 * VGOFF_(m_edx);
- case R_EBX: return 4 * VGOFF_(m_ebx);
- case R_ESP:
- if (size == 1) return 4 * VGOFF_(m_eax) + 1;
- else return 4 * VGOFF_(m_esp);
- case R_EBP:
- if (size == 1) return 4 * VGOFF_(m_ecx) + 1;
- else return 4 * VGOFF_(m_ebp);
- case R_ESI:
- if (size == 1) return 4 * VGOFF_(m_edx) + 1;
- else return 4 * VGOFF_(m_esi);
- case R_EDI:
- if (size == 1) return 4 * VGOFF_(m_ebx) + 1;
- else return 4 * VGOFF_(m_edi);
- }
- }
- VG_(core_panic)("spillOrArchOffset");
-}
-
-static Int eflagsOffset ( void )
-{
- return 4 * VGOFF_(m_eflags);
-}
-
-static Int segRegOffset ( UInt archregs )
-{
- switch (archregs) {
- case R_CS: return 4 * VGOFF_(m_cs);
- case R_SS: return 4 * VGOFF_(m_ss);
- case R_DS: return 4 * VGOFF_(m_ds);
- case R_ES: return 4 * VGOFF_(m_es);
- case R_FS: return 4 * VGOFF_(m_fs);
- case R_GS: return 4 * VGOFF_(m_gs);
- default: VG_(core_panic)("segRegOffset");
- }
-}
-
-UInt VG_(get_archreg) ( UInt arch )
-{
- switch (arch) {
- case R_EAX: return VG_(baseBlock)[ VGOFF_(m_eax) ];
- case R_ECX: return VG_(baseBlock)[ VGOFF_(m_ecx) ];
- case R_EDX: return VG_(baseBlock)[ VGOFF_(m_edx) ];
- case R_EBX: return VG_(baseBlock)[ VGOFF_(m_ebx) ];
- case R_ESP: return VG_(baseBlock)[ VGOFF_(m_esp) ];
- case R_EBP: return VG_(baseBlock)[ VGOFF_(m_ebp) ];
- case R_ESI: return VG_(baseBlock)[ VGOFF_(m_esi) ];
- case R_EDI: return VG_(baseBlock)[ VGOFF_(m_edi) ];
- default: VG_(core_panic)( "get_archreg");
- }
-}
-
-UInt VG_(get_thread_archreg) ( ThreadId tid, UInt arch )
-{
- ThreadState* tst;
-
- vg_assert(VG_(is_valid_tid)(tid));
- tst = & VG_(threads)[tid];
-
- switch (arch) {
- case R_EAX: return tst->arch.m_eax;
- case R_ECX: return tst->arch.m_ecx;
- case R_EDX: return tst->arch.m_edx;
- case R_EBX: return tst->arch.m_ebx;
- case R_ESP: return tst->arch.m_esp;
- case R_EBP: return tst->arch.m_ebp;
- case R_ESI: return tst->arch.m_esi;
- case R_EDI: return tst->arch.m_edi;
- default: VG_(core_panic)( "get_thread_archreg");
- }
-}
-
-/* Return the baseBlock index for the specified shadow register */
-static Int shadow_reg_index ( Int arch )
-{
- switch (arch) {
- case R_EAX: return VGOFF_(sh_eax);
- case R_ECX: return VGOFF_(sh_ecx);
- case R_EDX: return VGOFF_(sh_edx);
- case R_EBX: return VGOFF_(sh_ebx);
- case R_ESP: return VGOFF_(sh_esp);
- case R_EBP: return VGOFF_(sh_ebp);
- case R_ESI: return VGOFF_(sh_esi);
- case R_EDI: return VGOFF_(sh_edi);
- default: VG_(core_panic)( "shadow_reg_index");
- }
-}
-
-/* Return the byte offset from %ebp (ie, into baseBlock)
- for the specified shadow register */
-Int VG_(shadow_reg_offset) ( Int arch )
-{
- return 4 * shadow_reg_index ( arch );
-}
-
-Int VG_(shadow_flags_offset) ( void )
-{
- return 4 * VGOFF_(sh_eflags);
-}
-
-/* Accessing shadow arch. registers */
-UInt VG_(get_shadow_archreg) ( UInt archreg )
-{
- return VG_(baseBlock)[ shadow_reg_index(archreg) ];
-}
-
-void VG_(set_shadow_archreg) ( UInt archreg, UInt val )
-{
- VG_(baseBlock)[ shadow_reg_index(archreg) ] = val;
-}
-
-void VG_(set_shadow_eflags) ( UInt val )
-{
- VG_(baseBlock)[ VGOFF_(sh_eflags) ] = val;
-}
-
-UInt VG_(get_thread_shadow_archreg) ( ThreadId tid, UInt archreg )
-{
- ThreadState* tst;
-
- vg_assert(VG_(is_valid_tid)(tid));
- tst = & VG_(threads)[tid];
-
- switch (archreg) {
- case R_EAX: return tst->arch.sh_eax;
- case R_ECX: return tst->arch.sh_ecx;
- case R_EDX: return tst->arch.sh_edx;
- case R_EBX: return tst->arch.sh_ebx;
- case R_ESP: return tst->arch.sh_esp;
- case R_EBP: return tst->arch.sh_ebp;
- case R_ESI: return tst->arch.sh_esi;
- case R_EDI: return tst->arch.sh_edi;
- default: VG_(core_panic)( "get_thread_shadow_archreg");
- }
-}
-
-void VG_(set_thread_shadow_archreg) ( ThreadId tid, UInt archreg, UInt val )
-{
- ThreadState* tst;
-
- vg_assert(VG_(is_valid_tid)(tid));
- tst = & VG_(threads)[tid];
-
- switch (archreg) {
- case R_EAX: tst->arch.sh_eax = val; break;
- case R_ECX: tst->arch.sh_ecx = val; break;
- case R_EDX: tst->arch.sh_edx = val; break;
- case R_EBX: tst->arch.sh_ebx = val; break;
- case R_ESP: tst->arch.sh_esp = val; break;
- case R_EBP: tst->arch.sh_ebp = val; break;
- case R_ESI: tst->arch.sh_esi = val; break;
- case R_EDI: tst->arch.sh_edi = val; break;
- default: VG_(core_panic)( "set_thread_shadow_archreg");
- }
-}
-
-Addr VG_(shadow_archreg_address) ( UInt archreg )
-{
- return (Addr) & VG_(baseBlock)[ shadow_reg_index(archreg) ];
-}
-
-static void synth_WIDEN_signed ( Int sz_src, Int sz_dst, Int reg )
-{
- if (sz_src == 1 && sz_dst == 4) {
- VG_(emit_shiftopv_lit_reg) ( False, 4, SHL, 24, reg );
- VG_(emit_shiftopv_lit_reg) ( False, 4, SAR, 24, reg );
- }
- else if (sz_src == 2 && sz_dst == 4) {
- VG_(emit_shiftopv_lit_reg) ( False, 4, SHL, 16, reg );
- VG_(emit_shiftopv_lit_reg) ( False, 4, SAR, 16, reg );
- }
- else if (sz_src == 1 && sz_dst == 2) {
- VG_(emit_shiftopv_lit_reg) ( False, 2, SHL, 8, reg );
- VG_(emit_shiftopv_lit_reg) ( False, 2, SAR, 8, reg );
- }
- else
- VG_(core_panic)("synth_WIDEN");
-}
-
-
-/*----------------------------------------------------*/
-/*--- Generate code for a single UInstr. ---*/
-/*----------------------------------------------------*/
-
-static __inline__
-Bool writeFlagUse ( UInstr* u )
-{
- return (u->flags_w != FlagsEmpty);
-}
-
-static __inline__
-Bool readFlagUse ( UInstr* u )
-{
- /* If the UInstr writes some flags but not all, then we still need
- to consider it as reading flags so that the unchanged values are
- passed through properly. (D is special) */
- return
- (u->flags_r != FlagsEmpty) ||
- (u->flags_w != FlagsEmpty && u->flags_w != FlagsOSZACP) ;
-}
-
-static __inline__
-Bool anyFlagUse ( UInstr* u )
-{
- return readFlagUse(u) || writeFlagUse(u);
-}
-
-
-/* *fplive==True indicates that the simulated machine's FPU/SSE state is in
- the real machine's cpu. If so we need to be very careful not to trash it.
- If FPU/SSE state is live and we deem it necessary to copy it back to
- the simulated machine's FPU/SSE state, we do so. The final state of
- fpliveness is returned. In short we _must_ do put_sse_state if
- there is any chance at all that the code generated for a UInstr
- will change the real FPU/MMX/SSE/SSE2 state.
-*/
-static void emitUInstr ( UCodeBlock* cb, Int i,
- RRegSet regs_live_before,
- /* Running state, which we update. */
- Bool* sselive, /* True<==>FPU/SSE
- state in real FPU */
- Addr* orig_eip, /* previous curr_eip, or zero */
- Addr* curr_eip ) /* current eip */
-{
- Int old_emitted_code_used;
- UInstr* u = &cb->instrs[i];
-
- if (dis)
- VG_(pp_UInstr_regs)(i, u);
-
- old_emitted_code_used = emitted_code_used;
-
- switch (u->opcode) {
- case NOP: case LOCK: case CALLM_S: case CALLM_E: break;
-
- case INCEIP:
- /* Advance %EIP some small amount. */
- *curr_eip += (UInt)(u->val1);
-
- if (*orig_eip == 0 /* we don't know what the old value was */
- || ((*orig_eip & ~0xFF) != (*curr_eip & ~0xFF))) {
- /* We have to update all 32 bits of the value. */
- VG_(emit_movv_lit_offregmem)(
- 4, *curr_eip, 4*VGOFF_(m_eip), R_EBP);
- } else {
- /* Cool! we only need to update lowest 8 bits */
- VG_(emit_movb_lit_offregmem)(
- *curr_eip & 0xFF, 4*VGOFF_(m_eip)+0, R_EBP);
- }
-
- *orig_eip = *curr_eip;
- break;
-
- case LEA1: {
- vg_assert(u->tag1 == RealReg);
- vg_assert(u->tag2 == RealReg);
- emit_lea_litreg_reg ( u->lit32, u->val1, u->val2 );
- break;
- }
-
- case LEA2: {
- vg_assert(u->tag1 == RealReg);
- vg_assert(u->tag2 == RealReg);
- vg_assert(u->tag3 == RealReg);
- emit_lea_sib_reg ( u->lit32, u->extra4b,
- u->val1, u->val2, u->val3 );
- break;
- }
-
- case WIDEN: {
- vg_assert(u->tag1 == RealReg);
- if (u->signed_widen) {
- synth_WIDEN_signed ( u->extra4b, u->size, u->val1 );
- } else {
- /* no need to generate any code. */
- }
- break;
- }
-
- case STORE: {
- vg_assert(u->tag1 == RealReg);
- vg_assert(u->tag2 == RealReg);
- synth_mov_reg_memreg ( u->size | DO_BOUNDSCHECK, u->val1, u->val2 );
- break;
- }
-
- case LOAD: {
- vg_assert(u->tag1 == RealReg);
- vg_assert(u->tag2 == RealReg);
- synth_mov_regmem_reg ( u->size | DO_BOUNDSCHECK, u->val1, u->val2 );
- break;
- }
-
- case GET: {
- vg_assert(u->tag1 == ArchReg || u->tag1 == SpillNo);
- vg_assert(u->tag2 == RealReg);
- synth_mov_offregmem_reg (
- u->size,
- spillOrArchOffset( u->size, u->tag1, u->val1 ),
- R_EBP,
- u->val2
- );
- break;
- }
-
- case PUT: {
- vg_assert(u->tag2 == ArchReg || u->tag2 == SpillNo);
- vg_assert(u->tag1 == RealReg);
- synth_mov_reg_offregmem (
- u->size,
- u->val1,
- spillOrArchOffset( u->size, u->tag2, u->val2 ),
- R_EBP
- );
- break;
- }
-
- case GETSEG: {
- vg_assert(u->tag1 == ArchRegS);
- vg_assert(u->tag2 == RealReg);
- vg_assert(u->size == 2);
- synth_mov_offregmem_reg (
- 4,
- segRegOffset( u->val1 ),
- R_EBP,
- u->val2
- );
- break;
- }
-
- case PUTSEG: {
- vg_assert(u->tag1 == RealReg);
- vg_assert(u->tag2 == ArchRegS);
- vg_assert(u->size == 2);
- synth_mov_reg_offregmem (
- 4,
- u->val1,
- segRegOffset( u->val2 ),
- R_EBP
- );
- break;
- }
-
- case GETF: {
- vg_assert(u->size == 2 || u->size == 4);
- vg_assert(u->tag1 == RealReg);
-
- /* This complexity is because the D(irection) flag is stored
- separately from the rest of EFLAGS. */
-
- /* We're only fetching from the Simd state, so make sure it's
- up to date. */
- maybe_emit_put_eflags();
-
- /* get D in u->val1 (== 1 or -1) */
- synth_mov_offregmem_reg (u->size, 4*VGOFF_(m_dflag), R_EBP, u->val1);
-
- /* u->val1 &= EFlagD (== 0 or EFlagD) */
- synth_nonshiftop_lit_reg(False, AND, u->size, EFlagD, u->val1);
-
- /* EFLAGS &= ~EFlagD (make sure there's no surprises) */
- synth_nonshiftop_lit_offregmem(False, AND, u->size, ~EFlagD,
- eflagsOffset(), R_EBP);
-
- /* EFLAGS &= ~EFlagD (make sure there's no surprises) */
- synth_nonshiftop_lit_offregmem(False, AND, u->size, ~EFlagD,
- eflagsOffset(), R_EBP);
-
- /* u->val1 |= EFLAGS (EFLAGS & EflagD == 0) */
- synth_nonshiftop_offregmem_reg(False, OR, u->size,
- eflagsOffset(), R_EBP, u->val1);
- break;
- }
-
- case PUTF: {
- vg_assert(u->size == 2 || u->size == 4);
- vg_assert(u->tag1 == RealReg);
-
- /* When putting a value into EFLAGS, this generates the
- correct value for m_dflag (-1 or 1), and clears the D bit
- in EFLAGS. */
-
- /* We're updating the whole flag state, so the old state
- doesn't matter; make sure that the new simulated state
- will be fetched when needed. */
- eflags_state = UPD_Simd;
-
- /* store EFLAGS (with D) */
- synth_mov_reg_offregmem (u->size, u->val1, eflagsOffset(), R_EBP);
-
- /* u->val1 &= EFlagD */
- synth_nonshiftop_lit_reg(False, AND, u->size, EFlagD, u->val1);
-
- /* computes: u->val1 = (u->val1 == 0) ? 1 : -1 */
- synth_unaryop_reg(False, NEG, u->size, u->val1);
- synth_nonshiftop_reg_reg(False, SBB, u->size, u->val1, u->val1);
- synth_nonshiftop_lit_reg(False, SBB, u->size, -1, u->val1);
-
- /* save D */
- synth_mov_reg_offregmem(u->size, u->val1, 4*VGOFF_(m_dflag), R_EBP);
-
- /* EFLAGS &= ~EFlagD */
- synth_nonshiftop_lit_offregmem(False, AND, u->size, ~EFlagD,
- eflagsOffset(), R_EBP);
- break;
- }
-
- case MOV: {
- vg_assert(u->tag1 == RealReg || u->tag1 == Literal);
- vg_assert(u->tag2 == RealReg);
- switch (u->tag1) {
- case RealReg: vg_assert(u->size == 4);
- if (u->val1 != u->val2)
- synth_movl_reg_reg ( u->val1, u->val2 );
- break;
- case Literal: synth_mov_lit_reg ( u->size, u->lit32, u->val2 );
- break;
- default: VG_(core_panic)("emitUInstr:mov");
- }
- break;
- }
-
- case USESEG: {
- /* Lazy: copy all three vals; synth_ccall ignores any unnecessary
- ones. */
- UInt argv[] = { u->val1, u->val2 };
- UInt tagv[] = { RealReg, RealReg };
- UInt ret_reg = u->val2;
-
- vg_assert(u->tag1 == RealReg);
- vg_assert(u->tag2 == RealReg);
- vg_assert(u->size == 0);
-
- if (*sselive) {
- emit_put_sse_state();
- *sselive = False;
- }
-
- VG_(synth_ccall) ( (Addr) & VG_(do_useseg),
- 2, /* args */
- 0, /* regparms_n */
- argv, tagv,
- ret_reg, regs_live_before, u->regs_live_after );
- break;
- }
-
- case MUL: {
- vg_assert(u->tag2 == RealReg);
-
- switch(u->tag1) {
- case Literal:
- synth_mul_lit_reg(anyFlagUse(u),
- u->opcode, u->size, u->lit32, u->val2);
- break;
- case RealReg:
- synth_mul_reg_reg(anyFlagUse(u),
- u->opcode, u->size, u->val1, u->val2);
- break;
- case ArchReg:
- synth_mul_offregmem_reg(anyFlagUse(u),
- u->opcode, u->size,
- spillOrArchOffset(u->size, u->tag1, u->val1),
- R_EBP, u->val2);
- break;
-
- default: VG_(core_panic)("emitUInstr:MUL");
- }
- break;
- }
-
- case SBB:
- case ADC:
- case XOR:
- case OR:
- case AND:
- case SUB:
- case ADD: {
- vg_assert(u->tag2 == RealReg);
- switch (u->tag1) {
- case Literal: synth_nonshiftop_lit_reg (
- anyFlagUse(u),
- u->opcode, u->size, u->lit32, u->val2 );
- break;
- case RealReg: synth_nonshiftop_reg_reg (
- anyFlagUse(u),
- u->opcode, u->size, u->val1, u->val2 );
- break;
- case ArchReg: synth_nonshiftop_offregmem_reg (
- anyFlagUse(u),
- u->opcode, u->size,
- spillOrArchOffset( u->size, u->tag1, u->val1 ),
- R_EBP,
- u->val2 );
- break;
- default: VG_(core_panic)("emitUInstr:non-shift-op");
- }
- break;
- }
-
- case RCR:
- case RCL:
- case ROR:
- case ROL:
- case SAR:
- case SHR:
- case SHL: {
- vg_assert(u->tag2 == RealReg);
- switch (u->tag1) {
- case Literal: synth_shiftop_lit_reg (
- anyFlagUse(u),
- u->opcode, u->size, u->lit32, u->val2 );
- break;
- case RealReg: synth_shiftop_reg_reg (
- anyFlagUse(u),
- u->opcode, u->size, u->val1, u->val2 );
- break;
- default: VG_(core_panic)("emitUInstr:shift-op");
- }
- break;
- }
-
- case INC:
- case DEC:
- case NEG:
- case NOT:
- vg_assert(u->tag1 == RealReg);
- synth_unaryop_reg (
- anyFlagUse(u), u->opcode, u->size, u->val1 );
- break;
-
- case BSWAP:
- vg_assert(u->tag1 == RealReg);
- vg_assert(u->size == 4);
- vg_assert(!VG_(any_flag_use)(u));
- emit_bswapl_reg ( u->val1 );
- break;
-
- case CMOV:
- vg_assert(u->tag1 == RealReg);
- vg_assert(u->tag2 == RealReg);
- vg_assert(u->cond != CondAlways);
- vg_assert(u->size == 4);
- synth_cmovl_reg_reg ( u->cond, u->val1, u->val2 );
- break;
-
- case JMP: {
- vg_assert(u->tag2 == NoValue);
- vg_assert(u->tag1 == RealReg || u->tag1 == Literal);
- if (*sselive) {
- emit_put_sse_state();
- *sselive = False;
- }
- if (u->cond == CondAlways) {
- switch (u->tag1) {
- case RealReg:
- synth_jmp_reg ( u->val1, u->jmpkind );
- break;
- case Literal:
- synth_jmp_lit ( u->lit32, u->jmpkind );
- break;
- default:
- VG_(core_panic)("emitUInstr(JMP, unconditional, default)");
- break;
- }
- } else {
- switch (u->tag1) {
- case RealReg:
- VG_(core_panic)("emitUInstr(JMP, conditional, RealReg)");
- break;
- case Literal:
- vg_assert(u->jmpkind == JmpBoring);
- /* %eax had better not be live since synth_jcond_lit
- trashes it in some circumstances. If that turns
- out to be a problem we can get synth_jcond_lit to
- push/pop it when it is live. */
- vg_assert(! IS_RREG_LIVE(VG_(realreg_to_rank)(R_EAX),
- u->regs_live_after));
- synth_jcond_lit ( u->cond, u->lit32, True );
- break;
- default:
- VG_(core_panic)("emitUInstr(JMP, conditional, default)");
- break;
- }
- }
- break;
- }
-
- case JIFZ:
- vg_assert(u->tag1 == RealReg);
- vg_assert(u->tag2 == Literal);
- vg_assert(u->size == 4);
- if (*sselive) {
- emit_put_sse_state();
- *sselive = False;
- }
- synth_jmp_ifzero_reg_lit ( u->val1, u->lit32 );
- break;
-
- case PUSH:
- vg_assert(u->tag1 == RealReg);
- vg_assert(u->tag2 == NoValue);
- VG_(emit_pushv_reg) ( 4, u->val1 );
- break;
-
- case POP:
- vg_assert(u->tag1 == RealReg);
- vg_assert(u->tag2 == NoValue);
- VG_(emit_popv_reg) ( 4, u->val1 );
- break;
-
- case CALLM:
- vg_assert(u->tag1 == Lit16);
- vg_assert(u->tag2 == NoValue);
- vg_assert(u->size == 0);
- if (*sselive) {
- emit_put_sse_state();
- *sselive = False;
- }
- /* Call to a helper which is pretending to be a real CPU
- instruction (and therefore operates on Real flags and
- registers) */
- VG_(synth_call) ( False, u->val1,
- True, u->flags_r, u->flags_w );
- break;
-
- case CCALL: {
- /* If you change this, remember to change USESEG above, since
- that's just a copy of this, slightly simplified. */
- /* Lazy: copy all three vals; synth_ccall ignores any unnecessary
- ones. */
- UInt argv[] = { u->val1, u->val2, u->val3 };
- UInt tagv[] = { RealReg, RealReg, RealReg };
- UInt ret_reg = ( u->has_ret_val ? u->val3 : INVALID_REALREG );
-
- if (u->argc >= 1) vg_assert(u->tag1 == RealReg);
- else vg_assert(u->tag1 == NoValue);
- if (u->argc >= 2) vg_assert(u->tag2 == RealReg);
- else vg_assert(u->tag2 == NoValue);
- if (u->argc == 3 || u->has_ret_val) vg_assert(u->tag3 == RealReg);
- else vg_assert(u->tag3 == NoValue);
- vg_assert(u->size == 0);
-
- if (*sselive) {
- emit_put_sse_state();
- *sselive = False;
- }
- VG_(synth_ccall) ( u->lit32, u->argc, u->regparms_n, argv, tagv,
- ret_reg, regs_live_before, u->regs_live_after );
- break;
- }
-
- case CLEAR:
- vg_assert(u->tag1 == Lit16);
- vg_assert(u->tag2 == NoValue);
- VG_(emit_add_lit_to_esp) ( u->val1 );
- break;
-
- case CC2VAL:
- vg_assert(u->tag1 == RealReg);
- vg_assert(u->tag2 == NoValue);
- vg_assert(VG_(any_flag_use)(u));
- synth_setb_reg ( True, u->val1, u->cond );
- break;
-
- case FPU_R:
- case FPU_W:
- vg_assert(u->tag1 == Lit16);
- vg_assert(u->tag2 == RealReg);
- if (!(*sselive)) {
- emit_get_sse_state();
- *sselive = True;
- }
- synth_fpu_regmem ( u->flags_r, u->flags_w,
- (u->val1 >> 8) & 0xFF,
- u->val1 & 0xFF,
- u->val2 );
- break;
-
- case FPU:
- vg_assert(u->tag1 == Lit16);
- vg_assert(u->tag2 == NoValue);
- if (!(*sselive)) {
- emit_get_sse_state();
- *sselive = True;
- }
- synth_fpu_no_mem ( u->flags_r, u->flags_w,
- (u->val1 >> 8) & 0xFF,
- u->val1 & 0xFF );
- break;
-
- case MMX2_MemWr:
- case MMX2_MemRd:
- vg_assert(u->size == 4 || u->size == 8);
- vg_assert(u->tag1 == Lit16);
- vg_assert(u->tag2 == RealReg);
- vg_assert(u->tag3 == NoValue);
- vg_assert(!anyFlagUse(u));
- if (!(*sselive)) {
- emit_get_sse_state();
- *sselive = True;
- }
- synth_MMX2_regmem ( u->flags_r, u->flags_w,
- (u->val1 >> 8) & 0xFF,
- u->val1 & 0xFF,
- u->val2 );
- break;
-
- case MMX2a1_MemRd:
- vg_assert(u->size == 8);
- vg_assert(u->tag1 == Lit16);
- vg_assert(u->tag2 == Lit16);
- vg_assert(u->tag3 == RealReg);
- vg_assert(!anyFlagUse(u));
- if (!(*sselive)) {
- emit_get_sse_state();
- *sselive = True;
- }
- synth_MMX2a1 ( u->flags_r, u->flags_w,
- (u->val1 >> 8) & 0xFF,
- u->val1 & 0xFF,
- u->val2 & 0xFF,
- u->val3 );
- break;
-
- case MMX2_ERegRd:
- vg_assert(u->tag1 == Lit16);
- vg_assert(u->tag2 == RealReg);
- vg_assert(u->tag3 == NoValue);
- vg_assert(!anyFlagUse(u));
- if (!(*sselive)) {
- emit_get_sse_state();
- *sselive = True;
- }
- synth_MMX2_reg_to_mmxreg ( u->flags_r, u->flags_w,
- (u->val1 >> 8) & 0xFF,
- u->val1 & 0xFF,
- u->val2 );
- break;
-
- case MMX2_ERegWr:
- vg_assert(u->tag1 == Lit16);
- vg_assert(u->tag2 == RealReg);
- vg_assert(u->tag3 == NoValue);
- vg_assert(!anyFlagUse(u));
- if (!(*sselive)) {
- emit_get_sse_state();
- *sselive = True;
- }
- synth_MMX2_mmxreg_to_reg ( u->flags_r, u->flags_w,
- (u->val1 >> 8) & 0xFF,
- u->val1 & 0xFF,
- u->val2 );
- break;
-
- case MMX1:
- vg_assert(u->tag1 == Lit16);
- vg_assert(u->tag2 == NoValue);
- vg_assert(u->tag3 == NoValue);
- if (!(*sselive)) {
- emit_get_sse_state();
- *sselive = True;
- }
- synth_MMX1_no_mem ( u->flags_r, u->flags_w,
- u->val1 & 0xFF );
- break;
-
- case MMX2:
- vg_assert(u->tag1 == Lit16);
- vg_assert(u->tag2 == NoValue);
- vg_assert(u->tag3 == NoValue);
- if (!(*sselive)) {
- emit_get_sse_state();
- *sselive = True;
- }
- synth_MMX2_no_mem ( u->flags_r, u->flags_w,
- (u->val1 >> 8) & 0xFF,
- u->val1 & 0xFF );
- break;
-
- case MMX3:
- vg_assert(u->tag1 == Lit16);
- vg_assert(u->tag2 == Lit16);
- vg_assert(u->tag3 == NoValue);
- if (!(*sselive)) {
- emit_get_sse_state();
- *sselive = True;
- }
- synth_MMX3_no_mem ( u->flags_r, u->flags_w,
- (u->val1 >> 8) & 0xFF,
- u->val1 & 0xFF,
- u->val2 & 0xFF );
- break;
-
- case SSE2a_MemWr:
- case SSE2a_MemRd:
- vg_assert(u->size == 4 || u->size == 8
- || u->size == 16 || u->size == 512);
- vg_assert(u->tag1 == Lit16);
- vg_assert(u->tag2 == Lit16);
- vg_assert(u->tag3 == RealReg);
- if (!(*sselive)) {
- emit_get_sse_state();
- *sselive = True;
- }
- emit_SSE2a ( u->flags_r, u->flags_w,
- (u->val1 >> 8) & 0xFF,
- u->val1 & 0xFF,
- u->val2 & 0xFF,
- u->val3 );
- break;
-
- case SSE2g_RegWr:
- vg_assert(u->size == 4);
- vg_assert(u->tag1 == Lit16);
- vg_assert(u->tag2 == Lit16);
- vg_assert(u->tag3 == RealReg);
- vg_assert(!anyFlagUse(u));
- if (!(*sselive)) {
- emit_get_sse_state();
- *sselive = True;
- }
- emit_SSE2g ( u->flags_r, u->flags_w,
- (u->val1 >> 8) & 0xFF,
- u->val1 & 0xFF,
- u->val2 & 0xFF,
- u->val3 );
- break;
-
- case SSE2g1_RegWr:
- vg_assert(u->size == 4);
- vg_assert(u->tag1 == Lit16);
- vg_assert(u->tag2 == Lit16);
- vg_assert(u->tag3 == RealReg);
- vg_assert(!anyFlagUse(u));
- if (!(*sselive)) {
- emit_get_sse_state();
- *sselive = True;
- }
- emit_SSE2g1 ( u->flags_r, u->flags_w,
- (u->val1 >> 8) & 0xFF,
- u->val1 & 0xFF,
- u->val2 & 0xFF,
- u->lit32 & 0xFF,
- u->val3 );
- break;
-
- case SSE2e1_RegRd:
- vg_assert(u->size == 2);
- vg_assert(u->tag1 == Lit16);
- vg_assert(u->tag2 == Lit16);
- vg_assert(u->tag3 == RealReg);
- vg_assert(!anyFlagUse(u));
- if (!(*sselive)) {
- emit_get_sse_state();
- *sselive = True;
- }
- emit_SSE2e1 ( u->flags_r, u->flags_w,
- (u->val1 >> 8) & 0xFF,
- u->val1 & 0xFF,
- u->val2 & 0xFF,
- u->lit32 & 0xFF,
- u->val3 );
- break;
-
- case SSE2a1_MemRd:
- vg_assert(u->size == 4 || u->size == 8 || u->size == 16);
- vg_assert(u->tag1 == Lit16);
- vg_assert(u->tag2 == Lit16);
- vg_assert(u->tag3 == RealReg);
- vg_assert(!anyFlagUse(u));
- if (!(*sselive)) {
- emit_get_sse_state();
- *sselive = True;
- }
- emit_SSE2a1 ( u->flags_r, u->flags_w,
- (u->val1 >> 8) & 0xFF,
- u->val1 & 0xFF,
- (u->val2 >> 8) & 0xFF,
- u->val2 & 0xFF,
- u->val3 );
- break;
-
- case SSE3a_MemWr:
- case SSE3a_MemRd:
- vg_assert(u->size == 4 || u->size == 8 || u->size == 16);
- vg_assert(u->tag1 == Lit16);
- vg_assert(u->tag2 == Lit16);
- vg_assert(u->tag3 == RealReg);
- if (!(*sselive)) {
- emit_get_sse_state();
- *sselive = True;
- }
- emit_SSE3a ( u->flags_r, u->flags_w,
- (u->val1 >> 8) & 0xFF,
- u->val1 & 0xFF,
- (u->val2 >> 8) & 0xFF,
- u->val2 & 0xFF,
- u->val3 );
- break;
-
- case SSE3e_RegWr:
- case SSE3e_RegRd:
- case SSE3g_RegWr:
- vg_assert(u->size == 4);
- vg_assert(u->tag1 == Lit16);
- vg_assert(u->tag2 == Lit16);
- vg_assert(u->tag3 == RealReg);
- vg_assert(!anyFlagUse(u));
- if (!(*sselive)) {
- emit_get_sse_state();
- *sselive = True;
- }
- if (u->opcode==SSE3e_RegRd || u->opcode==SSE3e_RegWr) {
- emit_SSE3e ( u->flags_r, u->flags_w,
- (u->val1 >> 8) & 0xFF,
- u->val1 & 0xFF,
- (u->val2 >> 8) & 0xFF,
- u->val2 & 0xFF,
- u->val3 );
- } else {
- emit_SSE3g ( u->flags_r, u->flags_w,
- (u->val1 >> 8) & 0xFF,
- u->val1 & 0xFF,
- (u->val2 >> 8) & 0xFF,
- u->val2 & 0xFF,
- u->val3 );
- }
- break;
-
- case SSE3g1_RegWr:
- vg_assert(u->size == 4);
- vg_assert(u->tag1 == Lit16);
- vg_assert(u->tag2 == Lit16);
- vg_assert(u->tag3 == RealReg);
- vg_assert(!anyFlagUse(u));
- if (!(*sselive)) {
- emit_get_sse_state();
- *sselive = True;
- }
- emit_SSE3g1 ( u->flags_r, u->flags_w,
- (u->val1 >> 8) & 0xFF,
- u->val1 & 0xFF,
- (u->val2 >> 8) & 0xFF,
- u->val2 & 0xFF,
- u->lit32 & 0xFF,
- u->val3 );
- break;
-
- case SSE3e1_RegRd:
- vg_assert(u->size == 2);
- vg_assert(u->tag1 == Lit16);
- vg_assert(u->tag2 == Lit16);
- vg_assert(u->tag3 == RealReg);
- vg_assert(!anyFlagUse(u));
- if (!(*sselive)) {
- emit_get_sse_state();
- *sselive = True;
- }
- emit_SSE3e1 ( u->flags_r, u->flags_w,
- (u->val1 >> 8) & 0xFF,
- u->val1 & 0xFF,
- (u->val2 >> 8) & 0xFF,
- u->val2 & 0xFF,
- u->lit32 & 0xFF,
- u->val3 );
- break;
-
- case SSE3a1_MemRd:
- vg_assert(u->size == 8 || u->size == 16);
- vg_assert(u->tag1 == Lit16);
- vg_assert(u->tag2 == Lit16);
- vg_assert(u->tag3 == RealReg);
- vg_assert(!anyFlagUse(u));
- if (!(*sselive)) {
- emit_get_sse_state();
- *sselive = True;
- }
- emit_SSE3a1 ( u->flags_r, u->flags_w,
- (u->val1 >> 8) & 0xFF,
- u->val1 & 0xFF,
- (u->val2 >> 8) & 0xFF,
- u->val2 & 0xFF,
- u->lit32 & 0xFF,
- u->val3 );
- break;
-
- case SSE5:
- vg_assert(u->size == 0);
- vg_assert(u->tag1 == Lit16);
- vg_assert(u->tag2 == Lit16);
- vg_assert(u->tag3 == Lit16);
- vg_assert(!anyFlagUse(u));
- if (!(*sselive)) {
- emit_get_sse_state();
- *sselive = True;
- }
- emit_SSE5 ( u->flags_r, u->flags_w,
- (u->val1 >> 8) & 0xFF,
- u->val1 & 0xFF,
- (u->val2 >> 8) & 0xFF,
- u->val2 & 0xFF,
- u->val3 & 0xFF );
- break;
-
- case SSE4:
- vg_assert(u->size == 0);
- vg_assert(u->tag1 == Lit16);
- vg_assert(u->tag2 == Lit16);
- vg_assert(u->tag3 == NoValue);
- vg_assert(u->flags_r == FlagsEmpty);
- if (!(*sselive)) {
- emit_get_sse_state();
- *sselive = True;
- }
- emit_SSE4 ( u->flags_r, u->flags_w,
- (u->val1 >> 8) & 0xFF,
- u->val1 & 0xFF,
- (u->val2 >> 8) & 0xFF,
- u->val2 & 0xFF );
- break;
-
- case SSE3:
- vg_assert(u->size == 0);
- vg_assert(u->tag1 == Lit16);
- vg_assert(u->tag2 == Lit16);
- vg_assert(u->tag3 == NoValue);
- vg_assert(!readFlagUse(u));
- if (!(*sselive)) {
- emit_get_sse_state();
- *sselive = True;
- }
- emit_SSE3 ( u->flags_r, u->flags_w,
- (u->val1 >> 8) & 0xFF,
- u->val1 & 0xFF,
- u->val2 & 0xFF );
- break;
-
- case SSE3ag_MemRd_RegWr:
- vg_assert(u->size == 4 || u->size == 8);
- vg_assert(u->tag1 == RealReg);
- vg_assert(u->tag2 == RealReg);
- vg_assert(u->tag3 == NoValue);
- vg_assert(!anyFlagUse(u));
- if (!(*sselive)) {
- emit_get_sse_state();
- *sselive = True;
- }
- emit_SSE3ag_MemRd_RegWr ( u->flags_r, u->flags_w,
- (u->lit32 >> 24) & 0xFF,
- (u->lit32 >> 16) & 0xFF,
- (u->lit32 >> 8) & 0xFF,
- u->val1, u->val2 );
- break;
-
- default:
- if (VG_(needs).extended_UCode) {
- if (*sselive) {
- emit_put_sse_state();
- *sselive = False;
- }
- TL_(emit_XUInstr)(u, regs_live_before);
- } else {
- VG_(printf)("\nError:\n"
- " unhandled opcode: %u. Perhaps "
- " VG_(needs).extended_UCode should be set?\n",
- u->opcode);
- VG_(pp_UInstr)(0,u);
- VG_(core_panic)("emitUInstr: unimplemented opcode");
- }
- }
-
- if (0 && (*sselive)) {
- emit_put_sse_state();
- *sselive = False;
- }
-
- /* Update UInstr histogram */
- vg_assert(u->opcode < 100);
- histogram[u->opcode].counts++;
- histogram[u->opcode].size += (emitted_code_used - old_emitted_code_used);
-}
-
-
-/* Emit x86 for the ucode in cb, returning the address of the
- generated code and setting *nbytes to its size. */
-UChar* VG_(emit_code) ( UCodeBlock* cb,
- Int* nbytes,
- UShort j[VG_MAX_JUMPS] )
-{
- Int i;
- UChar regs_live_before = 0; /* No regs live at BB start */
- Bool sselive;
- Addr orig_eip, curr_eip;
- Int tgt;
-
- reset_state();
-
- if (dis) VG_(printf)("Generated x86 code:\n");
-
- /* Generate subl $1, VG_(dispatch_ctr) and drop into dispatch if we hit
- zero. We have to do this regardless of whether we're t-chaining
- or not. (The ia32 optimisation guide recommends sub over dec.) */
- VG_(init_target)(&tgt);
- VG_(new_emit)(False, FlagsEmpty, FlagsOSZAP);
- VG_(emitB) (0x83); /* subl */
- emit_amode_litmem_reg((Addr)&VG_(dispatch_ctr), 5);
- VG_(emitB) (0x01);
-
- if (dis)
- VG_(printf)("\n\t\tsubl $1, (%p)\n", &VG_(dispatch_ctr));
-
- VG_(emit_jcondshort_target)(False, CondNZ, &tgt, JP_TAKEN);
- VG_(emit_movv_lit_reg) ( 4, VG_TRC_INNER_COUNTERZERO, R_EBP );
- emit_ret();
- VG_(target_forward)(&tgt);
-
- /* Set up running state. */
- sselive = False;
- orig_eip = cb->orig_eip; /* we know EIP is up to date on BB entry */
- curr_eip = cb->orig_eip;
- vg_assert(curr_eip != 0); /* otherwise the incremental updating
- algorithm gets messed up. */
- /* for each uinstr ... */
- for (i = 0; i < cb->used; i++) {
- UInstr* u = &cb->instrs[i];
- VG_(sanity_check_UInstr)( i, u );
- if (cb->instrs[i].opcode != NOP) {
- emitUInstr( cb, i, regs_live_before,
- &sselive, &orig_eip, &curr_eip );
- }
- regs_live_before = u->regs_live_after;
- }
- if (dis) VG_(printf)("\n");
- vg_assert(!sselive); /* SSE state must be saved by end of BB */
- vg_assert(eflags_state != UPD_Real); /* flags can't just be in CPU */
-
- vg_assert(NULL != j);
- vg_assert(jumpidx <= VG_MAX_JUMPS);
- for(i = 0; i < jumpidx; i++)
- j[i] = jumps[i];
-
- /* Returns a pointer to the emitted code. This will have to be
- copied by the caller into the translation cache, and then freed */
- *nbytes = emitted_code_used;
- return emitted_code;
-}
-
-#undef dis
-
/*--------------------------------------------------------------------*/
/*--- end vg_from_ucode.c ---*/
/*--------------------------------------------------------------------*/
The GNU General Public License is contained in the file COPYING.
*/
-/* We only import tool.h here, because this file only provides functions
- for doing things that could be done directly by the tool -- it's just to
- make tools' lives easier, rather than let them do something they
- couldn't otherwise do. */
-#include "tool.h"
-
-
-void VG_(lit_to_reg)(UCodeBlock* cb, UInt lit, UInt t)
-{
- uInstr2 (cb, MOV, 4, Literal, 0, TempReg, t);
- uLiteral(cb, lit);
-}
-
-UInt VG_(lit_to_newreg)(UCodeBlock* cb, UInt lit)
-{
- UInt t = newTemp(cb);
- uInstr2 (cb, MOV, 4, Literal, 0, TempReg, t);
- uLiteral(cb, lit);
- return t;
-}
-
-// f()
-void VG_(ccall_0_0)(UCodeBlock* cb, Addr f)
-{
- uInstr0(cb, CCALL, 0);
- uCCall(cb, f, 0, 0, /*retval*/False);
-}
-
-// f(reg)
-void VG_(ccall_R_0)(UCodeBlock* cb, Addr f, UInt t1, UInt regparms_n)
-{
- tl_assert(regparms_n <= 1);
- uInstr1(cb, CCALL, 0, TempReg, t1);
- uCCall(cb, f, 1, regparms_n, /*retval*/False);
-}
-
-// f(lit)
-void VG_(ccall_L_0)(UCodeBlock* cb, Addr f, UInt lit1, UInt regparms_n)
-{
- UInt t1 = VG_(lit_to_newreg)(cb, lit1);
- VG_(ccall_R_0)(cb, f, t1, regparms_n);
-}
-
-// reg = f(reg)
-void VG_(ccall_R_R)(UCodeBlock* cb, Addr f, UInt t1, UInt t_ret,
- UInt regparms_n)
-{
- tl_assert(regparms_n <= 1);
- tl_assert(t1 < VG_(get_num_temps)(cb)); // help catch lits accidentally passed in
- uInstr3(cb, CCALL, 0, TempReg, t1, NoValue, 0, TempReg, t_ret);
- uCCall(cb, f, 1, regparms_n, /*retval*/True);
-}
-
-// reg = f(lit)
-void VG_(ccall_L_R)(UCodeBlock* cb, Addr f, UInt lit1, UInt t_ret,
- UInt regparms_n)
-{
- UInt t1 = VG_(lit_to_newreg)(cb, lit1);
- VG_(ccall_R_R)(cb, f, t1, t_ret, regparms_n);
-}
-
-// f(reg, reg)
-void VG_(ccall_RR_0)(UCodeBlock* cb, Addr f, UInt t1, UInt t2, UInt regparms_n)
-{
- tl_assert(regparms_n <= 2);
- tl_assert(t1 < VG_(get_num_temps)(cb));
- tl_assert(t2 < VG_(get_num_temps)(cb));
- uInstr2(cb, CCALL, 0, TempReg, t1, TempReg, t2);
- uCCall(cb, f, 2, regparms_n, /*retval*/False);
-}
-
-// f(reg, lit)
-void VG_(ccall_RL_0)(UCodeBlock* cb, Addr f, UInt t1, UInt lit2,
- UInt regparms_n)
-{
- UInt t2 = VG_(lit_to_newreg)(cb, lit2);
- VG_(ccall_RR_0)(cb, f, t1, t2, regparms_n);
-}
-
-// f(lit, reg)
-void VG_(ccall_LR_0)(UCodeBlock* cb, Addr f, UInt lit1, UInt t2,
- UInt regparms_n)
-{
- UInt t1 = VG_(lit_to_newreg)(cb, lit1);
- VG_(ccall_RR_0)(cb, f, t1, t2, regparms_n);
-}
-
-// f(lit, lit)
-void VG_(ccall_LL_0)(UCodeBlock* cb, Addr f, UInt lit1, UInt lit2,
- UInt regparms_n)
-{
- UInt t1 = VG_(lit_to_newreg)(cb, lit1);
- UInt t2 = VG_(lit_to_newreg)(cb, lit2);
- VG_(ccall_RR_0)(cb, f, t1, t2, regparms_n);
-}
-
-// reg = f(reg, reg)
-void VG_(ccall_RR_R)(UCodeBlock* cb, Addr f, UInt t1, UInt t2, UInt t_ret,
- UInt regparms_n)
-{
- tl_assert(regparms_n <= 2);
- tl_assert(t1 < VG_(get_num_temps)(cb));
- tl_assert(t2 < VG_(get_num_temps)(cb));
- uInstr3(cb, CCALL, 0, TempReg, t1, TempReg, t2, TempReg, t_ret);
- uCCall(cb, f, 2, regparms_n, /*retval*/True);
-}
-
-// reg = f(reg, lit)
-void VG_(ccall_RL_R)(UCodeBlock* cb, Addr f, UInt t1, UInt lit2, UInt t_ret,
- UInt regparms_n)
-{
- UInt t2 = VG_(lit_to_newreg)(cb, lit2);
- VG_(ccall_RR_R)(cb, f, t1, t2, t_ret, regparms_n);
-}
-
-// reg = f(lit, reg)
-void VG_(ccall_LR_R)(UCodeBlock* cb, Addr f, UInt lit1, UInt t2, UInt t_ret,
- UInt regparms_n)
-{
- UInt t1 = VG_(lit_to_newreg)(cb, lit1);
- VG_(ccall_RR_R)(cb, f, t1, t2, t_ret, regparms_n);
-}
-
-// reg = f(lit, lit)
-void VG_(ccall_LL_R)(UCodeBlock* cb, Addr f, UInt lit1, UInt lit2, UInt t_ret,
- UInt regparms_n)
-{
- UInt t1 = VG_(lit_to_newreg)(cb, lit2);
- UInt t2 = VG_(lit_to_newreg)(cb, lit2);
- VG_(ccall_RR_R)(cb, f, t1, t2, t_ret, regparms_n);
-}
-
-// f(reg, reg, reg)
-void VG_(ccall_RRR_0)(UCodeBlock* cb, Addr f, UInt t1, UInt t2,
- UInt t3, UInt regparms_n)
-{
- tl_assert(regparms_n <= 3);
- tl_assert(t1 < VG_(get_num_temps)(cb));
- tl_assert(t2 < VG_(get_num_temps)(cb));
- tl_assert(t3 < VG_(get_num_temps)(cb));
- uInstr3(cb, CCALL, 0, TempReg, t1, TempReg, t2, TempReg, t3);
- uCCall(cb, f, 3, regparms_n, /*retval*/False);
-}
-
-// f(reg, lit, lit)
-void VG_(ccall_RLL_0)(UCodeBlock* cb, Addr f, UInt t1, UInt lit2,
- UInt lit3, UInt regparms_n)
-{
- UInt t2 = VG_(lit_to_newreg)(cb, lit2);
- UInt t3 = VG_(lit_to_newreg)(cb, lit3);
- VG_(ccall_RRR_0)(cb, f, t1, t2, t3, regparms_n);
-}
-
-// f(lit, reg, reg)
-void VG_(ccall_LRR_0)(UCodeBlock* cb, Addr f, UInt lit1, UInt t2,
- UInt t3, UInt regparms_n)
-{
- UInt t1 = VG_(lit_to_newreg)(cb, lit1);
- VG_(ccall_RRR_0)(cb, f, t1, t2, t3, regparms_n);
-}
-
-// f(lit, lit, reg)
-void VG_(ccall_LLR_0)(UCodeBlock* cb, Addr f, UInt lit1, UInt lit2,
- UInt t3, UInt regparms_n)
-{
- UInt t1 = VG_(lit_to_newreg)(cb, lit1);
- UInt t2 = VG_(lit_to_newreg)(cb, lit2);
- VG_(ccall_RRR_0)(cb, f, t1, t2, t3, regparms_n);
-}
-
-// f(lit, lit, lit)
-void VG_(ccall_LLL_0)(UCodeBlock* cb, Addr f, UInt lit1, UInt lit2,
- UInt lit3, UInt regparms_n)
-{
- UInt t1 = VG_(lit_to_newreg)(cb, lit1);
- UInt t2 = VG_(lit_to_newreg)(cb, lit2);
- UInt t3 = VG_(lit_to_newreg)(cb, lit3);
- VG_(ccall_RRR_0)(cb, f, t1, t2, t3, regparms_n);
-}
-
-void VG_(reg_to_globvar)(UCodeBlock* cb, UInt t, UInt* globvar_ptr)
-{
- Int t_gv = VG_(lit_to_newreg)(cb, (UInt)globvar_ptr);
- uInstr2(cb, STORE, 4, TempReg, t, TempReg, t_gv);
-}
-
-void VG_(lit_to_globvar)(UCodeBlock* cb, UInt lit, UInt* globvar_ptr)
-{
- Int t_lit = VG_(lit_to_newreg)(cb, lit);
- VG_(reg_to_globvar)(cb, t_lit, globvar_ptr);
-}
-
-/*--------------------------------------------------------------------
- Old versions of these functions, for backwards compatibility
- --------------------------------------------------------------------*/
-
-void VG_(call_helper_0_0)(UCodeBlock* cb, Addr f)
-{
- VG_(ccall_0_0)(cb, f);
-}
-
-void VG_(call_helper_1_0)(UCodeBlock* cb, Addr f, UInt arg1, UInt regparms_n)
-{
- VG_(ccall_L_0)(cb, f, arg1, regparms_n);
-}
-
-void VG_(call_helper_2_0)(UCodeBlock* cb, Addr f, UInt arg1, UInt arg2,
- UInt regparms_n)
-{
- VG_(ccall_LL_0)(cb, f, arg1, arg2, regparms_n);
-}
-
-void VG_(set_global_var)(UCodeBlock* cb, Addr globvar_ptr, UInt val)
-{
- VG_(lit_to_globvar)(cb, val, (UInt*)globvar_ptr);
-}
-
-void VG_(set_global_var_tempreg)(UCodeBlock* cb, Addr globvar_ptr, UInt t_val)
-{
- VG_(reg_to_globvar)(cb, t_val, (UInt*)globvar_ptr);
-}
-
/*--------------------------------------------------------------------*/
/*--- end vg_instrument.c ---*/
/*--------------------------------------------------------------------*/
UInt VG_(dispatch_ctr);
/* 64-bit counter for the number of basic blocks done. */
-ULong VG_(bbs_done);
+ULong VG_(bbs_done) = 0;
/* Tell the logging mechanism whether we are logging to a file
descriptor or a socket descriptor. */
// Scheduler stats
VG_(print_scheduler_stats)();
- // Reg-alloc stats
- VG_(print_reg_alloc_stats)();
VG_(message)(Vg_DebugMsg,
" sanity: %d cheap, %d expensive checks.",
sanity_fast_count, sanity_slow_count );
- // C call stats
- VG_(print_ccall_stats)();
-
- // UInstr histogram
- if (VG_(clo_verbosity) > 3)
- VG_(print_UInstr_histogram)();
-
// Memory stats
if (VG_(clo_verbosity) > 2) {
VG_(message)(Vg_DebugMsg, "");
Addr VG_(get_stack_pointer) ( void )
{
- return VG_(baseBlock)[VGOFF_STACK_PTR];
+ return BASEBLOCK_STACK_PTR;
}
/* Debugging thing .. can be called from assembly with OYNK macro. */
/*====================================================================*/
/* Define, and set defaults. */
+VexControl VG_(clo_vex_control);
Bool VG_(clo_error_limit) = True;
Bool VG_(clo_db_attach) = False;
Char* VG_(clo_db_command) = VG_CLO_DEFAULT_DBCOMMAND;
" --profile=no|yes profile? (tool must be built for it) [no]\n"
" --chain-bb=no|yes do basic-block chaining? [yes]\n"
" --branchpred=yes|no generate branch prediction hints [no]\n"
-" --trace-codegen=<XXXXX> show generated code? (X = 0|1) [00000]\n"
+" --trace-codegen=<XXXXXXXX> show generated code? (X = 0|1) [00000000]\n"
" --trace-syscalls=no|yes show all system calls? [no]\n"
" --trace-signals=no|yes show signal handling details? [no]\n"
" --trace-symtab=no|yes show symbol table details? [no]\n"
" --trace-pthread=none|some|all show pthread event details? [none]\n"
" --wait-for-gdb=yes|no pause on startup to wait for gdb attach\n"
"\n"
+" --vex-iropt-verbosity 0 .. 9 [0]\n"
+" --vex-iropt-level 0 .. 2 [2]\n"
+" --vex-iropt-precise-memory-exns [no]\n"
+" --vex-iropt-unroll-thresh 0 .. 400 [120]\n"
+" --vex-guest-max-insns 1 .. 100 [50]\n"
+" --vex-guest-chase-thresh 0 .. 99 [10]\n"
+"\n"
" debugging options for Valgrind tools that report errors\n"
" --dump-error=<number> show translation for basic block associated\n"
" with <number>'th error context [0=show none]\n"
{
UInt i;
+ LibVEX_default_VexControl(& VG_(clo_vex_control));
+
/* parse the options we have (only the options we care about now) */
for (i = 1; i < vg_argc; i++) {
else VG_BNUM_CLO("--num-callers", VG_(clo_backtrace_size), 1,
VG_DEEPEST_BACKTRACE)
+ else VG_BNUM_CLO("--vex-iropt-verbosity",
+ VG_(clo_vex_control).iropt_verbosity, 0, 10)
+ else VG_BNUM_CLO("--vex-iropt-level",
+ VG_(clo_vex_control).iropt_level, 0, 2)
+ else VG_BOOL_CLO("--vex-iropt-precise-memory-exns",
+ VG_(clo_vex_control).iropt_precise_memory_exns)
+ else VG_BNUM_CLO("--vex-iropt-unroll-thresh",
+ VG_(clo_vex_control).iropt_unroll_thresh, 0, 400)
+ else VG_BNUM_CLO("--vex-guest-max-insns",
+ VG_(clo_vex_control).guest_max_insns, 1, 100)
+ else VG_BNUM_CLO("--vex-guest-chase-thresh",
+ VG_(clo_vex_control).guest_chase_thresh, 0, 99)
+
// for backwards compatibility, replaced by --log-fd
else if (VG_CLO_STREQN(13, arg, "--logfile-fd=")) {
VG_(clo_log_to) = VgLogTo_Fd;
if (5 != VG_(strlen)(opt)) {
VG_(message)(Vg_UserMsg,
- "--trace-codegen argument must have 5 digits");
+ "--trace-codegen argument must have 8 digits");
VG_(bad_option)(arg);
}
- for (j = 0; j < 5; j++) {
+ for (j = 0; j < 8; j++) {
if ('0' == opt[j]) { /* do nothing */ }
- else if ('1' == opt[j]) VG_(clo_trace_codegen) |= (1 << j);
+ else if ('1' == opt[j]) VG_(clo_trace_codegen) |= (1 << (7-j));
else {
VG_(message)(Vg_UserMsg, "--trace-codegen argument can only "
"contain 0s and 1s");
VG_(threads)[last_run_tid].status == VgTs_WaitJoiner);
VG_(nuke_all_threads_except)(VG_INVALID_THREADID);
+ /* Print Vex storage stats */
+ LibVEX_ClearTemporary( True/*show stats*/ );
+
//--------------------------------------------------------------
// Exit, according to the scheduler's return code
//--------------------------------------------------------------
REGPARM(1)
void VG_(unknown_SP_update)(Addr new_SP)
{
- Addr old_SP = VG_(get_archreg)(R_STACK_PTR);
+ Addr old_SP = BASEBLOCK_STACK_PTR;
Word delta = (Word)new_SP - (Word)old_SP;
if (delta < -(VG_HUGE_DELTA) || VG_HUGE_DELTA < delta) {
VG_(baseBlock). */
if (vg_tid_currently_in_baseBlock != VG_INVALID_THREADID) {
tid = vg_tid_currently_in_baseBlock;
- if ( p ( VG_(baseBlock)[VGOFF_STACK_PTR],
+ if ( p ( BASEBLOCK_STACK_PTR,
VG_(threads)[tid].stack_highest_word, d ) )
return tid;
else
UInt run_thread_for_a_while ( ThreadId tid )
{
volatile UInt trc = 0;
+ volatile Int dispatch_ctr_SAVED = VG_(dispatch_ctr);
+ volatile Int done_this_time;
+
vg_assert(VG_(is_valid_tid)(tid));
vg_assert(VG_(threads)[tid].status == VgTs_Runnable);
vg_assert(!scheduler_jmpbuf_valid);
vg_assert(!scheduler_jmpbuf_valid);
save_thread_state ( tid );
+
+ done_this_time = (Int)dispatch_ctr_SAVED - (Int)VG_(dispatch_ctr) - 0;
+
+ vg_assert(done_this_time >= 0);
+ VG_(bbs_done) += (ULong)done_this_time;
+
VGP_POPCC(VgpRun);
return trc;
}
{
ThreadId tid, tid_next;
UInt trc;
- UInt dispatch_ctr_SAVED;
Int done_this_time, n_in_bounded_wait;
Int n_exists, n_waiting_for_reaper;
Addr trans_addr;
*/
VG_(dispatch_ctr) = VG_SCHEDULING_QUANTUM + 1;
- /* ... and remember what we asked for. */
- dispatch_ctr_SAVED = VG_(dispatch_ctr);
-
/* paranoia ... */
vg_assert(VG_(threads)[tid].tid == tid);
if (trc == VG_TRC_INNER_FASTMISS) {
Addr ip = ARCH_INSTR_PTR(VG_(threads)[tid].arch);
- vg_assert(VG_(dispatch_ctr) > 0);
+ vg_assert(VG_(dispatch_ctr) > 1);
/* Trivial event. Miss in the fast-cache. Do a full
lookup for it. */
non-completely-trivial reason. First, update basic-block
counters. */
- done_this_time = (Int)dispatch_ctr_SAVED - (Int)VG_(dispatch_ctr);
- vg_assert(done_this_time > 0);
- VG_(bbs_done) += (ULong)done_this_time;
-
if (0 && trc != VG_TRC_INNER_FASTMISS)
VG_(message)(Vg_DebugMsg, "thread %d: completed %d bbs, trc %d",
tid, done_this_time, (Int)trc );
/* Timeslice is out. Let a new thread be scheduled,
simply by doing nothing, causing us to arrive back at
Phase 1. */
- vg_assert(VG_(dispatch_ctr) == 0);
+ vg_assert(VG_(dispatch_ctr) == 1);
break;
case VG_TRC_UNRESUMABLE_SIGNAL:
void VG_(set_return_from_syscall_shadow) ( ThreadId tid, UInt ret_shadow )
{
- VG_(set_thread_shadow_archreg)(tid, R_SYSCALL_RET, ret_shadow);
+ VGA_(set_thread_shadow_archreg)(tid, R_SYSCALL_RET, ret_shadow);
}
UInt VG_(get_exit_status_shadow) ( void )
{
- return VG_(get_shadow_archreg)(R_SYSCALL_ARG1);
+ return VGA_(get_shadow_archreg)(R_SYSCALL_ARG1);
}
void VG_(intercept_libc_freeres_wrapper)(Addr addr)
}
}
-static void fill_prstatus(const ThreadState *tst, struct vki_elf_prstatus *prs, const vki_siginfo_t *si)
+static void fill_prstatus(ThreadState *tst, struct vki_elf_prstatus *prs, const vki_siginfo_t *si)
{
struct vki_user_regs_struct *regs;
*/
if (VG_(clo_trace_signals)) {
+ VG_(message)(Vg_DebugMsg, "");
VG_(message)(Vg_DebugMsg, "signal %d arrived ... si_code=%d",
sigNo, info->si_code );
}
ThreadId tid = VG_(get_current_or_recent_tid)();
Addr fault = (Addr)info->_sifields._sigfault._addr;
Addr esp = VG_(is_running_thread)(tid)
- ? VG_(baseBlock)[VGOFF_STACK_PTR]
+ ? BASEBLOCK_STACK_PTR
: ARCH_STACK_PTR(VG_(threads)[tid].arch);
Segment *seg;
The GNU General Public License is contained in the file COPYING.
*/
-#include "core.h"
-
-
-/*------------------------------------------------------------*/
-/*--- Debugging output ---*/
-/*------------------------------------------------------------*/
-
-#define DIP(format, args...) \
- if (VG_(print_codegen)) \
- VG_(printf)(format, ## args)
-
-#define DIS(buf, format, args...) \
- if (VG_(print_codegen)) \
- VG_(sprintf)(buf, format, ## args)
-
-/*------------------------------------------------------------*/
-/*--- CPU feature set stuff ---*/
-/*--- This is a little out of place here, but it will do ---*/
-/*--- for now. ---*/
-/*------------------------------------------------------------*/
-
-#define VG_CPU_VENDOR_GENERIC 0
-#define VG_CPU_VENDOR_INTEL 1
-#define VG_CPU_VENDOR_AMD 2
-
-/* Standard macro to see if a specific flag is changeable */
-static inline Bool flag_is_changeable(UInt flag)
-{
- UInt f1, f2;
-
- asm("pushfl\n\t"
- "pushfl\n\t"
- "popl %0\n\t"
- "movl %0,%1\n\t"
- "xorl %2,%0\n\t"
- "pushl %0\n\t"
- "popfl\n\t"
- "pushfl\n\t"
- "popl %0\n\t"
- "popfl\n\t"
- : "=&r" (f1), "=&r" (f2)
- : "ir" (flag));
-
- return ((f1^f2) & flag) != 0;
-}
-
-
-/* Probe for the CPUID instruction */
-static Bool has_cpuid(void)
-{
- return flag_is_changeable(EFlagID);
-}
-
-// Returns the CPU features, and also the vendorid. Only ever calls CPUID
-// once, and caches the necessary info in static variables for later reuse.
-static UInt* get_cpu_features(Int* cpu_vendorid_ptr)
-{
- Char vendorstr[13];
- Int i, cpuid_level;
- static Bool done_before = False;
- static Int cpu_vendorid = VG_CPU_VENDOR_GENERIC;
- static UInt cpu_features[VG_N_FEATURE_WORDS];
- static const struct {
- const Char *vendorstr;
- Int vendorid;
- } cpu_vendors[] = {
- { "GenuineIntel", VG_CPU_VENDOR_INTEL },
- { "AuthenticAMD", VG_CPU_VENDOR_AMD },
- };
-
- // If we haven't already worked this stuff out...
- if (!done_before && has_cpuid()) {
-
- cpu_features[VG_INT_FEAT] |= (1 << (VG_X86_FEAT_CPUID%32));
-
- // Get vendor string, eg. "GenuineIntel". Note characteristically
- // stupid word order chosen by Intel.
- VG_(cpuid)(0, &cpuid_level, (UInt *)&vendorstr[0],
- (UInt *)&vendorstr[8],
- (UInt *)&vendorstr[4]);
- vendorstr[12] = '\0';
-
- // Determine vendor ID
- for (i = 0; i < sizeof(cpu_vendors)/sizeof(*cpu_vendors); i++)
- if (VG_(memcmp)(vendorstr, cpu_vendors[i].vendorstr, 12) == 0) {
- cpu_vendorid = cpu_vendors[i].vendorid;
- break;
- }
-
- // Determine CPU features
- if (cpuid_level >= 1)
- VG_(cpuid)(1, NULL, NULL, &cpu_features[VG_EXT_FEAT],
- &cpu_features[VG_X86_FEAT]);
-
- if (VG_CPU_VENDOR_AMD == cpu_vendorid) {
- /* get AMD-specific flags */
- VG_(cpuid)(0x80000001, NULL, NULL, NULL, &cpu_features[VG_AMD_FEAT]);
- }
- }
- if (NULL != cpu_vendorid_ptr) *cpu_vendorid_ptr = cpu_vendorid;
- return cpu_features;
-}
-
-Bool VG_(cpu_has_feature)(UInt feature)
-{
- UInt word = feature / 32;
- UInt bit = feature % 32;
- UInt* cpu_features;
-
- vg_assert(word >= 0 && word < VG_N_FEATURE_WORDS);
-
- cpu_features = get_cpu_features(NULL);
-
- return !!( cpu_features[word] & (1 << bit) );
-}
-
-/* The set of features we're willing to support for the client
-
- This includes supported instruction set extensions, plus any
- extensions which don't have any user-mode visible effect (but the
- client may find interesting).
- */
-#define VG_X86_SUPPORTED_FEATURES \
- ((1 << VG_X86_FEAT_FPU) | \
- (1 << VG_X86_FEAT_VME) | \
- (1 << VG_X86_FEAT_DE) | \
- (1 << VG_X86_FEAT_PSE) | \
- (1 << VG_X86_FEAT_TSC) | \
- (0 << VG_X86_FEAT_MSR) | \
- (1 << VG_X86_FEAT_PAE) | \
- (1 << VG_X86_FEAT_MCE) | \
- (1 << VG_X86_FEAT_CX8) | \
- (1 << VG_X86_FEAT_APIC) | \
- (0 << VG_X86_FEAT_SEP) | \
- (1 << VG_X86_FEAT_MTRR) | \
- (1 << VG_X86_FEAT_PGE) | \
- (1 << VG_X86_FEAT_MCA) | \
- (1 << VG_X86_FEAT_CMOV) | \
- (1 << VG_X86_FEAT_PAT) | \
- (1 << VG_X86_FEAT_PSE36) | \
- (0 << VG_X86_FEAT_CLFSH) | \
- (1 << VG_X86_FEAT_DS) | \
- (1 << VG_X86_FEAT_ACPI) | \
- (1 << VG_X86_FEAT_MMX) | \
- (1 << VG_X86_FEAT_FXSR) | \
- (1 << VG_X86_FEAT_SSE) | \
- (1 << VG_X86_FEAT_SSE2) | \
- (1 << VG_X86_FEAT_SS) | \
- (1 << VG_X86_FEAT_HT) | \
- (1 << VG_X86_FEAT_TM) | \
- (0 << VG_X86_FEAT_IA64) | \
- (1 << VG_X86_FEAT_PBE))
-
-#define VG_AMD_SUPPORTED_FEATURES \
- ((0 << (VG_AMD_FEAT_SYSCALL % 32)) | \
- (0 << (VG_AMD_FEAT_NXP % 32)) | \
- (1 << (VG_AMD_FEAT_MMXEXT % 32)) | \
- (0 << (VG_AMD_FEAT_FFXSR % 32)) | \
- (0 << (VG_AMD_FEAT_LONGMODE % 32)) | \
- (0 << (VG_AMD_FEAT_3DNOWEXT % 32)) | \
- (0 << (VG_AMD_FEAT_3DNOW % 32)) | \
- /* Common bits between standard features and AMD features */ \
- (1 << VG_X86_FEAT_FPU) | \
- (1 << VG_X86_FEAT_VME) | \
- (1 << VG_X86_FEAT_DE) | \
- (1 << VG_X86_FEAT_PSE) | \
- (1 << VG_X86_FEAT_TSC) | \
- (0 << VG_X86_FEAT_MSR) | \
- (1 << VG_X86_FEAT_PAE) | \
- (1 << VG_X86_FEAT_MCE) | \
- (1 << VG_X86_FEAT_CX8) | \
- (1 << VG_X86_FEAT_APIC) | \
- (1 << VG_X86_FEAT_MTRR) | \
- (1 << VG_X86_FEAT_PGE) | \
- (1 << VG_X86_FEAT_MCA) | \
- (1 << VG_X86_FEAT_CMOV) | \
- (1 << VG_X86_FEAT_PAT) | \
- (1 << VG_X86_FEAT_PSE36) | \
- (1 << VG_X86_FEAT_MMX) | \
- (1 << VG_X86_FEAT_FXSR))
-
-
-/*
- For simulating the cpuid instruction, we will
- issue a "real" cpuid instruction and then mask out
- the bits of the features we do not support currently (3dnow mostly).
- We also claim to not support most CPUID operations.
-
- Dirk Mueller <mueller@kde.org>
-
- http://www.sandpile.org/ia32/cpuid.htm
-
- references:
-
- pre-MMX pentium:
-
- <werner> cpuid words (0): 0x1 0x756e6547 0x6c65746e 0x49656e69
- <werner> cpuid words (1): 0x52b 0x0 0x0 0x1bf
-
- Updated to be more extensible about future vendor extensions and
- vendor-specific parts of CPUID.
-*/
-void VG_(helperc_CPUID)(UInt op, UInt *eax_ret, UInt *ebx_ret,
- UInt *ecx_ret, UInt *edx_ret)
-{
- UInt eax, ebx, ecx, edx;
- Int cpu_vendorid;
-
- // This function should not be called unless the CPU has CPUID.
- vg_assert( VG_(cpu_has_feature)(VG_X86_FEAT_CPUID) );
-
- // Get vendor ID.
- get_cpu_features( &cpu_vendorid );
-
- VG_(cpuid)(op, &eax, &ebx, &ecx, &edx);
-
- /* Common mangling */
- switch(op) {
- case 1:
- edx &= VG_X86_SUPPORTED_FEATURES;
- break;
-
- case 0xd8000000: {
- /* Implement some private information at 0xd8000000 */
- static const Char valgrind_vendor[] = "ValgrindVCPU";
-
- eax = 0xd8000000; /* max request */
- ebx = *(UInt *)&valgrind_vendor[0];
- ecx = *(UInt *)&valgrind_vendor[8];
- edx = *(UInt *)&valgrind_vendor[4];
- }
- break;
- }
-
- /* Vendor-specific mangling of the results */
- switch (cpu_vendorid) {
- case VG_CPU_VENDOR_INTEL:
- switch(op) {
- case 1:
- ecx = 0; /* mask out all extended features for now */
- break;
-
- case 0x80000001:
- ebx = ecx = edx = 0;
- break;
- }
- break;
-
- case VG_CPU_VENDOR_AMD:
- switch(op) {
- case 0x80000001:
- edx &= VG_AMD_SUPPORTED_FEATURES;
- break;
- }
- break;
- }
-
- *eax_ret = eax;
- *ebx_ret = ebx;
- *ecx_ret = ecx;
- *edx_ret = edx;
-}
-
-
-/*------------------------------------------------------------*/
-/*--- Here so it can be inlined everywhere. ---*/
-/*------------------------------------------------------------*/
-
-/* Allocate a new temp reg number. */
-__inline__ Int VG_(get_new_temp) ( UCodeBlock* cb )
-{
- Int t = cb->nextTemp;
- cb->nextTemp += 2;
- return t;
-}
-
-Int VG_(get_new_shadow) ( UCodeBlock* cb )
-{
- Int t = cb->nextTemp;
- cb->nextTemp += 2;
- return SHADOW(t);
-}
-
-
-/*------------------------------------------------------------*/
-/*--- Helper bits and pieces for deconstructing the ---*/
-/*--- x86 insn stream. ---*/
-/*------------------------------------------------------------*/
-
-static Char* nameGrp1 ( Int opc_aux )
-{
- static Char* grp1_names[8]
- = { "add", "or", "adc", "sbb", "and", "sub", "xor", "cmp" };
- if (opc_aux < 0 || opc_aux > 7) VG_(core_panic)("nameGrp1");
- return grp1_names[opc_aux];
-}
-
-static Char* nameGrp2 ( Int opc_aux )
-{
- static Char* grp2_names[8]
- = { "rol", "ror", "rcl", "rcr", "shl", "shr", "shl", "sar" };
- if (opc_aux < 0 || opc_aux > 7) VG_(core_panic)("nameGrp2");
- return grp2_names[opc_aux];
-}
-
-static Char* nameGrp4 ( Int opc_aux )
-{
- static Char* grp4_names[8]
- = { "inc", "dec", "???", "???", "???", "???", "???", "???" };
- if (opc_aux < 0 || opc_aux > 1) VG_(core_panic)("nameGrp4");
- return grp4_names[opc_aux];
-}
-
-static Char* nameGrp5 ( Int opc_aux )
-{
- static Char* grp5_names[8]
- = { "inc", "dec", "call*", "call*", "jmp*", "jmp*", "push", "???" };
- if (opc_aux < 0 || opc_aux > 6) VG_(core_panic)("nameGrp5");
- return grp5_names[opc_aux];
-}
-
-static Char* nameGrp8 ( Int opc_aux )
-{
- static Char* grp8_names[8]
- = { "???", "???", "???", "???", "bt", "bts", "btr", "btc" };
- if (opc_aux < 4 || opc_aux > 7) VG_(core_panic)("nameGrp8");
- return grp8_names[opc_aux];
-}
-
-const Char* VG_(name_of_int_reg) ( Int size, Int reg )
-{
- static Char* ireg32_names[8]
- = { "%eax", "%ecx", "%edx", "%ebx",
- "%esp", "%ebp", "%esi", "%edi" };
- static Char* ireg16_names[8]
- = { "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di" };
- static Char* ireg8_names[8]
- = { "%al", "%cl", "%dl", "%bl",
- "%ah{sp}", "%ch{bp}", "%dh{si}", "%bh{di}" };
- if (reg < 0 || reg > 7) goto bad;
- switch (size) {
- case 4: return ireg32_names[reg];
- case 2: return ireg16_names[reg];
- case 1: return ireg8_names[reg];
- }
- bad:
- VG_(core_panic)("name_of_int_reg");
- return NULL; /*notreached*/
-}
-
-const Char* VG_(name_of_seg_reg) ( Int sreg )
-{
- switch (sreg) {
- case R_ES: return "%es";
- case R_CS: return "%cs";
- case R_SS: return "%ss";
- case R_DS: return "%ds";
- case R_FS: return "%fs";
- case R_GS: return "%gs";
- default: VG_(core_panic)("nameOfSegReg");
- }
-}
-
-const Char* VG_(name_of_mmx_reg) ( Int mmxreg )
-{
- static const Char* mmx_names[8]
- = { "%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7" };
- if (mmxreg < 0 || mmxreg > 7) VG_(core_panic)("name_of_mmx_reg");
- return mmx_names[mmxreg];
-}
-
-const Char* VG_(name_of_xmm_reg) ( Int xmmreg )
-{
- static const Char* xmm_names[8]
- = { "%xmm0", "%xmm1", "%xmm2", "%xmm3", "%xmm4", "%xmm5", "%xmm6", "%xmm7" };
- if (xmmreg < 0 || xmmreg > 7) VG_(core_panic)("name_of_xmm_reg");
- return xmm_names[xmmreg];
-}
-
-const Char* VG_(name_of_mmx_gran) ( UChar gran )
-{
- switch (gran) {
- case 0: return "b";
- case 1: return "w";
- case 2: return "d";
- case 3: return "q";
- default: VG_(core_panic)("name_of_mmx_gran");
- }
-}
-
-const Char VG_(name_of_int_size) ( Int size )
-{
- switch (size) {
- case 4: return 'l';
- case 2: return 'w';
- case 1: return 'b';
- default: VG_(core_panic)("name_of_int_size");
- }
-}
-
-__inline__ UInt VG_(extend_s_8to32) ( UInt x )
-{
- return (UInt)((((Int)x) << 24) >> 24);
-}
-
-__inline__ static UInt extend_s_16to32 ( UInt x )
-{
- return (UInt)((((Int)x) << 16) >> 16);
-}
-
-
-/* Get a byte value out of the insn stream and sign-extend to 32
- bits. */
-__inline__ static UInt getSDisp8 ( Addr eip0 )
-{
- UChar* eip = (UChar*)eip0;
- return VG_(extend_s_8to32)( (UInt) (eip[0]) );
-}
-
-__inline__ static UInt getSDisp16 ( Addr eip0 )
-{
- UChar* eip = (UChar*)eip0;
- UInt d = *eip++;
- d |= ((*eip++) << 8);
- return extend_s_16to32(d);
-}
-
-/* Get a 32-bit value out of the insn stream. */
-__inline__ static UInt getUDisp32 ( Addr eip0 )
-{
- UChar* eip = (UChar*)eip0;
- UInt v = eip[3]; v <<= 8;
- v |= eip[2]; v <<= 8;
- v |= eip[1]; v <<= 8;
- v |= eip[0];
- return v;
-}
-
-__inline__ static UInt getUDisp16 ( Addr eip0 )
-{
- UChar* eip = (UChar*)eip0;
- UInt v = eip[1]; v <<= 8;
- v |= eip[0];
- return v;
-}
-
-__inline__ static UChar getUChar ( Addr eip0 )
-{
- UChar* eip = (UChar*)eip0;
- return eip[0];
-}
-
-__inline__ static UInt LOW24 ( UInt x )
-{
- return x & 0x00FFFFFF;
-}
-
-__inline__ static UInt HI8 ( UInt x )
-{
- return x >> 24;
-}
-
-__inline__ static UInt getUDisp ( Int size, Addr eip )
-{
- switch (size) {
- case 4: return getUDisp32(eip);
- case 2: return getUDisp16(eip);
- case 1: return getUChar(eip);
- default: VG_(core_panic)("getUDisp");
- }
- return 0; /*notreached*/
-}
-
-__inline__ static UInt getSDisp ( Int size, Addr eip )
-{
- switch (size) {
- case 4: return getUDisp32(eip);
- case 2: return getSDisp16(eip);
- case 1: return getSDisp8(eip);
- default: VG_(core_panic)("getUDisp");
- }
- return 0; /*notreached*/
-}
-
-/*------------------------------------------------------------*/
-/*--- Flag-related helpers. ---*/
-/*------------------------------------------------------------*/
-
-static void setFlagsFromUOpcode ( UCodeBlock* cb, Int uopc )
-{
- switch (uopc) {
- case XOR: case OR: case AND:
- uFlagsRWU(cb, FlagsEmpty, FlagsOSZCP, FlagA); break;
- case ADC: case SBB:
- uFlagsRWU(cb, FlagC, FlagsOSZACP, FlagsEmpty); break;
- case MUL: case UMUL:
- uFlagsRWU(cb, FlagsEmpty, FlagsOC, FlagsSZAP); break;
- case ADD: case SUB: case NEG:
- uFlagsRWU(cb, FlagsEmpty, FlagsOSZACP, FlagsEmpty); break;
- case INC: case DEC:
- uFlagsRWU(cb, FlagsEmpty, FlagsOSZAP, FlagsEmpty); break;
- case SHR: case SAR: case SHL:
- uFlagsRWU(cb, FlagsEmpty, FlagsOSZCP, FlagA); break;
- case ROL: case ROR:
- uFlagsRWU(cb, FlagsEmpty, FlagsOC, FlagsEmpty); break;
- case RCR: case RCL:
- uFlagsRWU(cb, FlagC, FlagsOC, FlagsEmpty); break;
- case NOT:
- uFlagsRWU(cb, FlagsEmpty, FlagsEmpty, FlagsEmpty); break;
- default:
- VG_(printf)("unhandled case is %s\n",
- VG_(name_UOpcode)(True, uopc));
- VG_(core_panic)("setFlagsFromUOpcode: unhandled case");
- }
-}
-
-/*------------------------------------------------------------*/
-/*--- JMP helpers ---*/
-/*------------------------------------------------------------*/
-
-static __inline__
-void jmp_lit( UCodeBlock* cb, Addr d32 )
-{
- uInstr1 (cb, JMP, 0, Literal, 0);
- uLiteral(cb, d32);
- uCond (cb, CondAlways);
-}
-
-static __inline__
-void jmp_treg( UCodeBlock* cb, Int t )
-{
- uInstr1 (cb, JMP, 0, TempReg, t);
- uCond (cb, CondAlways);
-}
-
-static __inline__
-void jcc_lit( UCodeBlock* cb, Addr d32, Condcode cond )
-{
- uInstr1 (cb, JMP, 0, Literal, 0);
- uLiteral (cb, d32);
- uCond (cb, cond);
- uFlagsRWU(cb, FlagsOSZACP, FlagsEmpty, FlagsEmpty);
-}
-
-
-/*------------------------------------------------------------*/
-/*--- Disassembling addressing modes ---*/
-/*------------------------------------------------------------*/
-
-static
-UChar* sorbTxt ( UChar sorb )
-{
- switch (sorb) {
- case 0: return ""; /* no override */
- case 0x3E: return "%ds";
- case 0x26: return "%es:";
- case 0x64: return "%fs:";
- case 0x65: return "%gs:";
- default: VG_(core_panic)("sorbTxt");
- }
-}
-
-
-/* Tmp is a TempReg holding a virtual address. Convert it to a linear
- address by adding any required segment override as indicated by
- sorb. */
-static
-void handleSegOverride ( UCodeBlock* cb, UChar sorb, Int tmp )
-{
- Int sreg, tsreg;
-
- if (sorb == 0)
- /* the common case - no override */
- return;
-
- switch (sorb) {
- case 0x3E: sreg = R_DS; break;
- case 0x26: sreg = R_ES; break;
- case 0x64: sreg = R_FS; break;
- case 0x65: sreg = R_GS; break;
- default: VG_(core_panic)("handleSegOverride");
- }
-
- tsreg = newTemp(cb);
-
- /* sreg -> tsreg */
- uInstr2(cb, GETSEG, 2, ArchRegS, sreg, TempReg, tsreg );
-
- /* tmp += segment_base(ldt[tsreg]); also do limit check */
- uInstr2(cb, USESEG, 0, TempReg, tsreg, TempReg, tmp );
-}
-
-
-/* Generate ucode to calculate an address indicated by a ModRM and
- following SIB bytes, getting the value in a new temporary. The
- temporary, and the number of bytes in the address mode, are
- returned, as a pair (length << 24) | temp. Note that this fn should
- not be called if the R/M part of the address denotes a register
- instead of memory. If VG_(print_codegen) is true, text of the addressing
- mode is placed therein. */
-
-static
-UInt disAMode ( UCodeBlock* cb, UChar sorb, Addr eip0, UChar* buf )
-{
- UChar* eip = (UChar*)eip0;
- UChar mod_reg_rm = *eip++;
- Int tmp = newTemp(cb);
-
- /* squeeze out the reg field from mod_reg_rm, since a 256-entry
- jump table seems a bit excessive.
- */
- mod_reg_rm &= 0xC7; /* is now XX000YYY */
- mod_reg_rm |= (mod_reg_rm >> 3); /* is now XX0XXYYY */
- mod_reg_rm &= 0x1F; /* is now 000XXYYY */
- switch (mod_reg_rm) {
-
- /* (%eax) .. (%edi), not including (%esp) or (%ebp).
- --> GET %reg, t
- */
- case 0x00: case 0x01: case 0x02: case 0x03:
- /* ! 04 */ /* ! 05 */ case 0x06: case 0x07:
- { UChar rm = mod_reg_rm;
- uInstr2(cb, GET, 4, ArchReg, rm, TempReg, tmp);
- handleSegOverride(cb, sorb, tmp);
- DIS(buf, "%s(%s)", sorbTxt(sorb), nameIReg(4,rm));
- return (1<<24 | tmp);
- }
-
- /* d8(%eax) ... d8(%edi), not including d8(%esp)
- --> GET %reg, t ; ADDL d8, t
- */
- case 0x08: case 0x09: case 0x0A: case 0x0B:
- /* ! 0C */ case 0x0D: case 0x0E: case 0x0F:
- { UChar rm = mod_reg_rm & 7;
- Int tmq = newTemp(cb);
- UInt d = getSDisp8((Addr)eip); eip++;
- uInstr2(cb, GET, 4, ArchReg, rm, TempReg, tmq);
- uInstr2(cb, LEA1, 4, TempReg, tmq, TempReg, tmp);
- uLiteral(cb, d);
- handleSegOverride(cb, sorb, tmp);
- DIS(buf, "%s%d(%s)", sorbTxt(sorb), d, nameIReg(4,rm));
- return (2<<24 | tmp);
- }
-
- /* d32(%eax) ... d32(%edi), not including d32(%esp)
- --> GET %reg, t ; ADDL d8, t
- */
- case 0x10: case 0x11: case 0x12: case 0x13:
- /* ! 14 */ case 0x15: case 0x16: case 0x17:
- { UChar rm = mod_reg_rm & 7;
- Int tmq = newTemp(cb);
- UInt d = getUDisp32((Addr)eip); eip += 4;
- uInstr2(cb, GET, 4, ArchReg, rm, TempReg, tmq);
- uInstr2(cb, LEA1, 4, TempReg, tmq, TempReg, tmp);
- uLiteral(cb, d);
- handleSegOverride(cb, sorb, tmp);
- DIS(buf, "%s0x%x(%s)", sorbTxt(sorb), d, nameIReg(4,rm));
- return (5<<24 | tmp);
- }
-
- /* a register, %eax .. %edi. This shouldn't happen. */
- case 0x18: case 0x19: case 0x1A: case 0x1B:
- case 0x1C: case 0x1D: case 0x1E: case 0x1F:
- VG_(core_panic)("disAMode: not an addr!");
-
- /* a 32-bit literal address
- --> MOV d32, tmp
- */
- case 0x05:
- { UInt d = getUDisp32((Addr)eip); eip += 4;
- uInstr2(cb, MOV, 4, Literal, 0, TempReg, tmp);
- uLiteral(cb, d);
- handleSegOverride(cb, sorb, tmp);
- DIS(buf, "%s(0x%x)", sorbTxt(sorb), d);
- return (5<<24 | tmp);
- }
-
- case 0x04: {
- /* SIB, with no displacement. Special cases:
- -- %esp cannot act as an index value.
- If index_r indicates %esp, zero is used for the index.
- -- when mod is zero and base indicates EBP, base is instead
- a 32-bit literal.
- It's all madness, I tell you. Extract %index, %base and
- scale from the SIB byte. The value denoted is then:
- | %index == %ESP && %base == %EBP
- = d32 following SIB byte
- | %index == %ESP && %base != %EBP
- = %base
- | %index != %ESP && %base == %EBP
- = d32 following SIB byte + (%index << scale)
- | %index != %ESP && %base != %ESP
- = %base + (%index << scale)
-
- What happens to the souls of CPU architects who dream up such
- horrendous schemes, do you suppose?
- */
- UChar sib = *eip++;
- UChar scale = (sib >> 6) & 3;
- UChar index_r = (sib >> 3) & 7;
- UChar base_r = sib & 7;
-
- if (index_r != R_ESP && base_r != R_EBP) {
- Int index_tmp = newTemp(cb);
- Int base_tmp = newTemp(cb);
- uInstr2(cb, GET, 4, ArchReg, index_r, TempReg, index_tmp);
- uInstr2(cb, GET, 4, ArchReg, base_r, TempReg, base_tmp);
- uInstr3(cb, LEA2, 4, TempReg, base_tmp, TempReg, index_tmp,
- TempReg, tmp);
- uLiteral(cb, 0);
- LAST_UINSTR(cb).extra4b = 1 << scale;
- handleSegOverride(cb, sorb, tmp);
- DIS(buf, "%s(%s,%s,%d)", sorbTxt(sorb),
- nameIReg(4,base_r), nameIReg(4,index_r), 1<<scale);
- return (2<<24 | tmp);
- }
-
- if (index_r != R_ESP && base_r == R_EBP) {
- Int index_tmp = newTemp(cb);
- UInt d = getUDisp32((Addr)eip); eip += 4;
- uInstr2(cb, GET, 4, ArchReg, index_r, TempReg, index_tmp);
- uInstr2(cb, MOV, 4, Literal, 0, TempReg, tmp);
- uLiteral(cb, 0);
- uInstr3(cb, LEA2, 4, TempReg, tmp, TempReg, index_tmp,
- TempReg, tmp);
- uLiteral(cb, d);
- LAST_UINSTR(cb).extra4b = 1 << scale;
- handleSegOverride(cb, sorb, tmp);
- DIS(buf, "%s0x%x(,%s,%d)", sorbTxt(sorb), d,
- nameIReg(4,index_r), 1<<scale);
- return (6<<24 | tmp);
- }
-
- if (index_r == R_ESP && base_r != R_EBP) {
- uInstr2(cb, GET, 4, ArchReg, base_r, TempReg, tmp);
- handleSegOverride(cb, sorb, tmp);
- DIS(buf, "%s(%s,,)", sorbTxt(sorb), nameIReg(4,base_r));
- return (2<<24 | tmp);
- }
-
- if (index_r == R_ESP && base_r == R_EBP) {
- UInt d = getUDisp32((Addr)eip); eip += 4;
- uInstr2(cb, MOV, 4, Literal, 0, TempReg, tmp);
- uLiteral(cb, d);
- handleSegOverride(cb, sorb, tmp);
- DIS(buf, "%s0x%x()", sorbTxt(sorb), d);
- return (6<<24 | tmp);
- }
-
- vg_assert(0);
- }
-
- /* SIB, with 8-bit displacement. Special cases:
- -- %esp cannot act as an index value.
- If index_r indicates %esp, zero is used for the index.
- Denoted value is:
- | %index == %ESP
- = d8 + %base
- | %index != %ESP
- = d8 + %base + (%index << scale)
- */
- case 0x0C: {
- UChar sib = *eip++;
- UChar scale = (sib >> 6) & 3;
- UChar index_r = (sib >> 3) & 7;
- UChar base_r = sib & 7;
- UInt d = getSDisp8((Addr)eip); eip++;
-
- if (index_r == R_ESP) {
- Int tmq = newTemp(cb);
- uInstr2(cb, GET, 4, ArchReg, base_r, TempReg, tmq);
- uInstr2(cb, LEA1, 4, TempReg, tmq, TempReg, tmp);
- uLiteral(cb, d);
- handleSegOverride(cb, sorb, tmp);
- DIS(buf, "%s%d(%s,,)", sorbTxt(sorb), d, nameIReg(4,base_r));
- return (3<<24 | tmp);
- } else {
- Int index_tmp = newTemp(cb);
- Int base_tmp = newTemp(cb);
- uInstr2(cb, GET, 4, ArchReg, index_r, TempReg, index_tmp);
- uInstr2(cb, GET, 4, ArchReg, base_r, TempReg, base_tmp);
- uInstr3(cb, LEA2, 4, TempReg, base_tmp, TempReg, index_tmp,
- TempReg, tmp);
- uLiteral(cb, d);
- LAST_UINSTR(cb).extra4b = 1 << scale;
- handleSegOverride(cb, sorb, tmp);
- DIS(buf, "%s%d(%s,%s,%d)", sorbTxt(sorb), d,
- nameIReg(4,base_r), nameIReg(4,index_r), 1<<scale);
- return (3<<24 | tmp);
- }
- vg_assert(0);
- }
-
- /* SIB, with 32-bit displacement. Special cases:
- -- %esp cannot act as an index value.
- If index_r indicates %esp, zero is used for the index.
- Denoted value is:
- | %index == %ESP
- = d32 + %base
- | %index != %ESP
- = d32 + %base + (%index << scale)
- */
- case 0x14: {
- UChar sib = *eip++;
- UChar scale = (sib >> 6) & 3;
- UChar index_r = (sib >> 3) & 7;
- UChar base_r = sib & 7;
- UInt d = getUDisp32((Addr)eip); eip += 4;
-
- if (index_r == R_ESP) {
- Int tmq = newTemp(cb);
- uInstr2(cb, GET, 4, ArchReg, base_r, TempReg, tmq);
- uInstr2(cb, LEA1, 4, TempReg, tmq, TempReg, tmp);
- uLiteral(cb, d);
- handleSegOverride(cb, sorb, tmp);
- DIS(buf, "%s%d(%s,,)", sorbTxt(sorb), d, nameIReg(4,base_r));
- return (6<<24 | tmp);
- } else {
- Int index_tmp = newTemp(cb);
- Int base_tmp = newTemp(cb);
- uInstr2(cb, GET, 4, ArchReg, index_r, TempReg, index_tmp);
- uInstr2(cb, GET, 4, ArchReg, base_r, TempReg, base_tmp);
- uInstr3(cb, LEA2, 4, TempReg, base_tmp, TempReg, index_tmp,
- TempReg, tmp);
- uLiteral(cb, d);
- LAST_UINSTR(cb).extra4b = 1 << scale;
- handleSegOverride(cb, sorb, tmp);
- DIS(buf, "%s%d(%s,%s,%d)", sorbTxt(sorb), d,
- nameIReg(4,base_r), nameIReg(4,index_r), 1<<scale);
- return (6<<24 | tmp);
- }
- vg_assert(0);
- }
-
- default:
- VG_(core_panic)("disAMode");
- return 0; /*notreached*/
- }
-}
-
-
-/* Figure out the number of (insn-stream) bytes constituting the amode
- beginning at eip0. Is useful for getting hold of literals beyond
- the end of the amode before it has been disassembled. */
-
-static UInt lengthAMode ( Addr eip0 )
-{
- UChar* eip = (UChar*)eip0;
- UChar mod_reg_rm = *eip++;
-
- /* squeeze out the reg field from mod_reg_rm, since a 256-entry
- jump table seems a bit excessive.
- */
- mod_reg_rm &= 0xC7; /* is now XX000YYY */
- mod_reg_rm |= (mod_reg_rm >> 3); /* is now XX0XXYYY */
- mod_reg_rm &= 0x1F; /* is now 000XXYYY */
- switch (mod_reg_rm) {
-
- /* (%eax) .. (%edi), not including (%esp) or (%ebp). */
- case 0x00: case 0x01: case 0x02: case 0x03:
- /* ! 04 */ /* ! 05 */ case 0x06: case 0x07:
- return 1;
-
- /* d8(%eax) ... d8(%edi), not including d8(%esp). */
- case 0x08: case 0x09: case 0x0A: case 0x0B:
- /* ! 0C */ case 0x0D: case 0x0E: case 0x0F:
- return 2;
-
- /* d32(%eax) ... d32(%edi), not including d32(%esp). */
- case 0x10: case 0x11: case 0x12: case 0x13:
- /* ! 14 */ case 0x15: case 0x16: case 0x17:
- return 5;
-
- /* a register, %eax .. %edi. (Not an addr, but still handled.) */
- case 0x18: case 0x19: case 0x1A: case 0x1B:
- case 0x1C: case 0x1D: case 0x1E: case 0x1F:
- return 1;
-
- /* a 32-bit literal address. */
- case 0x05: return 5;
-
- /* SIB, no displacement. */
- case 0x04: {
- UChar sib = *eip++;
- UChar base_r = sib & 7;
- if (base_r == R_EBP) return 6; else return 2;
- }
- /* SIB, with 8-bit displacement. */
- case 0x0C: return 3;
-
- /* SIB, with 32-bit displacement. */
- case 0x14: return 6;
-
- default:
- VG_(core_panic)("amode_from_RM");
- return 0; /*notreached*/
- }
-}
-
-
-/* Extract the reg field from a modRM byte. */
-static __inline__ Int gregOfRM ( UChar mod_reg_rm )
-{
- return (Int)( (mod_reg_rm >> 3) & 7 );
-}
-
-/* Figure out whether the mod and rm parts of a modRM byte refer to a
- register or memory. If so, the byte will have the form 11XXXYYY,
- where YYY is the register number. */
-static __inline__ Bool epartIsReg ( UChar mod_reg_rm )
-{
- return (0xC0 == (mod_reg_rm & 0xC0));
-}
-
-/* ... and extract the register number ... */
-static __inline__ Int eregOfRM ( UChar mod_reg_rm )
-{
- return (Int)(mod_reg_rm & 0x7);
-}
-
-
-/*------------------------------------------------------------*/
-/*--- Disassembling common idioms ---*/
-/*------------------------------------------------------------*/
-
-static
-void codegen_XOR_reg_with_itself ( UCodeBlock* cb, Int size,
- Int ge_reg, Int tmp )
-{
- DIP("xor%c %s, %s\n", nameISize(size),
- nameIReg(size,ge_reg), nameIReg(size,ge_reg) );
- uInstr2(cb, MOV, size, Literal, 0, TempReg, tmp);
- uLiteral(cb, 0);
- uInstr2(cb, XOR, size, TempReg, tmp, TempReg, tmp);
- setFlagsFromUOpcode(cb, XOR);
- uInstr2(cb, PUT, size, TempReg, tmp, ArchReg, ge_reg);
-}
-
-/* Handle binary integer instructions of the form
- op E, G meaning
- op reg-or-mem, reg
- Is passed the a ptr to the modRM byte, the actual operation, and the
- data size. Returns the address advanced completely over this
- instruction.
-
- E(src) is reg-or-mem
- G(dst) is reg.
-
- If E is reg, --> GET %G, tmp
- OP %E, tmp
- PUT tmp, %G
-
- If E is mem and OP is not reversible,
- --> (getAddr E) -> tmpa
- LD (tmpa), tmpa
- GET %G, tmp2
- OP tmpa, tmp2
- PUT tmp2, %G
-
- If E is mem and OP is reversible
- --> (getAddr E) -> tmpa
- LD (tmpa), tmpa
- OP %G, tmpa
- PUT tmpa, %G
-*/
-static
-Addr dis_op2_E_G ( UCodeBlock* cb,
- UChar sorb,
- Opcode opc,
- Bool keep,
- Int size,
- Addr eip0,
- Char* t_x86opc )
-{
- Bool reversible;
- UChar rm = getUChar(eip0);
- UChar dis_buf[50];
-
- if (epartIsReg(rm)) {
- Int tmp = newTemp(cb);
-
- /* Specially handle XOR reg,reg, because that doesn't really
- depend on reg, and doing the obvious thing potentially
- generates a spurious value check failure due to the bogus
- dependency. */
- if (opc == XOR && gregOfRM(rm) == eregOfRM(rm)) {
- codegen_XOR_reg_with_itself ( cb, size, gregOfRM(rm), tmp );
- return 1+eip0;
- }
-
- uInstr2(cb, GET, size, ArchReg, gregOfRM(rm), TempReg, tmp);
- if (opc == AND || opc == OR) {
- Int tao = newTemp(cb);
- uInstr2(cb, GET, size, ArchReg, eregOfRM(rm), TempReg, tao);
- uInstr2(cb, opc, size, TempReg, tao, TempReg, tmp);
- setFlagsFromUOpcode(cb, opc);
- } else {
- uInstr2(cb, opc, size, ArchReg, eregOfRM(rm), TempReg, tmp);
- setFlagsFromUOpcode(cb, opc);
- }
- if (keep)
- uInstr2(cb, PUT, size, TempReg, tmp, ArchReg, gregOfRM(rm));
- DIP("%s%c %s,%s\n", t_x86opc, nameISize(size),
- nameIReg(size,eregOfRM(rm)),
- nameIReg(size,gregOfRM(rm)));
- return 1+eip0;
- }
-
- /* E refers to memory */
- reversible
- = (opc == ADD || opc == OR || opc == AND || opc == XOR || opc == ADC)
- ? True : False;
- if (reversible) {
- UInt pair = disAMode ( cb, sorb, eip0, dis_buf);
- Int tmpa = LOW24(pair);
- uInstr2(cb, LOAD, size, TempReg, tmpa, TempReg, tmpa);
-
- if (opc == AND || opc == OR) {
- Int tao = newTemp(cb);
- uInstr2(cb, GET, size, ArchReg, gregOfRM(rm), TempReg, tao);
- uInstr2(cb, opc, size, TempReg, tao, TempReg, tmpa);
- setFlagsFromUOpcode(cb, opc);
- } else {
- uInstr2(cb, opc, size, ArchReg, gregOfRM(rm), TempReg, tmpa);
- setFlagsFromUOpcode(cb, opc);
- }
- if (keep)
- uInstr2(cb, PUT, size, TempReg, tmpa, ArchReg, gregOfRM(rm));
- DIP("%s%c %s,%s\n", t_x86opc, nameISize(size),
- dis_buf,nameIReg(size,gregOfRM(rm)));
- return HI8(pair)+eip0;
- } else {
- UInt pair = disAMode ( cb, sorb, eip0, dis_buf);
- Int tmpa = LOW24(pair);
- Int tmp2 = newTemp(cb);
- uInstr2(cb, LOAD, size, TempReg, tmpa, TempReg, tmpa);
- uInstr2(cb, GET, size, ArchReg, gregOfRM(rm), TempReg, tmp2);
- uInstr2(cb, opc, size, TempReg, tmpa, TempReg, tmp2);
- setFlagsFromUOpcode(cb, opc);
- if (keep)
- uInstr2(cb, PUT, size, TempReg, tmp2, ArchReg, gregOfRM(rm));
- DIP("%s%c %s,%s\n", t_x86opc, nameISize(size),
- dis_buf,nameIReg(size,gregOfRM(rm)));
- return HI8(pair)+eip0;
- }
-}
-
-
-
-/* Handle binary integer instructions of the form
- op G, E meaning
- op reg, reg-or-mem
- Is passed the a ptr to the modRM byte, the actual operation, and the
- data size. Returns the address advanced completely over this
- instruction.
-
- G(src) is reg.
- E(dst) is reg-or-mem
-
- If E is reg, --> GET %E, tmp
- OP %G, tmp
- PUT tmp, %E
-
- If E is mem, --> (getAddr E) -> tmpa
- LD (tmpa), tmpv
- OP %G, tmpv
- ST tmpv, (tmpa)
-*/
-static
-Addr dis_op2_G_E ( UCodeBlock* cb,
- UChar sorb,
- Opcode opc,
- Bool keep,
- Int size,
- Addr eip0,
- Char* t_x86opc )
-{
- UChar rm = getUChar(eip0);
- UChar dis_buf[50];
-
- if (epartIsReg(rm)) {
- Int tmp = newTemp(cb);
-
- /* Specially handle XOR reg,reg, because that doesn't really
- depend on reg, and doing the obvious thing potentially
- generates a spurious value check failure due to the bogus
- dependency. */
- if (opc == XOR && gregOfRM(rm) == eregOfRM(rm)) {
- codegen_XOR_reg_with_itself ( cb, size, gregOfRM(rm), tmp );
- return 1+eip0;
- }
-
- /* gcc sometimes generates "sbbl %reg,%reg" to convert the carry
- flag into 0 or -1 in reg. This has no actual dependency on
- reg, but memcheck can't see that, and so will yelp if reg
- contains garbage. A simple fix is to put zero into reg
- before we start, zapping any undefinedness it might otherwise
- contain.
- */
- if (opc == SBB && gregOfRM(rm) == eregOfRM(rm)) {
- Int tzero = newTemp(cb);
- uInstr2(cb, MOV, size, Literal, 0, TempReg, tzero);
- uLiteral(cb, 0);
- uInstr2(cb, PUT, size, TempReg, tzero, ArchReg, eregOfRM(rm));
- }
-
- uInstr2(cb, GET, size, ArchReg, eregOfRM(rm), TempReg, tmp);
-
- if (opc == AND || opc == OR) {
- Int tao = newTemp(cb);
- uInstr2(cb, GET, size, ArchReg, gregOfRM(rm), TempReg, tao);
- uInstr2(cb, opc, size, TempReg, tao, TempReg, tmp);
- setFlagsFromUOpcode(cb, opc);
- } else {
- uInstr2(cb, opc, size, ArchReg, gregOfRM(rm), TempReg, tmp);
- setFlagsFromUOpcode(cb, opc);
- }
- if (keep)
- uInstr2(cb, PUT, size, TempReg, tmp, ArchReg, eregOfRM(rm));
- DIP("%s%c %s,%s\n", t_x86opc, nameISize(size),
- nameIReg(size,gregOfRM(rm)),
- nameIReg(size,eregOfRM(rm)));
- return 1+eip0;
- }
-
- /* E refers to memory */
- {
- UInt pair = disAMode ( cb, sorb, eip0, dis_buf);
- Int tmpa = LOW24(pair);
- Int tmpv = newTemp(cb);
- uInstr2(cb, LOAD, size, TempReg, tmpa, TempReg, tmpv);
-
- if (opc == AND || opc == OR) {
- Int tao = newTemp(cb);
- uInstr2(cb, GET, size, ArchReg, gregOfRM(rm), TempReg, tao);
- uInstr2(cb, opc, size, TempReg, tao, TempReg, tmpv);
- setFlagsFromUOpcode(cb, opc);
- } else {
- uInstr2(cb, opc, size, ArchReg, gregOfRM(rm), TempReg, tmpv);
- setFlagsFromUOpcode(cb, opc);
- }
- if (keep) {
- uInstr2(cb, STORE, size, TempReg, tmpv, TempReg, tmpa);
- }
- DIP("%s%c %s,%s\n", t_x86opc, nameISize(size),
- nameIReg(size,gregOfRM(rm)), dis_buf);
- return HI8(pair)+eip0;
- }
-}
-
-
-/* Handle move instructions of the form
- mov E, G meaning
- mov reg-or-mem, reg
- Is passed the a ptr to the modRM byte, and the data size. Returns
- the address advanced completely over this instruction.
-
- E(src) is reg-or-mem
- G(dst) is reg.
-
- If E is reg, --> GET %E, tmpv
- PUT tmpv, %G
-
- If E is mem --> (getAddr E) -> tmpa
- LD (tmpa), tmpb
- PUT tmpb, %G
-*/
-static
-Addr dis_mov_E_G ( UCodeBlock* cb,
- UChar sorb,
- Int size,
- Addr eip0 )
-{
- UChar rm = getUChar(eip0);
- UChar dis_buf[50];
-
- if (epartIsReg(rm)) {
- Int tmpv = newTemp(cb);
- uInstr2(cb, GET, size, ArchReg, eregOfRM(rm), TempReg, tmpv);
- uInstr2(cb, PUT, size, TempReg, tmpv, ArchReg, gregOfRM(rm));
- DIP("mov%c %s,%s\n", nameISize(size),
- nameIReg(size,eregOfRM(rm)),
- nameIReg(size,gregOfRM(rm)));
- return 1+eip0;
- }
-
- /* E refers to memory */
- {
- UInt pair = disAMode ( cb, sorb, eip0, dis_buf);
- Int tmpa = LOW24(pair);
- Int tmpb = newTemp(cb);
- uInstr2(cb, LOAD, size, TempReg, tmpa, TempReg, tmpb);
- uInstr2(cb, PUT, size, TempReg, tmpb, ArchReg, gregOfRM(rm));
- DIP("mov%c %s,%s\n", nameISize(size),
- dis_buf,nameIReg(size,gregOfRM(rm)));
- return HI8(pair)+eip0;
- }
-}
-
-
-/* Handle move instructions of the form
- mov G, E meaning
- mov reg, reg-or-mem
- Is passed the a ptr to the modRM byte, and the data size. Returns
- the address advanced completely over this instruction.
-
- G(src) is reg.
- E(dst) is reg-or-mem
-
- If E is reg, --> GET %G, tmp
- PUT tmp, %E
-
- If E is mem, --> (getAddr E) -> tmpa
- GET %G, tmpv
- ST tmpv, (tmpa)
-*/
-static
-Addr dis_mov_G_E ( UCodeBlock* cb,
- UChar sorb,
- Int size,
- Addr eip0 )
-{
- UChar rm = getUChar(eip0);
- UChar dis_buf[50];
-
- if (epartIsReg(rm)) {
- Int tmpv = newTemp(cb);
- uInstr2(cb, GET, size, ArchReg, gregOfRM(rm), TempReg, tmpv);
- uInstr2(cb, PUT, size, TempReg, tmpv, ArchReg, eregOfRM(rm));
- DIP("mov%c %s,%s\n", nameISize(size),
- nameIReg(size,gregOfRM(rm)),
- nameIReg(size,eregOfRM(rm)));
- return 1+eip0;
- }
-
- /* E refers to memory */
- {
- UInt pair = disAMode ( cb, sorb, eip0, dis_buf);
- Int tmpa = LOW24(pair);
- Int tmpv = newTemp(cb);
- uInstr2(cb, GET, size, ArchReg, gregOfRM(rm), TempReg, tmpv);
- uInstr2(cb, STORE, size, TempReg, tmpv, TempReg, tmpa);
- DIP("mov%c %s,%s\n", nameISize(size),
- nameIReg(size,gregOfRM(rm)), dis_buf);
- return HI8(pair)+eip0;
- }
-}
-
-
-/* op $immediate, AL/AX/EAX. */
-static
-Addr dis_op_imm_A ( UCodeBlock* cb,
- Int size,
- Opcode opc,
- Bool keep,
- Addr eip,
- Char* t_x86opc )
-{
- Int tmp = newTemp(cb);
- UInt lit = getUDisp(size,eip);
- uInstr2(cb, GET, size, ArchReg, R_EAX, TempReg, tmp);
- if (opc == AND || opc == OR) {
- Int tao = newTemp(cb);
- uInstr2(cb, MOV, size, Literal, 0, TempReg, tao);
- uLiteral(cb, lit);
- uInstr2(cb, opc, size, TempReg, tao, TempReg, tmp);
- setFlagsFromUOpcode(cb, opc);
- } else {
- uInstr2(cb, opc, size, Literal, 0, TempReg, tmp);
- uLiteral(cb, lit);
- setFlagsFromUOpcode(cb, opc);
- }
- if (keep)
- uInstr2(cb, PUT, size, TempReg, tmp, ArchReg, R_EAX);
- DIP("%s%c $0x%x, %s\n", t_x86opc, nameISize(size),
- lit, nameIReg(size,R_EAX));
- return eip+size;
-}
-
-
-/* Sign- and Zero-extending moves. */
-static
-Addr dis_movx_E_G ( UCodeBlock* cb,
- UChar sorb,
- Addr eip, Int szs, Int szd, Bool sign_extend )
-{
- UChar dis_buf[50];
- UChar rm = getUChar(eip);
- if (epartIsReg(rm)) {
- Int tmpv = newTemp(cb);
- uInstr2(cb, GET, szs, ArchReg, eregOfRM(rm), TempReg, tmpv);
- uInstr1(cb, WIDEN, szd, TempReg, tmpv);
- uWiden(cb, szs, sign_extend);
- uInstr2(cb, PUT, szd, TempReg, tmpv, ArchReg, gregOfRM(rm));
- DIP("mov%c%c%c %s,%s\n", sign_extend ? 's' : 'z',
- nameISize(szs), nameISize(szd),
- nameIReg(szs,eregOfRM(rm)),
- nameIReg(szd,gregOfRM(rm)));
- return 1+eip;
- }
-
- /* E refers to memory */
- {
- UInt pair = disAMode ( cb, sorb, eip, dis_buf);
- Int tmpa = LOW24(pair);
- uInstr2(cb, LOAD, szs, TempReg, tmpa, TempReg, tmpa);
- uInstr1(cb, WIDEN, szd, TempReg, tmpa);
- uWiden(cb, szs, sign_extend);
- uInstr2(cb, PUT, szd, TempReg, tmpa, ArchReg, gregOfRM(rm));
- DIP("mov%c%c%c %s,%s\n", sign_extend ? 's' : 'z',
- nameISize(szs), nameISize(szd),
- dis_buf, nameIReg(szd,gregOfRM(rm)));
- return HI8(pair)+eip;
- }
-}
-
-
-/* Generate code to divide ArchRegs EDX:EAX / DX:AX / AX by the 32 /
- 16 / 8 bit quantity in the given TempReg. */
-static
-void codegen_div ( UCodeBlock* cb, Int sz, Int t, Bool signed_divide )
-{
- Int helper;
- Int ta = newTemp(cb);
- Int td = newTemp(cb);
-
- switch (sz) {
- case 4: helper = (signed_divide ? VGOFF_(helper_idiv_64_32)
- : VGOFF_(helper_div_64_32));
- break;
- case 2: helper = (signed_divide ? VGOFF_(helper_idiv_32_16)
- : VGOFF_(helper_div_32_16));
- break;
- case 1: helper = (signed_divide ? VGOFF_(helper_idiv_16_8)
- : VGOFF_(helper_div_16_8));
- break;
- default: VG_(core_panic)("codegen_div");
- }
- uInstr0(cb, CALLM_S, 0);
- if (sz == 4 || sz == 2) {
- uInstr1(cb, PUSH, sz, TempReg, t);
- uInstr2(cb, GET, sz, ArchReg, R_EAX, TempReg, ta);
- uInstr1(cb, PUSH, sz, TempReg, ta);
- uInstr2(cb, GET, sz, ArchReg, R_EDX, TempReg, td);
- uInstr1(cb, PUSH, sz, TempReg, td);
- uInstr1(cb, CALLM, 0, Lit16, helper);
- uFlagsRWU(cb, FlagsEmpty, FlagsEmpty, FlagsOSZACP);
- uInstr1(cb, POP, sz, TempReg, t);
- uInstr2(cb, PUT, sz, TempReg, t, ArchReg, R_EDX);
- uInstr1(cb, POP, sz, TempReg, t);
- uInstr2(cb, PUT, sz, TempReg, t, ArchReg, R_EAX);
- uInstr1(cb, CLEAR, 0, Lit16, 4);
- } else {
- uInstr1(cb, PUSH, 1, TempReg, t);
- uInstr2(cb, GET, 2, ArchReg, R_EAX, TempReg, ta);
- uInstr1(cb, PUSH, 2, TempReg, ta);
- uInstr2(cb, MOV, 1, Literal, 0, TempReg, td);
- uLiteral(cb, 0);
- uInstr1(cb, PUSH, 1, TempReg, td);
- uInstr1(cb, CALLM, 0, Lit16, helper);
- uFlagsRWU(cb, FlagsEmpty, FlagsEmpty, FlagsOSZACP);
- uInstr1(cb, POP, 1, TempReg, t);
- uInstr2(cb, PUT, 1, TempReg, t, ArchReg, R_AL);
- uInstr1(cb, POP, 1, TempReg, t);
- uInstr2(cb, PUT, 1, TempReg, t, ArchReg, R_AH);
- uInstr1(cb, CLEAR, 0, Lit16, 4);
- }
- uInstr0(cb, CALLM_E, 0);
-}
-
-
-static
-Addr dis_Grp1 ( UCodeBlock* cb,
- UChar sorb,
- Addr eip, UChar modrm,
- Int am_sz, Int d_sz, Int sz, UInt d32 )
-{
- Int t1, t2, uopc;
- UInt pair;
- UChar dis_buf[50];
- if (epartIsReg(modrm)) {
- vg_assert(am_sz == 1);
- t1 = newTemp(cb);
- uInstr2(cb, GET, sz, ArchReg, eregOfRM(modrm), TempReg, t1);
- switch (gregOfRM(modrm)) {
- case 0: uopc = ADD; break; case 1: uopc = OR; break;
- case 2: uopc = ADC; break; case 3: uopc = SBB; break;
- case 4: uopc = AND; break; case 5: uopc = SUB; break;
- case 6: uopc = XOR; break; case 7: uopc = SUB; break;
- default: VG_(core_panic)("dis_Grp1(Reg): unhandled case");
- }
- if (uopc == AND || uopc == OR) {
- Int tao = newTemp(cb);
- uInstr2(cb, MOV, sz, Literal, 0, TempReg, tao);
- uLiteral(cb, d32);
- uInstr2(cb, uopc, sz, TempReg, tao, TempReg, t1);
- setFlagsFromUOpcode(cb, uopc);
- } else {
- uInstr2(cb, uopc, sz, Literal, 0, TempReg, t1);
- uLiteral(cb, d32);
- setFlagsFromUOpcode(cb, uopc);
- }
- if (gregOfRM(modrm) < 7)
- uInstr2(cb, PUT, sz, TempReg, t1, ArchReg, eregOfRM(modrm));
- eip += (am_sz + d_sz);
- DIP("%s%c $0x%x, %s\n", nameGrp1(gregOfRM(modrm)), nameISize(sz), d32,
- nameIReg(sz,eregOfRM(modrm)));
- } else {
- pair = disAMode ( cb, sorb, eip, dis_buf);
- t1 = LOW24(pair);
- t2 = newTemp(cb);
- eip += HI8(pair);
- eip += d_sz;
- uInstr2(cb, LOAD, sz, TempReg, t1, TempReg, t2);
- switch (gregOfRM(modrm)) {
- case 0: uopc = ADD; break; case 1: uopc = OR; break;
- case 2: uopc = ADC; break; case 3: uopc = SBB; break;
- case 4: uopc = AND; break; case 5: uopc = SUB; break;
- case 6: uopc = XOR; break; case 7: uopc = SUB; break;
- default: VG_(core_panic)("dis_Grp1(Mem): unhandled case");
- }
- if (uopc == AND || uopc == OR) {
- Int tao = newTemp(cb);
- uInstr2(cb, MOV, sz, Literal, 0, TempReg, tao);
- uLiteral(cb, d32);
- uInstr2(cb, uopc, sz, TempReg, tao, TempReg, t2);
- setFlagsFromUOpcode(cb, uopc);
- } else {
- uInstr2(cb, uopc, sz, Literal, 0, TempReg, t2);
- uLiteral(cb, d32);
- setFlagsFromUOpcode(cb, uopc);
- }
- if (gregOfRM(modrm) < 7) {
- uInstr2(cb, STORE, sz, TempReg, t2, TempReg, t1);
- }
- DIP("%s%c $0x%x, %s\n", nameGrp1(gregOfRM(modrm)), nameISize(sz),
- d32, dis_buf);
- }
- return eip;
-}
-
-
-/* Group 2 extended opcodes. */
-static
-Addr dis_Grp2 ( UCodeBlock* cb,
- UChar sorb,
- Addr eip, UChar modrm,
- Int am_sz, Int d_sz, Int sz,
- Tag orig_src_tag, UInt orig_src_val )
-{
- /* orig_src_tag and orig_src_val denote either ArchReg(%CL) or a
- Literal. And eip on entry points at the modrm byte. */
- Int t1, t2, uopc;
- UInt pair;
- UChar dis_buf[50];
- UInt src_val;
- Tag src_tag;
-
- /* Get the amount to be shifted by into src_tag/src_val. */
- if (orig_src_tag == ArchReg) {
- src_val = newTemp(cb);
- src_tag = TempReg;
- uInstr2(cb, GET, 1, orig_src_tag, orig_src_val, TempReg, src_val);
- } else {
- src_val = orig_src_val;
- src_tag = Literal;
- }
-
- if (epartIsReg(modrm)) {
- vg_assert(am_sz == 1);
- t1 = newTemp(cb);
- uInstr2(cb, GET, sz, ArchReg, eregOfRM(modrm), TempReg, t1);
- switch (gregOfRM(modrm)) {
- case 0: uopc = ROL; break; case 1: uopc = ROR; break;
- case 2: uopc = RCL; break; case 3: uopc = RCR; break;
- case 4: uopc = SHL; break; case 5: uopc = SHR; break;
- case 7: uopc = SAR; break;
- default: VG_(core_panic)("dis_Grp2(Reg): unhandled case");
- }
- if (src_tag == Literal) {
- uInstr2(cb, uopc, sz, Literal, 0, TempReg, t1);
- uLiteral(cb, src_val);
- } else {
- uInstr2(cb, uopc, sz, src_tag, src_val, TempReg, t1);
- }
- setFlagsFromUOpcode(cb, uopc);
- uInstr2(cb, PUT, sz, TempReg, t1, ArchReg, eregOfRM(modrm));
- eip += (am_sz + d_sz);
- if (VG_(print_codegen)) {
- if (orig_src_tag == Literal)
- VG_(printf)("%s%c $0x%x, %s\n",
- nameGrp2(gregOfRM(modrm)), nameISize(sz),
- orig_src_val, nameIReg(sz,eregOfRM(modrm)));
- else
- VG_(printf)("%s%c %s, %s\n",
- nameGrp2(gregOfRM(modrm)), nameISize(sz),
- nameIReg(1,orig_src_val),
- nameIReg(sz,eregOfRM(modrm)));
- }
- } else {
- pair = disAMode ( cb, sorb, eip, dis_buf);
- t1 = LOW24(pair);
- t2 = newTemp(cb);
- eip += HI8(pair);
- eip += d_sz;
- uInstr2(cb, LOAD, sz, TempReg, t1, TempReg, t2);
- switch (gregOfRM(modrm)) {
- case 0: uopc = ROL; break; case 1: uopc = ROR; break;
- case 2: uopc = RCL; break; case 3: uopc = RCR; break;
- case 4: uopc = SHL; break; case 5: uopc = SHR; break;
- case 7: uopc = SAR; break;
- default: VG_(core_panic)("dis_Grp2(Reg): unhandled case");
- }
- if (src_tag == Literal) {
- uInstr2(cb, uopc, sz, Literal, 0, TempReg, t2);
- uLiteral(cb, src_val);
- } else {
- uInstr2(cb, uopc, sz, src_tag, src_val, TempReg, t2);
- }
- setFlagsFromUOpcode(cb, uopc);
- uInstr2(cb, STORE, sz, TempReg, t2, TempReg, t1);
- if (VG_(print_codegen)) {
- if (orig_src_tag == Literal)
- VG_(printf)("%s%c $0x%x, %s\n",
- nameGrp2(gregOfRM(modrm)), nameISize(sz),
- orig_src_val, dis_buf);
- else
- VG_(printf)("%s%c %s, %s\n",
- nameGrp2(gregOfRM(modrm)), nameISize(sz),
- nameIReg(1,orig_src_val),
- dis_buf);
- }
- }
- return eip;
-}
-
-
-
-/* Group 8 extended opcodes (but BT/BTS/BTC/BTR only). */
-static
-Addr dis_Grp8_BT ( UCodeBlock* cb,
- UChar sorb,
- Addr eip, UChar modrm,
- Int am_sz, Int sz, UInt src_val )
-{
-# define MODIFY_t2_AND_SET_CARRY_FLAG \
- /* t2 is the value to be op'd on. Copy to t_fetched, then \
- modify t2, if non-BT. */ \
- uInstr2(cb, MOV, 4, TempReg, t2, TempReg, t_fetched); \
- uInstr2(cb, MOV, sz, Literal, 0, TempReg, t_mask); \
- uLiteral(cb, v_mask); \
- switch (gregOfRM(modrm)) { \
- case 4: /* BT */ break; \
- case 5: /* BTS */ \
- uInstr2(cb, OR, sz, TempReg, t_mask, TempReg, t2); break; \
- case 6: /* BTR */ \
- uInstr2(cb, AND, sz, TempReg, t_mask, TempReg, t2); break; \
- case 7: /* BTC */ \
- uInstr2(cb, XOR, sz, TempReg, t_mask, TempReg, t2); break; \
- } \
- /* Copy relevant bit from t_fetched into carry flag. */ \
- uInstr2(cb, SHR, sz, Literal, 0, TempReg, t_fetched); \
- uLiteral(cb, src_val); \
- uInstr2(cb, MOV, sz, Literal, 0, TempReg, t_mask); \
- uLiteral(cb, 1); \
- uInstr2(cb, AND, sz, TempReg, t_mask, TempReg, t_fetched); \
- uInstr1(cb, NEG, sz, TempReg, t_fetched); \
- setFlagsFromUOpcode(cb, NEG);
-
-
- /* src_val denotes a d8.
- And eip on entry points at the modrm byte. */
- Int t1, t2, t_fetched, t_mask;
- UInt pair;
- Char dis_buf[50];
- UInt v_mask;
-
- /* There is no 1-byte form of this instruction, AFAICS. */
- vg_assert(sz == 2 || sz == 4);
-
- /* Limit src_val -- the bit offset -- to something within a word.
- The Intel docs say that literal offsets larger than a word are
- masked in this way. */
- switch (sz) {
- case 2: src_val &= 15; break;
- case 4: src_val &= 31; break;
- default: VG_(core_panic)("dis_Grp8_BT: invalid size");
- }
-
- /* Invent a mask suitable for the operation. */
-
- switch (gregOfRM(modrm)) {
- case 4: /* BT */ v_mask = 0; break;
- case 5: /* BTS */ v_mask = 1 << src_val; break;
- case 6: /* BTR */ v_mask = ~(1 << src_val); break;
- case 7: /* BTC */ v_mask = 1 << src_val; break;
- /* If this needs to be extended, probably simplest to make a
- new function to handle the other cases (0 .. 3). The
- Intel docs do however not indicate any use for 0 .. 3, so
- we don't expect this to happen. */
- default: VG_(core_panic)("dis_Grp8_BT");
- }
- /* Probably excessively paranoid. */
- if (sz == 2)
- v_mask &= 0x0000FFFF;
-
- t1 = INVALID_TEMPREG;
- t_fetched = newTemp(cb);
- t_mask = newTemp(cb);
-
- if (epartIsReg(modrm)) {
- vg_assert(am_sz == 1);
- t2 = newTemp(cb);
-
- /* Fetch the value to be tested and modified. */
- uInstr2(cb, GET, sz, ArchReg, eregOfRM(modrm), TempReg, t2);
- /* Do it! */
- MODIFY_t2_AND_SET_CARRY_FLAG;
- /* Dump the result back, if non-BT. */
- if (gregOfRM(modrm) != 4 /* BT */)
- uInstr2(cb, PUT, sz, TempReg, t2, ArchReg, eregOfRM(modrm));
-
- eip += (am_sz + 1);
- DIP("%s%c $0x%x, %s\n", nameGrp8(gregOfRM(modrm)), nameISize(sz),
- src_val, nameIReg(sz,eregOfRM(modrm)));
- } else {
- pair = disAMode ( cb, sorb, eip, dis_buf);
- t1 = LOW24(pair);
- t2 = newTemp(cb);
- eip += HI8(pair);
- eip += 1;
-
- /* Fetch the value to be tested and modified. */
- uInstr2(cb, LOAD, sz, TempReg, t1, TempReg, t2);
- /* Do it! */
- MODIFY_t2_AND_SET_CARRY_FLAG;
- /* Dump the result back, if non-BT. */
- if (gregOfRM(modrm) != 4 /* BT */) {
- uInstr2(cb, STORE, sz, TempReg, t2, TempReg, t1);
- }
- DIP("%s%c $0x%x, %s\n", nameGrp8(gregOfRM(modrm)), nameISize(sz),
- src_val, dis_buf);
- }
- return eip;
-
-# undef MODIFY_t2_AND_SET_CARRY_FLAG
-}
-
-
-
-/* Generate ucode to multiply the value in EAX/AX/AL by the register
- specified by the ereg of modrm, and park the result in
- EDX:EAX/DX:AX/AX. */
-static void codegen_mul_A_D_Reg ( UCodeBlock* cb, Int sz,
- UChar modrm, Bool signed_multiply )
-{
- Int helper = signed_multiply
- ?
- (sz==1 ? VGOFF_(helper_imul_8_16)
- : (sz==2 ? VGOFF_(helper_imul_16_32)
- : VGOFF_(helper_imul_32_64)))
- :
- (sz==1 ? VGOFF_(helper_mul_8_16)
- : (sz==2 ? VGOFF_(helper_mul_16_32)
- : VGOFF_(helper_mul_32_64)));
- Int t1 = newTemp(cb);
- Int ta = newTemp(cb);
- uInstr0(cb, CALLM_S, 0);
- uInstr2(cb, GET, sz, ArchReg, eregOfRM(modrm), TempReg, t1);
- uInstr1(cb, PUSH, sz, TempReg, t1);
- uInstr2(cb, GET, sz, ArchReg, R_EAX, TempReg, ta);
- uInstr1(cb, PUSH, sz, TempReg, ta);
- uInstr1(cb, CALLM, 0, Lit16, helper);
- uFlagsRWU(cb, FlagsEmpty, FlagsOC, FlagsSZAP);
- if (sz > 1) {
- uInstr1(cb, POP, sz, TempReg, t1);
- uInstr2(cb, PUT, sz, TempReg, t1, ArchReg, R_EDX);
- uInstr1(cb, POP, sz, TempReg, t1);
- uInstr2(cb, PUT, sz, TempReg, t1, ArchReg, R_EAX);
- } else {
- uInstr1(cb, CLEAR, 0, Lit16, 4);
- uInstr1(cb, POP, 2, TempReg, t1);
- uInstr2(cb, PUT, 2, TempReg, t1, ArchReg, R_EAX);
- }
- uInstr0(cb, CALLM_E, 0);
- DIP("%s%c %s\n", signed_multiply ? "imul" : "mul",
- nameISize(sz), nameIReg(sz, eregOfRM(modrm)));
-
-}
-
-
-/* Generate ucode to multiply the value in EAX/AX/AL by the value in
- TempReg temp, and park the result in EDX:EAX/DX:AX/AX. */
-static void codegen_mul_A_D_Temp ( UCodeBlock* cb, Int sz,
- Int temp, Bool signed_multiply,
- UChar* dis_buf )
-{
- Int helper = signed_multiply
- ?
- (sz==1 ? VGOFF_(helper_imul_8_16)
- : (sz==2 ? VGOFF_(helper_imul_16_32)
- : VGOFF_(helper_imul_32_64)))
- :
- (sz==1 ? VGOFF_(helper_mul_8_16)
- : (sz==2 ? VGOFF_(helper_mul_16_32)
- : VGOFF_(helper_mul_32_64)));
- Int t1 = newTemp(cb);
- uInstr0(cb, CALLM_S, 0);
- uInstr1(cb, PUSH, sz, TempReg, temp);
- uInstr2(cb, GET, sz, ArchReg, R_EAX, TempReg, t1);
- uInstr1(cb, PUSH, sz, TempReg, t1);
- uInstr1(cb, CALLM, 0, Lit16, helper);
- uFlagsRWU(cb, FlagsEmpty, FlagsOC, FlagsSZAP);
- if (sz > 1) {
- uInstr1(cb, POP, sz, TempReg, t1);
- uInstr2(cb, PUT, sz, TempReg, t1, ArchReg, R_EDX);
- uInstr1(cb, POP, sz, TempReg, t1);
- uInstr2(cb, PUT, sz, TempReg, t1, ArchReg, R_EAX);
- } else {
- uInstr1(cb, CLEAR, 0, Lit16, 4);
- uInstr1(cb, POP, 2, TempReg, t1);
- uInstr2(cb, PUT, 2, TempReg, t1, ArchReg, R_EAX);
- }
- uInstr0(cb, CALLM_E, 0);
- DIP("%s%c %s\n", signed_multiply ? "imul" : "mul",
- nameISize(sz), dis_buf);
-}
-
-
-/* Group 3 extended opcodes. */
-static
-Addr dis_Grp3 ( UCodeBlock* cb,
- UChar sorb,
- Int sz, Addr eip )
-{
- Int t1, t2;
- UInt pair, d32;
- UChar modrm;
- UChar dis_buf[50];
- t1 = t2 = INVALID_TEMPREG;
- modrm = getUChar(eip);
- if (epartIsReg(modrm)) {
- t1 = newTemp(cb);
- switch (gregOfRM(modrm)) {
- case 0: { /* TEST */
- Int tao = newTemp(cb);
- eip++; d32 = getUDisp(sz, eip); eip += sz;
- uInstr2(cb, GET, sz, ArchReg, eregOfRM(modrm), TempReg, t1);
- uInstr2(cb, MOV, sz, Literal, 0, TempReg, tao);
- uLiteral(cb, d32);
- uInstr2(cb, AND, sz, TempReg, tao, TempReg, t1);
- setFlagsFromUOpcode(cb, AND);
- DIP("test%c $0x%x, %s\n",
- nameISize(sz), d32, nameIReg(sz, eregOfRM(modrm)));
- break;
- }
- case 2: /* NOT */
- eip++;
- uInstr2(cb, GET, sz, ArchReg, eregOfRM(modrm), TempReg, t1);
- uInstr1(cb, NOT, sz, TempReg, t1);
- setFlagsFromUOpcode(cb, NOT);
- uInstr2(cb, PUT, sz, TempReg, t1, ArchReg, eregOfRM(modrm));
- DIP("not%c %s\n", nameISize(sz), nameIReg(sz, eregOfRM(modrm)));
- break;
- case 3: /* NEG */
- eip++;
- uInstr2(cb, GET, sz, ArchReg, eregOfRM(modrm), TempReg, t1);
- uInstr1(cb, NEG, sz, TempReg, t1);
- setFlagsFromUOpcode(cb, NEG);
- uInstr2(cb, PUT, sz, TempReg, t1, ArchReg, eregOfRM(modrm));
- DIP("neg%c %s\n", nameISize(sz), nameIReg(sz, eregOfRM(modrm)));
- break;
- case 4: /* MUL */
- eip++;
- codegen_mul_A_D_Reg ( cb, sz, modrm, False );
- break;
- case 5: /* IMUL */
- eip++;
- codegen_mul_A_D_Reg ( cb, sz, modrm, True );
- break;
- case 6: /* DIV */
- eip++;
- uInstr2(cb, GET, sz, ArchReg, eregOfRM(modrm), TempReg, t1);
- codegen_div ( cb, sz, t1, False );
- DIP("div%c %s\n", nameISize(sz), nameIReg(sz, eregOfRM(modrm)));
- break;
- case 7: /* IDIV */
- eip++;
- uInstr2(cb, GET, sz, ArchReg, eregOfRM(modrm), TempReg, t1);
- codegen_div ( cb, sz, t1, True );
- DIP("idiv%c %s\n", nameISize(sz), nameIReg(sz, eregOfRM(modrm)));
- break;
- default:
- VG_(printf)(
- "unhandled Grp3(R) case %d\n", (UInt)gregOfRM(modrm));
- VG_(core_panic)("Grp3");
- }
- } else {
- pair = disAMode ( cb, sorb, eip, dis_buf );
- t2 = LOW24(pair);
- t1 = newTemp(cb);
- eip += HI8(pair);
- uInstr2(cb, LOAD, sz, TempReg, t2, TempReg, t1);
- switch (gregOfRM(modrm)) {
- case 0: { /* TEST */
- Int tao = newTemp(cb);
- d32 = getUDisp(sz, eip); eip += sz;
- uInstr2(cb, MOV, sz, Literal, 0, TempReg, tao);
- uLiteral(cb, d32);
- uInstr2(cb, AND, sz, TempReg, tao, TempReg, t1);
- setFlagsFromUOpcode(cb, AND);
- DIP("test%c $0x%x, %s\n", nameISize(sz), d32, dis_buf);
- break;
- }
- case 2: /* NOT */
- uInstr1(cb, NOT, sz, TempReg, t1);
- setFlagsFromUOpcode(cb, NOT);
- uInstr2(cb, STORE, sz, TempReg, t1, TempReg, t2);
- DIP("not%c %s\n", nameISize(sz), dis_buf);
- break;
- case 3: /* NEG */
- uInstr1(cb, NEG, sz, TempReg, t1);
- setFlagsFromUOpcode(cb, NEG);
- uInstr2(cb, STORE, sz, TempReg, t1, TempReg, t2);
- DIP("neg%c %s\n", nameISize(sz), dis_buf);
- break;
- case 4: /* MUL */
- codegen_mul_A_D_Temp ( cb, sz, t1, False,
- dis_buf );
- break;
- case 5: /* IMUL */
- codegen_mul_A_D_Temp ( cb, sz, t1, True, dis_buf );
- break;
- case 6: /* DIV */
- codegen_div ( cb, sz, t1, False );
- DIP("div%c %s\n", nameISize(sz), dis_buf);
- break;
- case 7: /* IDIV */
- codegen_div ( cb, sz, t1, True );
- DIP("idiv%c %s\n", nameISize(sz), dis_buf);
- break;
- default:
- VG_(printf)(
- "unhandled Grp3(M) case %d\n", (UInt)gregOfRM(modrm));
- VG_(core_panic)("Grp3");
- }
- }
- return eip;
-}
-
-
-/* Group 4 extended opcodes. */
-static
-Addr dis_Grp4 ( UCodeBlock* cb,
- UChar sorb,
- Addr eip )
-{
- Int t1, t2;
- UInt pair;
- UChar modrm;
- UChar dis_buf[50];
- t1 = t2 = INVALID_TEMPREG;
-
- modrm = getUChar(eip);
- if (epartIsReg(modrm)) {
- t1 = newTemp(cb);
- uInstr2(cb, GET, 1, ArchReg, eregOfRM(modrm), TempReg, t1);
- switch (gregOfRM(modrm)) {
- case 0: /* INC */
- uInstr1(cb, INC, 1, TempReg, t1);
- setFlagsFromUOpcode(cb, INC);
- uInstr2(cb, PUT, 1, TempReg, t1, ArchReg, eregOfRM(modrm));
- break;
- case 1: /* DEC */
- uInstr1(cb, DEC, 1, TempReg, t1);
- setFlagsFromUOpcode(cb, DEC);
- uInstr2(cb, PUT, 1, TempReg, t1, ArchReg, eregOfRM(modrm));
- break;
- default:
- VG_(printf)(
- "unhandled Grp4(R) case %d\n", (UInt)gregOfRM(modrm));
- VG_(core_panic)("Grp4");
- }
- eip++;
- DIP("%sb %s\n", nameGrp4(gregOfRM(modrm)),
- nameIReg(1, eregOfRM(modrm)));
- } else {
- pair = disAMode ( cb, sorb, eip, dis_buf );
- t2 = LOW24(pair);
- t1 = newTemp(cb);
- uInstr2(cb, LOAD, 1, TempReg, t2, TempReg, t1);
- switch (gregOfRM(modrm)) {
- case 0: /* INC */
- uInstr1(cb, INC, 1, TempReg, t1);
- setFlagsFromUOpcode(cb, INC);
- uInstr2(cb, STORE, 1, TempReg, t1, TempReg, t2);
- break;
- case 1: /* DEC */
- uInstr1(cb, DEC, 1, TempReg, t1);
- setFlagsFromUOpcode(cb, DEC);
- uInstr2(cb, STORE, 1, TempReg, t1, TempReg, t2);
- break;
- default:
- VG_(printf)(
- "unhandled Grp4(M) case %d\n", (UInt)gregOfRM(modrm));
- VG_(core_panic)("Grp4");
- }
- eip += HI8(pair);
- DIP("%sb %s\n", nameGrp4(gregOfRM(modrm)), dis_buf);
- }
- return eip;
-}
-
-
-/* Group 5 extended opcodes. */
-static
-Addr dis_Grp5 ( UCodeBlock* cb,
- UChar sorb,
- Int sz, Addr eip, Bool* isEnd )
-{
- Int t1, t2, t3, t4;
- UInt pair;
- UChar modrm;
- UChar dis_buf[50];
- t1 = t2 = t3 = t4 = INVALID_TEMPREG;
-
- modrm = getUChar(eip);
- if (epartIsReg(modrm)) {
- t1 = newTemp(cb);
- uInstr2(cb, GET, sz, ArchReg, eregOfRM(modrm), TempReg, t1);
- switch (gregOfRM(modrm)) {
- case 0: /* INC */
- uInstr1(cb, INC, sz, TempReg, t1);
- setFlagsFromUOpcode(cb, INC);
- uInstr2(cb, PUT, sz, TempReg, t1, ArchReg, eregOfRM(modrm));
- break;
- case 1: /* DEC */
- uInstr1(cb, DEC, sz, TempReg, t1);
- setFlagsFromUOpcode(cb, DEC);
- uInstr2(cb, PUT, sz, TempReg, t1, ArchReg, eregOfRM(modrm));
- break;
- case 2: /* call Ev */
- t3 = newTemp(cb); t4 = newTemp(cb);
- uInstr2(cb, GET, 4, ArchReg, R_ESP, TempReg, t3);
- uInstr2(cb, SUB, 4, Literal, 0, TempReg, t3);
- uLiteral(cb, 4);
- uInstr2(cb, PUT, 4, TempReg, t3, ArchReg, R_ESP);
- uInstr2(cb, MOV, 4, Literal, 0, TempReg, t4);
- uLiteral(cb, eip+1);
- uInstr2(cb, STORE, 4, TempReg, t4, TempReg, t3);
- jmp_treg(cb, t1);
- LAST_UINSTR(cb).jmpkind = JmpCall;
- *isEnd = True;
- break;
- case 4: /* jmp Ev */
- jmp_treg(cb, t1);
- *isEnd = True;
- break;
- default:
- VG_(printf)(
- "unhandled Grp5(R) case %d\n", (UInt)gregOfRM(modrm));
- VG_(core_panic)("Grp5");
- }
- eip++;
- DIP("%s%c %s\n", nameGrp5(gregOfRM(modrm)),
- nameISize(sz), nameIReg(sz, eregOfRM(modrm)));
- } else {
- pair = disAMode ( cb, sorb, eip, dis_buf );
- t2 = LOW24(pair);
- t1 = newTemp(cb);
- uInstr2(cb, LOAD, sz, TempReg, t2, TempReg, t1);
- switch (gregOfRM(modrm)) {
- case 0: /* INC */
- uInstr1(cb, INC, sz, TempReg, t1);
- setFlagsFromUOpcode(cb, INC);
- uInstr2(cb, STORE, sz, TempReg, t1, TempReg, t2);
- break;
- case 1: /* DEC */
- uInstr1(cb, DEC, sz, TempReg, t1);
- setFlagsFromUOpcode(cb, DEC);
- uInstr2(cb, STORE, sz, TempReg, t1, TempReg, t2);
- break;
- case 2: /* call Ev */
- t3 = newTemp(cb); t4 = newTemp(cb);
- uInstr2(cb, GET, 4, ArchReg, R_ESP, TempReg, t3);
- uInstr2(cb, SUB, 4, Literal, 0, TempReg, t3);
- uLiteral(cb, 4);
- uInstr2(cb, PUT, 4, TempReg, t3, ArchReg, R_ESP);
- uInstr2(cb, MOV, 4, Literal, 0, TempReg, t4);
- uLiteral(cb, eip+HI8(pair));
- uInstr2(cb, STORE, 4, TempReg, t4, TempReg, t3);
- jmp_treg(cb, t1);
- LAST_UINSTR(cb).jmpkind = JmpCall;
- *isEnd = True;
- break;
- case 4: /* JMP Ev */
- jmp_treg(cb, t1);
- *isEnd = True;
- break;
- case 6: /* PUSH Ev */
- t3 = newTemp(cb);
- uInstr2(cb, GET, 4, ArchReg, R_ESP, TempReg, t3);
- uInstr2(cb, SUB, 4, Literal, 0, TempReg, t3);
- uLiteral(cb, sz);
- uInstr2(cb, PUT, 4, TempReg, t3, ArchReg, R_ESP);
- uInstr2(cb, STORE, sz, TempReg, t1, TempReg, t3);
- break;
- default:
- VG_(printf)(
- "unhandled Grp5(M) case %d\n", (UInt)gregOfRM(modrm));
- VG_(core_panic)("Grp5");
- }
- eip += HI8(pair);
- DIP("%s%c %s\n", nameGrp5(gregOfRM(modrm)),
- nameISize(sz), dis_buf);
- }
- return eip;
-}
-
-/*------------------------------------------------------------*/
-/*--- Disassembling string ops (including REP prefixes) ---*/
-/*------------------------------------------------------------*/
-
-/* Code shared by all the string ops */
-static
-void dis_string_op_increment(UCodeBlock* cb, Int sz, Int t_inc)
-{
- uInstr0 (cb, CALLM_S, 0);
- uInstr2 (cb, MOV, 4, Literal, 0, TempReg, t_inc);
- uLiteral(cb, 0);
- uInstr1 (cb, PUSH, 4, TempReg, t_inc);
-
- uInstr1 (cb, CALLM, 0, Lit16, VGOFF_(helper_get_dirflag));
- uFlagsRWU(cb, FlagD, FlagsEmpty, FlagsEmpty);
-
- uInstr1(cb, POP, 4, TempReg, t_inc);
- uInstr0(cb, CALLM_E, 0);
-
- if (sz == 4 || sz == 2) {
- uInstr2(cb, SHL, 4, Literal, 0, TempReg, t_inc);
- uLiteral(cb, sz/2);
- }
-}
-
-static
-void dis_string_op( UCodeBlock* cb, void (*dis_OP)( UCodeBlock*, Int, Int ),
- Int sz, Char* name, UChar sorb )
-{
- Int t_inc = newTemp(cb);
- vg_assert(sorb == 0);
- dis_string_op_increment(cb, sz, t_inc);
- dis_OP( cb, sz, t_inc );
- DIP("%s%c\n", name, nameISize(sz));
-}
-
-
-static
-void dis_MOVS ( UCodeBlock* cb, Int sz, Int t_inc )
-{
- Int tv = newTemp(cb); /* value being copied */
- Int td = newTemp(cb); /* EDI */
- Int ts = newTemp(cb); /* ESI */
-
- uInstr2(cb, GET, 4, ArchReg, R_EDI, TempReg, td);
- uInstr2(cb, GET, 4, ArchReg, R_ESI, TempReg, ts);
-
- uInstr2(cb, LOAD, sz, TempReg, ts, TempReg, tv);
- uInstr2(cb, STORE,sz, TempReg, tv, TempReg, td);
-
- uInstr2(cb, ADD, 4, TempReg, t_inc, TempReg, td);
- uInstr2(cb, ADD, 4, TempReg, t_inc, TempReg, ts);
-
- uInstr2(cb, PUT, 4, TempReg, td, ArchReg, R_EDI);
- uInstr2(cb, PUT, 4, TempReg, ts, ArchReg, R_ESI);
-}
-
-static
-void dis_LODS ( UCodeBlock* cb, Int sz, Int t_inc )
-{
- Int ta = newTemp(cb); /* EAX */
- Int ts = newTemp(cb); /* ESI */
-
- uInstr2(cb, GET, 4, ArchReg, R_ESI, TempReg, ts);
- uInstr2(cb, LOAD, sz, TempReg, ts, TempReg, ta);
- uInstr2(cb, PUT, sz, TempReg, ta, ArchReg, R_EAX);
-
- uInstr2(cb, ADD, 4, TempReg, t_inc, TempReg, ts);
- uInstr2(cb, PUT, 4, TempReg, ts, ArchReg, R_ESI);
-}
-
-static
-void dis_STOS ( UCodeBlock* cb, Int sz, Int t_inc )
-{
- Int ta = newTemp(cb); /* EAX */
- Int td = newTemp(cb); /* EDI */
-
- uInstr2(cb, GET, sz, ArchReg, R_EAX, TempReg, ta);
- uInstr2(cb, GET, 4, ArchReg, R_EDI, TempReg, td);
- uInstr2(cb, STORE, sz, TempReg, ta, TempReg, td);
-
- uInstr2(cb, ADD, 4, TempReg, t_inc, TempReg, td);
- uInstr2(cb, PUT, 4, TempReg, td, ArchReg, R_EDI);
-}
-
-static
-void dis_CMPS ( UCodeBlock* cb, Int sz, Int t_inc )
-{
- Int tdv = newTemp(cb); /* (EDI) */
- Int tsv = newTemp(cb); /* (ESI) */
- Int td = newTemp(cb); /* EDI */
- Int ts = newTemp(cb); /* ESI */
-
- uInstr2(cb, GET, 4, ArchReg, R_EDI, TempReg, td);
- uInstr2(cb, GET, 4, ArchReg, R_ESI, TempReg, ts);
-
- uInstr2(cb, LOAD, sz, TempReg, td, TempReg, tdv);
- uInstr2(cb, LOAD, sz, TempReg, ts, TempReg, tsv);
-
- uInstr2(cb, SUB, sz, TempReg, tdv, TempReg, tsv);
- setFlagsFromUOpcode(cb, SUB);
-
- uInstr2(cb, ADD, 4, TempReg, t_inc, TempReg, td);
- uInstr2(cb, ADD, 4, TempReg, t_inc, TempReg, ts);
-
- uInstr2(cb, PUT, 4, TempReg, td, ArchReg, R_EDI);
- uInstr2(cb, PUT, 4, TempReg, ts, ArchReg, R_ESI);
-}
-
-static
-void dis_SCAS ( UCodeBlock* cb, Int sz, Int t_inc )
-{
- Int ta = newTemp(cb); /* EAX */
- Int td = newTemp(cb); /* EDI */
- Int tdv = newTemp(cb); /* (EDI) */
-
- uInstr2(cb, GET, sz, ArchReg, R_EAX, TempReg, ta);
- uInstr2(cb, GET, 4, ArchReg, R_EDI, TempReg, td);
- uInstr2(cb, LOAD, sz, TempReg, td, TempReg, tdv);
- /* next uinstr kills ta, but that's ok -- don't need it again */
- uInstr2(cb, SUB, sz, TempReg, tdv, TempReg, ta);
- setFlagsFromUOpcode(cb, SUB);
-
- uInstr2(cb, ADD, 4, TempReg, t_inc, TempReg, td);
- uInstr2(cb, PUT, 4, TempReg, td, ArchReg, R_EDI);
-}
-
-
-/* Wrap the appropriate string op inside a REP/REPE/REPNE.
- We assume the insn is the last one in the basic block, and so emit a jump
- to the next insn, rather than just falling through. */
-static
-void dis_REP_op ( UCodeBlock* cb, Int cond,
- void (*dis_OP)(UCodeBlock*, Int, Int),
- Int sz, Addr eip, Addr eip_next, Char* name )
-{
- Int t_inc = newTemp(cb);
- Int tc = newTemp(cb); /* ECX */
-
- dis_string_op_increment(cb, sz, t_inc);
-
- uInstr2 (cb, GET, 4, ArchReg, R_ECX, TempReg, tc);
- uInstr2 (cb, JIFZ, 4, TempReg, tc, Literal, 0);
- uLiteral(cb, eip_next);
- uInstr1 (cb, DEC, 4, TempReg, tc);
- uInstr2 (cb, PUT, 4, TempReg, tc, ArchReg, R_ECX);
-
- dis_OP (cb, sz, t_inc);
-
- if (cond == CondAlways) {
- jmp_lit(cb, eip);
- } else {
- jcc_lit(cb, eip, cond);
- jmp_lit(cb, eip_next);
- }
- DIP("%s%c\n", name, nameISize(sz));
-}
-
-/*------------------------------------------------------------*/
-/*--- Arithmetic, etc. ---*/
-/*------------------------------------------------------------*/
-
-/* (I)MUL E, G. Supplied eip points to the modR/M byte. */
-static
-Addr dis_mul_E_G ( UCodeBlock* cb,
- UChar sorb,
- Int size,
- Addr eip0,
- Bool signed_multiply )
-{
- Int ta, tg, te;
- UChar dis_buf[50];
- UChar rm = getUChar(eip0);
- ta = INVALID_TEMPREG;
- te = newTemp(cb);
- tg = newTemp(cb);
-
- if (epartIsReg(rm)) {
- vg_assert(signed_multiply);
- uInstr2(cb, GET, size, ArchReg, gregOfRM(rm), TempReg, tg);
- uInstr2(cb, MUL, size, ArchReg, eregOfRM(rm), TempReg, tg);
- setFlagsFromUOpcode(cb, MUL);
- uInstr2(cb, PUT, size, TempReg, tg, ArchReg, gregOfRM(rm));
- DIP("%smul%c %s, %s\n", signed_multiply ? "i" : "",
- nameISize(size),
- nameIReg(size,eregOfRM(rm)),
- nameIReg(size,gregOfRM(rm)));
- return 1+eip0;
- } else {
- UInt pair;
- vg_assert(signed_multiply);
- pair = disAMode ( cb, sorb, eip0, dis_buf );
- ta = LOW24(pair);
- uInstr2(cb, LOAD, size, TempReg, ta, TempReg, te);
- uInstr2(cb, GET, size, ArchReg, gregOfRM(rm), TempReg, tg);
- uInstr2(cb, MUL, size, TempReg, te, TempReg, tg);
- setFlagsFromUOpcode(cb, MUL);
- uInstr2(cb, PUT, size, TempReg, tg, ArchReg, gregOfRM(rm));
-
- DIP("%smul%c %s, %s\n", signed_multiply ? "i" : "",
- nameISize(size),
- dis_buf, nameIReg(size,gregOfRM(rm)));
- return HI8(pair)+eip0;
- }
-}
-
-
-/* IMUL I * E -> G. Supplied eip points to the modR/M byte. */
-static
-Addr dis_imul_I_E_G ( UCodeBlock* cb,
- UChar sorb,
- Int size,
- Addr eip,
- Int litsize )
-{
- Int ta, te, tl, d32;
- Char dis_buf[50];
- UChar rm = getUChar(eip);
- ta = INVALID_TEMPREG;
- te = newTemp(cb);
- tl = newTemp(cb);
-
- if (epartIsReg(rm)) {
- uInstr2(cb, GET, size, ArchReg, eregOfRM(rm), TempReg, te);
- eip++;
- } else {
- UInt pair = disAMode ( cb, sorb, eip, dis_buf );
- ta = LOW24(pair);
- uInstr2(cb, LOAD, size, TempReg, ta, TempReg, te);
- eip += HI8(pair);
- }
-
- d32 = getSDisp(litsize,eip);
- eip += litsize;
-
- uInstr2(cb, MOV, size, Literal, 0, TempReg, tl);
- uLiteral(cb, d32);
- uInstr2(cb, MUL, size, TempReg, tl, TempReg, te);
- setFlagsFromUOpcode(cb, MUL);
- uInstr2(cb, PUT, size, TempReg, te, ArchReg, gregOfRM(rm));
-
- DIP("imul %d, %s, %s\n", d32,
- ( epartIsReg(rm) ? nameIReg(size,eregOfRM(rm)) : dis_buf ),
- nameIReg(size,gregOfRM(rm)) );
-
- return eip;
-}
-
-
-/* Handle FPU insns which read/write memory. On entry, eip points to
- the second byte of the insn (the one following D8 .. DF). */
-static
-Addr dis_fpu_mem ( UCodeBlock* cb,
- UChar sorb,
- Int size, Bool is_write,
- Addr eip, UChar first_byte )
-{
- Int ta;
- UInt pair;
- UChar dis_buf[50];
- UChar second_byte = getUChar(eip);
- vg_assert(second_byte < 0xC0);
- second_byte &= 0x38;
- pair = disAMode ( cb, sorb, eip, dis_buf );
- ta = LOW24(pair);
- eip += HI8(pair);
- uInstr2(cb, is_write ? FPU_W : FPU_R, size,
- Lit16,
- (((UShort)first_byte) << 8) | ((UShort)second_byte),
- TempReg, ta);
- if (is_write) {
- DIP("fpu_w_%d 0x%x:0x%x, %s\n",
- size, (UInt)first_byte, (UInt)second_byte, dis_buf );
- } else {
- DIP("fpu_r_%d %s, 0x%x:0x%x\n",
- size, dis_buf, (UInt)first_byte, (UInt)second_byte );
- }
- return eip;
-}
-
-
-/* Handle FPU insns which don't reference memory. On entry, eip points to
- the second byte of the insn (the one following D8 .. DF). */
-static
-Addr dis_fpu_no_mem ( UCodeBlock* cb, Addr eip, UChar first_byte )
-{
- Bool sets_ZCP = False;
- Bool uses_ZCP = False;
- UChar second_byte = getUChar(eip); eip++;
- vg_assert(second_byte >= 0xC0);
-
- /* Does the insn write any integer condition codes (%EIP) ? */
-
- if (first_byte == 0xDB && second_byte >= 0xF0 && second_byte <= 0xF7) {
- /* FCOMI */
- sets_ZCP = True;
- } else
- if (first_byte == 0xDF && second_byte >= 0xF0 && second_byte <= 0xF7) {
- /* FCOMIP */
- sets_ZCP = True;
- } else
- if (first_byte == 0xDB && second_byte >= 0xE8 && second_byte <= 0xEF) {
- /* FUCOMI */
- sets_ZCP = True;
- } else
- if (first_byte == 0xDF && second_byte >= 0xE8 && second_byte <= 0xEF) {
- /* FUCOMIP */
- sets_ZCP = True;
- }
-
- /* Dually, does the insn read any integer condition codes (%EIP) ? */
-
- if (first_byte == 0xDA && second_byte >= 0xC0 && second_byte <= 0xDF) {
- /* FCMOVB %st(n), %st(0)
- FCMOVE %st(n), %st(0)
- FCMOVBE %st(n), %st(0)
- FCMOVU %st(n), %st(0)
- */
- uses_ZCP = True;
- } else
- if (first_byte == 0xDB && second_byte >= 0xC0 && second_byte <= 0xDF) {
- /* FCMOVNB %st(n), %st(0)
- FCMOVNE %st(n), %st(0)
- FCMOVNBE %st(n), %st(0)
- FCMOVNU %st(n), %st(0)
- */
- uses_ZCP = True;
- }
-
- uInstr1(cb, FPU, 0,
- Lit16,
- (((UShort)first_byte) << 8) | ((UShort)second_byte)
- );
- if (uses_ZCP) {
- /* VG_(printf)("!!! --- FPU insn which reads %EFLAGS\n"); */
- uFlagsRWU(cb, FlagsZCP, FlagsEmpty, FlagsEmpty);
- vg_assert(!sets_ZCP);
- }
- if (sets_ZCP) {
- /* VG_(printf)("!!! --- FPU insn which writes %EFLAGS\n"); */
- uFlagsRWU(cb, FlagsEmpty, FlagsZCP, FlagsEmpty);
- vg_assert(!uses_ZCP);
- }
-
- DIP("fpu 0x%x:0x%x%s%s\n", (UInt)first_byte, (UInt)second_byte,
- uses_ZCP ? " -rZCP" : "",
- sets_ZCP ? " -wZCP" : "" );
- return eip;
-}
-
-
-/* Top-level handler for all FPU insns. On entry, eip points to the
- second byte of the insn. */
-static
-Addr dis_fpu ( UCodeBlock* cb,
- UChar sorb,
- UChar first_byte, Addr eip )
-{
- const Bool rd = False;
- const Bool wr = True;
- UChar second_byte = getUChar(eip);
-
- /* Handle FSTSW %ax specially. */
- if (first_byte == 0xDF && second_byte == 0xE0) {
- Int t1 = newTemp(cb);
- uInstr0(cb, CALLM_S, 0);
- uInstr2(cb, MOV, 4, Literal, 0, TempReg, t1);
- uLiteral(cb, 0);
- uInstr1(cb, PUSH, 4, TempReg, t1);
- uInstr1(cb, CALLM, 0, Lit16, VGOFF_(helper_fstsw_AX) );
- uFlagsRWU(cb, FlagsEmpty, FlagsEmpty, FlagsEmpty);
- uInstr1(cb, POP, 2, TempReg, t1);
- uInstr2(cb, PUT, 2, TempReg, t1, ArchReg, R_EAX);
- uInstr0(cb, CALLM_E, 0);
- DIP("fstsw %%ax\n");
- eip++;
- return eip;
- }
-
- /* Handle all non-memory FPU ops simply. */
- if (second_byte >= 0xC0)
- return dis_fpu_no_mem ( cb, eip, first_byte );
-
- /* The insn references memory; need to determine
- whether it reads or writes, and at what size. */
- switch (first_byte) {
-
- case 0xD8:
- switch ((second_byte >> 3) & 7) {
- case 0: /* FADDs */
- case 1: /* FMULs */
- case 2: /* FCOMs */
- case 3: /* FCOMPs */
- case 4: /* FSUBs */
- case 5: /* FSUBRs */
- case 6: /* FDIVs */
- case 7: /* FDIVRs */
- return dis_fpu_mem(cb, sorb, 4, rd, eip, first_byte);
- default:
- goto unhandled;
- }
- break;
-
- case 0xD9:
- switch ((second_byte >> 3) & 7) {
- case 0: /* FLDs */
- return dis_fpu_mem(cb, sorb, 4, rd, eip, first_byte);
- case 2: /* FSTs */
- case 3: /* FSTPs */
- return dis_fpu_mem(cb, sorb, 4, wr, eip, first_byte);
- case 4: /* FLDENV */
- return dis_fpu_mem(cb, sorb, 28, rd, eip, first_byte);
- case 5: /* FLDCW */
- return dis_fpu_mem(cb, sorb, 2, rd, eip, first_byte);
- case 6: /* FNSTENV */
- return dis_fpu_mem(cb, sorb, 28, wr, eip, first_byte);
- case 7: /* FSTCW */
- /* HACK! FSTCW actually writes 2 bytes, not 4. glibc
- gets lots of moaning in __floor() if we do the right
- thing here. */
- /* Later ... hack disabled .. we do do the Right Thing. */
- return dis_fpu_mem(cb, sorb, /*4*/ 2, wr, eip, first_byte);
- default:
- goto unhandled;
- }
- break;
-
- case 0xDA:
- switch ((second_byte >> 3) & 7) {
- case 0: /* FIADD dword-integer */
- case 1: /* FIMUL dword-integer */
- case 2: /* FICOM dword-integer */
- case 3: /* FICOMP dword-integer */
- case 4: /* FISUB dword-integer */
- case 5: /* FISUBR dword-integer */
- case 6: /* FIDIV dword-integer */
- case 7: /* FIDIVR dword-integer */
- return dis_fpu_mem(cb, sorb, 4, rd, eip, first_byte);
- default:
- goto unhandled;
- }
- break;
-
- case 0xDB:
- switch ((second_byte >> 3) & 7) {
- case 0: /* FILD dword-integer */
- return dis_fpu_mem(cb, sorb, 4, rd, eip, first_byte);
- case 2: /* FIST dword-integer */
- return dis_fpu_mem(cb, sorb, 4, wr, eip, first_byte);
- case 3: /* FISTPl */
- return dis_fpu_mem(cb, sorb, 4, wr, eip, first_byte);
- case 5: /* FLD extended-real */
- return dis_fpu_mem(cb, sorb, 10, rd, eip, first_byte);
- case 7: /* FSTP extended-real */
- return dis_fpu_mem(cb, sorb, 10, wr, eip, first_byte);
- default:
- goto unhandled;
- }
- break;
-
- case 0xDC:
- switch ((second_byte >> 3) & 7) {
- case 0: /* FADD double-real */
- case 1: /* FMUL double-real */
- case 2: /* FCOM double-real */
- case 3: /* FCOMP double-real */
- case 4: /* FSUB double-real */
- case 5: /* FSUBR double-real */
- case 6: /* FDIV double-real */
- case 7: /* FDIVR double-real */
- return dis_fpu_mem(cb, sorb, 8, rd, eip, first_byte);
- default:
- goto unhandled;
- }
- break;
-
- case 0xDD:
- switch ((second_byte >> 3) & 7) {
- case 0: /* FLD double-real */
- return dis_fpu_mem(cb, sorb, 8, rd, eip, first_byte);
- case 2: /* FST double-real */
- case 3: /* FSTP double-real */
- return dis_fpu_mem(cb, sorb, 8, wr, eip, first_byte);
- case 4: /* FRSTOR */
- return dis_fpu_mem(cb, sorb, 108, rd, eip, first_byte);
- case 6: /* FSAVE */
- return dis_fpu_mem(cb, sorb, 108, wr, eip, first_byte);
- case 7: /* FSTSW */
- return dis_fpu_mem(cb, sorb, 2, wr, eip, first_byte);
- default:
- goto unhandled;
- }
- break;
-
- case 0xDE:
- switch ((second_byte >> 3) & 7) {
- case 0: /* FIADD word-integer */
- case 1: /* FIMUL word-integer */
- case 2: /* FICOM word-integer */
- case 3: /* FICOMP word-integer */
- case 4: /* FISUB word-integer */
- case 5: /* FISUBR word-integer */
- case 6: /* FIDIV word-integer */
- case 7: /* FIDIVR word-integer */
- return dis_fpu_mem(cb, sorb, 2, rd, eip, first_byte);
- default:
- goto unhandled;
- }
- break;
-
- case 0xDF:
- switch ((second_byte >> 3) & 7) {
- case 0: /* FILD word-integer */
- return dis_fpu_mem(cb, sorb, 2, rd, eip, first_byte);
- case 2: /* FIST word-integer */
- return dis_fpu_mem(cb, sorb, 2, wr, eip, first_byte);
- case 3: /* FISTP word-integer */
- return dis_fpu_mem(cb, sorb, 2, wr, eip, first_byte);
- case 4: /* FBLD extended-real */
- return dis_fpu_mem(cb, sorb, 10, rd, eip, first_byte);
- case 5: /* FILD qword-integer */
- return dis_fpu_mem(cb, sorb, 8, rd, eip, first_byte);
- case 6: /* FBSTP extended-real */
- return dis_fpu_mem(cb, sorb, 10, wr, eip, first_byte);
- case 7: /* FISTP qword-integer */
- return dis_fpu_mem(cb, sorb, 8, wr, eip, first_byte);
- default:
- goto unhandled;
- }
- break;
-
- default: goto unhandled;
- }
-
- unhandled:
- VG_(printf)("dis_fpu: unhandled memory case 0x%2x:0x%2x(%d)\n",
- (UInt)first_byte, (UInt)second_byte,
- (UInt)((second_byte >> 3) & 7) );
- VG_(core_panic)("dis_fpu: unhandled opcodes");
-}
-
-
-/* Double length left shifts. Apparently only required in v-size (no
- b- variant). */
-static
-Addr dis_SHLRD_Gv_Ev ( UCodeBlock* cb,
- UChar sorb,
- Addr eip, UChar modrm,
- Int sz,
- Tag amt_tag, UInt amt_val,
- Bool left_shift )
-{
- /* amt_tag and amt_val denote either ArchReg(%CL) or a Literal.
- And eip on entry points at the modrm byte. */
- Int t, t1, t2, ta, helper;
- UInt pair;
- UChar dis_buf[50];
-
- vg_assert(sz == 2 || sz == 4);
-
- helper = left_shift
- ? (sz==4 ? VGOFF_(helper_shldl)
- : VGOFF_(helper_shldw))
- : (sz==4 ? VGOFF_(helper_shrdl)
- : VGOFF_(helper_shrdw));
-
- /* Get the amount to be shifted by onto the stack. */
- t = newTemp(cb);
- t1 = newTemp(cb);
- t2 = newTemp(cb);
- if (amt_tag == ArchReg) {
- vg_assert(amt_val == R_CL);
- uInstr2(cb, GET, 1, ArchReg, amt_val, TempReg, t);
- } else {
- uInstr2(cb, MOV, 1, Literal, 0, TempReg, t);
- uLiteral(cb, amt_val);
- }
-
- uInstr0(cb, CALLM_S, 0);
- uInstr1(cb, PUSH, 1, TempReg, t);
-
- /* The E-part is the destination; this is shifted. The G-part
- supplies bits to be shifted into the E-part, but is not
- changed. */
-
- uInstr2(cb, GET, sz, ArchReg, gregOfRM(modrm), TempReg, t1);
- uInstr1(cb, PUSH, sz, TempReg, t1);
-
- if (epartIsReg(modrm)) {
- eip++;
- uInstr2(cb, GET, sz, ArchReg, eregOfRM(modrm), TempReg, t2);
- uInstr1(cb, PUSH, sz, TempReg, t2);
- uInstr1(cb, CALLM, 0, Lit16, helper);
- uFlagsRWU(cb, FlagsEmpty, FlagsOSZACP, FlagsEmpty);
- uInstr1(cb, POP, sz, TempReg, t);
- uInstr2(cb, PUT, sz, TempReg, t, ArchReg, eregOfRM(modrm));
- DIP("sh%cd%c %%cl, %s, %s\n",
- ( left_shift ? 'l' : 'r' ), nameISize(sz),
- nameIReg(sz, gregOfRM(modrm)), nameIReg(sz, eregOfRM(modrm)));
- } else {
- pair = disAMode ( cb, sorb, eip, dis_buf );
- ta = LOW24(pair);
- eip += HI8(pair);
- uInstr2(cb, LOAD, sz, TempReg, ta, TempReg, t2);
- uInstr1(cb, PUSH, sz, TempReg, t2);
- uInstr1(cb, CALLM, 0, Lit16, helper);
- uFlagsRWU(cb, FlagsEmpty, FlagsOSZACP, FlagsEmpty);
- uInstr1(cb, POP, sz, TempReg, t);
- uInstr2(cb, STORE, sz, TempReg, t, TempReg, ta);
- DIP("sh%cd%c %%cl, %s, %s\n", ( left_shift ? 'l' : 'r' ),
- nameISize(sz), nameIReg(sz, gregOfRM(modrm)), dis_buf);
- }
-
- if (amt_tag == Literal) eip++;
- uInstr1(cb, CLEAR, 0, Lit16, 8);
-
- uInstr0(cb, CALLM_E, 0);
- return eip;
-}
-
-
-/* Handle BT/BTS/BTR/BTC Gv, Ev. Apparently b-size is not
- required. */
-
-typedef enum { BtOpNone, BtOpSet, BtOpReset, BtOpComp } BtOp;
-
-static Char* nameBtOp ( BtOp op )
-{
- switch (op) {
- case BtOpNone: return "";
- case BtOpSet: return "s";
- case BtOpReset: return "r";
- case BtOpComp: return "c";
- default: VG_(core_panic)("nameBtOp");
- }
-}
-
-
-static
-Addr dis_bt_G_E ( UCodeBlock* cb,
- UChar sorb,
- Int sz, Addr eip, BtOp op )
-{
- UInt pair;
- Char dis_buf[50];
- UChar modrm;
-
- Int t_addr, t_bitno, t_mask, t_fetched, t_esp, temp, lit;
-
- vg_assert(sz == 2 || sz == 4);
-
- t_addr = t_bitno = t_mask
- = t_fetched = t_esp = temp = INVALID_TEMPREG;
-
- t_fetched = newTemp(cb);
- t_bitno = newTemp(cb);
- temp = newTemp(cb);
- lit = newTemp(cb);
-
- modrm = getUChar(eip);
-
- uInstr2(cb, GET, sz, ArchReg, gregOfRM(modrm), TempReg, t_bitno);
-
- if (sz == 2) {
- uInstr1(cb, WIDEN, 4, TempReg, t_bitno);
- uWiden(cb, 2, False);
- }
-
- if (epartIsReg(modrm)) {
- eip++;
- /* Get it onto the client's stack. */
- t_esp = newTemp(cb);
- t_addr = newTemp(cb);
- uInstr2(cb, GET, 4, ArchReg, R_ESP, TempReg, t_esp);
- uInstr2(cb, SUB, 4, Literal, 0, TempReg, t_esp);
- uLiteral(cb, sz);
- uInstr2(cb, PUT, 4, TempReg, t_esp, ArchReg, R_ESP);
- uInstr2(cb, GET, sz, ArchReg, eregOfRM(modrm), TempReg, temp);
- uInstr2(cb, STORE, sz, TempReg, temp, TempReg, t_esp);
- /* Make t_addr point at it. */
- uInstr2(cb, MOV, 4, TempReg, t_esp, TempReg, t_addr);
- /* Mask out upper bits of the shift amount, since we're doing a
- reg. */
- uInstr2(cb, MOV, 4, Literal, 0, TempReg, lit);
- uLiteral(cb, sz == 4 ? 31 : 15);
- uInstr2(cb, AND, 4, TempReg, lit, TempReg, t_bitno);
- } else {
- pair = disAMode ( cb, sorb, eip, dis_buf );
- t_addr = LOW24(pair);
- eip += HI8(pair);
- }
-
- /* At this point: t_addr points to the address being operated on. If
- it was a reg, we will have pushed it onto the client's stack.
- t_bitno is the bit number, suitable masked in the case of a reg. */
-
- /* Now the main sequence. */
-
- uInstr2(cb, MOV, 4, TempReg, t_bitno, TempReg, temp);
- uInstr2(cb, SAR, 4, Literal, 0, TempReg, temp);
- uLiteral(cb, 3);
- uInstr2(cb, ADD, 4, TempReg, temp, TempReg, t_addr);
- /* t_addr now holds effective address */
-
- uInstr2(cb, MOV, 4, Literal, 0, TempReg, lit);
- uLiteral(cb, 7);
- uInstr2(cb, AND, 4, TempReg, lit, TempReg, t_bitno);
- /* t_bitno contains offset of bit within byte */
-
- if (op != BtOpNone) {
- t_mask = newTemp(cb);
- uInstr2(cb, MOV, 4, Literal, 0, TempReg, t_mask);
- uLiteral(cb, 1);
- uInstr2(cb, SHL, 4, TempReg, t_bitno, TempReg, t_mask);
- }
- /* t_mask is now a suitable byte mask */
-
- uInstr2(cb, LOAD, 1, TempReg, t_addr, TempReg, t_fetched);
- if (op != BtOpNone) {
- uInstr2(cb, MOV, 4, TempReg, t_fetched, TempReg, temp);
- switch (op) {
- case BtOpSet:
- uInstr2(cb, OR, 4, TempReg, t_mask, TempReg, temp);
- break;
- case BtOpComp:
- uInstr2(cb, XOR, 4, TempReg, t_mask, TempReg, temp);
- break;
- case BtOpReset:
- uInstr1(cb, NOT, 4, TempReg, t_mask);
- uInstr2(cb, AND, 4, TempReg, t_mask, TempReg, temp);
- break;
- default:
- VG_(core_panic)("dis_bt_G_E");
- }
- uInstr2(cb, STORE, 1, TempReg, temp, TempReg, t_addr);
- }
-
- /* Side effect done; now get selected bit into Carry flag */
-
- uInstr2(cb, SHR, 4, TempReg, t_bitno, TempReg, t_fetched);
- /* at bit 0 of fetched */
-
- uInstr2(cb, MOV, 4, Literal, 0, TempReg, lit);
- uLiteral(cb, 1);
- uInstr2(cb, AND, 4, TempReg, lit, TempReg, t_fetched);
- /* t_fetched is now 1 or 0 */
-
- /* NEG is a handy way to convert zero/nonzero into the carry
- flag. */
- uInstr1(cb, NEG, 4, TempReg, t_fetched);
- setFlagsFromUOpcode(cb, NEG);
- /* t_fetched is now in carry flag */
-
- /* Move reg operand from stack back to reg */
- if (epartIsReg(modrm)) {
- /* t_esp still points at it. */
- uInstr2(cb, LOAD, sz, TempReg, t_esp, TempReg, temp);
- uInstr2(cb, PUT, sz, TempReg, temp, ArchReg, eregOfRM(modrm));
- uInstr2(cb, ADD, 4, Literal, 0, TempReg, t_esp);
- uLiteral(cb, sz);
- uInstr2(cb, PUT, 4, TempReg, t_esp, ArchReg, R_ESP);
- }
-
- DIP("bt%s%c %s, %s\n",
- nameBtOp(op), nameISize(sz), nameIReg(sz, gregOfRM(modrm)),
- ( epartIsReg(modrm) ? nameIReg(sz, eregOfRM(modrm)) : dis_buf ) );
-
- return eip;
-}
-
-
-
-/* Handle BSF/BSR. Only v-size seems necessary. */
-static
-Addr dis_bs_E_G ( UCodeBlock* cb,
- UChar sorb,
- Int sz, Addr eip, Bool fwds )
-{
- Int t, t1, ta, helper;
- UInt pair;
- Char dis_buf[50];
- UChar modrm;
- Bool isReg;
-
- vg_assert(sz == 2 || sz == 4);
-
- if (fwds)
- helper = sz == 2 ? VGOFF_(helper_bsfw) : VGOFF_(helper_bsfl);
- else
- helper = sz == 2 ? VGOFF_(helper_bsrw) : VGOFF_(helper_bsrl);
-
- modrm = getUChar(eip);
- t1 = newTemp(cb);
- t = newTemp(cb);
-
- uInstr0(cb, CALLM_S, 0);
- uInstr2(cb, GET, sz, ArchReg, gregOfRM(modrm), TempReg, t1);
- uInstr1(cb, PUSH, sz, TempReg, t1);
-
- isReg = epartIsReg(modrm);
- if (isReg) {
- eip++;
- uInstr2(cb, GET, sz, ArchReg, eregOfRM(modrm), TempReg, t);
- } else {
- pair = disAMode ( cb, sorb, eip, dis_buf );
- ta = LOW24(pair);
- eip += HI8(pair);
- uInstr2(cb, LOAD, sz, TempReg, ta, TempReg, t);
- }
- DIP("bs%c%c %s, %s\n",
- fwds ? 'f' : 'r', nameISize(sz),
- ( isReg ? nameIReg(sz, eregOfRM(modrm)) : dis_buf ),
- nameIReg(sz, gregOfRM(modrm)));
-
- uInstr1(cb, PUSH, sz, TempReg, t);
- uInstr1(cb, CALLM, 0, Lit16, helper);
- uFlagsRWU(cb, FlagsEmpty, FlagZ, FlagsOSACP);
- uInstr1(cb, POP, sz, TempReg, t);
- uInstr1(cb, POP, sz, TempReg, t);
- uInstr2(cb, PUT, sz, TempReg, t, ArchReg, gregOfRM(modrm));
- uInstr0(cb, CALLM_E, 0);
-
- return eip;
-}
-
-
-static
-void codegen_xchg_eAX_Reg ( UCodeBlock* cb, Int sz, Int reg )
-{
- Int t1, t2;
- vg_assert(sz == 2 || sz == 4);
- t1 = newTemp(cb);
- t2 = newTemp(cb);
- uInstr2(cb, GET, sz, ArchReg, R_EAX, TempReg, t1);
- uInstr2(cb, GET, sz, ArchReg, reg, TempReg, t2);
- uInstr2(cb, PUT, sz, TempReg, t2, ArchReg, R_EAX);
- uInstr2(cb, PUT, sz, TempReg, t1, ArchReg, reg);
- DIP("xchg%c %s, %s\n",
- nameISize(sz), nameIReg(sz, R_EAX), nameIReg(sz, reg));
-}
-
-
-static
-void codegen_SAHF ( UCodeBlock* cb )
-{
- Int t = newTemp(cb);
- Int t2 = newTemp(cb);
- uInstr2(cb, GET, 4, ArchReg, R_EAX, TempReg, t);
-
- /* Mask out parts of t not corresponding to %AH. This stops the
- instrumenter complaining if they are undefined. Otherwise, the
- instrumenter would check all 32 bits of t at the PUSH, which
- could be the cause of incorrect warnings. Discovered by Daniel
- Veillard <veillard@redhat.com>.
- */
- uInstr2(cb, MOV, 4, Literal, 0, TempReg, t2);
- uLiteral(cb, 0x0000FF00);
- uInstr2(cb, AND, 4, TempReg, t2, TempReg, t);
- /* We deliberately don't set the condition codes here, since this
- AND is purely internal to Valgrind and nothing to do with the
- client's state. */
-
- uInstr0(cb, CALLM_S, 0);
- uInstr1(cb, PUSH, 4, TempReg, t);
- uInstr1(cb, CALLM, 0, Lit16, VGOFF_(helper_SAHF));
- uFlagsRWU(cb, FlagsEmpty, FlagsSZACP, FlagsEmpty);
- uInstr1(cb, CLEAR, 0, Lit16, 4);
- uInstr0(cb, CALLM_E, 0);
-}
-
-static
-void codegen_LAHF ( UCodeBlock* cb )
-{
- Int t = newTemp(cb);
-
- /* Pushed arg is ignored, it just provides somewhere to put the
- return value. */
- uInstr2(cb, GET, 4, ArchReg, R_EAX, TempReg, t);
- uInstr0(cb, CALLM_S, 0);
- uInstr1(cb, PUSH, 4, TempReg, t);
- uInstr1(cb, CALLM, 0, Lit16, VGOFF_(helper_LAHF));
- uFlagsRWU(cb, FlagsSZACP, FlagsEmpty, FlagsEmpty);
- uInstr1(cb, POP, 4, TempReg, t);
- uInstr0(cb, CALLM_E, 0);
-
- /* At this point, the %ah sub-register in %eax has been updated,
- the rest is the same, so do a PUT of the whole thing. */
- uInstr2(cb, PUT, 4, TempReg, t, ArchReg, R_EAX);
-}
-
-
-static
-Addr dis_cmpxchg_G_E ( UCodeBlock* cb,
- UChar sorb,
- Int size,
- Addr eip0 )
-{
- Int ta, junk, dest, src, acc;
- UChar dis_buf[50];
- UChar rm;
-
- rm = getUChar(eip0);
- acc = newTemp(cb);
- src = newTemp(cb);
- dest = newTemp(cb);
- junk = newTemp(cb);
- /* Only needed to get gcc's dataflow analyser off my back. */
- ta = INVALID_TEMPREG;
-
- if (epartIsReg(rm)) {
- uInstr2(cb, GET, size, ArchReg, eregOfRM(rm), TempReg, dest);
- eip0++;
- DIP("cmpxchg%c %s,%s\n", nameISize(size),
- nameIReg(size,gregOfRM(rm)),
- nameIReg(size,eregOfRM(rm)) );
- } else {
- UInt pair = disAMode ( cb, sorb, eip0, dis_buf );
- ta = LOW24(pair);
- uInstr2(cb, LOAD, size, TempReg, ta, TempReg, dest);
- eip0 += HI8(pair);
- DIP("cmpxchg%c %s,%s\n", nameISize(size),
- nameIReg(size,gregOfRM(rm)), dis_buf);
- }
-
- uInstr2(cb, GET, size, ArchReg, gregOfRM(rm), TempReg, src);
- uInstr2(cb, GET, size, ArchReg, R_EAX, TempReg, acc);
- uInstr2(cb, MOV, 4, TempReg, acc, TempReg, junk);
- uInstr2(cb, SUB, size, TempReg, dest, TempReg, junk);
- setFlagsFromUOpcode(cb, SUB);
-
- uInstr2(cb, CMOV, 4, TempReg, src, TempReg, dest);
- uCond(cb, CondZ);
- uFlagsRWU(cb, FlagsOSZACP, FlagsEmpty, FlagsEmpty);
- uInstr2(cb, CMOV, 4, TempReg, dest, TempReg, acc);
- uCond(cb, CondNZ);
- uFlagsRWU(cb, FlagsOSZACP, FlagsEmpty, FlagsEmpty);
-
- uInstr2(cb, PUT, size, TempReg, acc, ArchReg, R_EAX);
- if (epartIsReg(rm)) {
- uInstr2(cb, PUT, size, TempReg, dest, ArchReg, eregOfRM(rm));
- } else {
- uInstr2(cb, STORE, size, TempReg, dest, TempReg, ta);
- }
-
- return eip0;
-}
-
-
-static
-Addr dis_cmpxchg8b ( UCodeBlock* cb,
- UChar sorb,
- Addr eip0 )
-{
- Int tal, tah, junkl, junkh, destl, desth, srcl, srch, accl, acch;
- UChar dis_buf[50];
- UChar rm;
- UInt pair;
-
- rm = getUChar(eip0);
- accl = newTemp(cb);
- acch = newTemp(cb);
- srcl = newTemp(cb);
- srch = newTemp(cb);
- destl = newTemp(cb);
- desth = newTemp(cb);
- junkl = newTemp(cb);
- junkh = newTemp(cb);
-
- vg_assert(!epartIsReg(rm));
-
- pair = disAMode ( cb, sorb, eip0, dis_buf );
- tal = LOW24(pair);
- tah = newTemp(cb);
- uInstr2(cb, MOV, 4, TempReg, tal, TempReg, tah);
- uInstr2(cb, ADD, 4, Literal, 0, TempReg, tah);
- uLiteral(cb, 4);
- eip0 += HI8(pair);
- DIP("cmpxchg8b %s\n", dis_buf);
-
- uInstr0(cb, CALLM_S, 0);
-
- uInstr2(cb, LOAD, 4, TempReg, tah, TempReg, desth);
- uInstr1(cb, PUSH, 4, TempReg, desth);
- uInstr2(cb, LOAD, 4, TempReg, tal, TempReg, destl);
- uInstr1(cb, PUSH, 4, TempReg, destl);
- uInstr2(cb, GET, 4, ArchReg, R_ECX, TempReg, srch);
- uInstr1(cb, PUSH, 4, TempReg, srch);
- uInstr2(cb, GET, 4, ArchReg, R_EBX, TempReg, srcl);
- uInstr1(cb, PUSH, 4, TempReg, srcl);
- uInstr2(cb, GET, 4, ArchReg, R_EDX, TempReg, acch);
- uInstr1(cb, PUSH, 4, TempReg, acch);
- uInstr2(cb, GET, 4, ArchReg, R_EAX, TempReg, accl);
- uInstr1(cb, PUSH, 4, TempReg, accl);
-
- uInstr1(cb, CALLM, 0, Lit16, VGOFF_(helper_cmpxchg8b));
- uFlagsRWU(cb, FlagsEmpty, FlagZ, FlagsEmpty);
-
- uInstr1(cb, POP, 4, TempReg, accl);
- uInstr2(cb, PUT, 4, TempReg, accl, ArchReg, R_EAX);
- uInstr1(cb, POP, 4, TempReg, acch);
- uInstr2(cb, PUT, 4, TempReg, acch, ArchReg, R_EDX);
- uInstr1(cb, POP, 4, TempReg, srcl);
- uInstr2(cb, PUT, 4, TempReg, srcl, ArchReg, R_EBX);
- uInstr1(cb, POP, 4, TempReg, srch);
- uInstr2(cb, PUT, 4, TempReg, srch, ArchReg, R_ECX);
- uInstr1(cb, POP, 4, TempReg, destl);
- uInstr2(cb, STORE, 4, TempReg, destl, TempReg, tal);
- uInstr1(cb, POP, 4, TempReg, desth);
- uInstr2(cb, STORE, 4, TempReg, desth, TempReg, tah);
-
- uInstr0(cb, CALLM_E, 0);
-
- return eip0;
-}
-
-
-/* Handle conditional move instructions of the form
- cmovcc E(reg-or-mem), G(reg)
-
- E(src) is reg-or-mem
- G(dst) is reg.
-
- If E is reg, --> GET %E, tmps
- GET %G, tmpd
- CMOVcc tmps, tmpd
- PUT tmpd, %G
-
- If E is mem --> (getAddr E) -> tmpa
- LD (tmpa), tmps
- GET %G, tmpd
- CMOVcc tmps, tmpd
- PUT tmpd, %G
-*/
-static
-Addr dis_cmov_E_G ( UCodeBlock* cb,
- UChar sorb,
- Int size,
- Condcode cond,
- Addr eip0 )
-{
- UChar rm = getUChar(eip0);
- UChar dis_buf[50];
-
- Int tmps = newTemp(cb);
- Int tmpd = newTemp(cb);
-
- if (epartIsReg(rm)) {
- uInstr2(cb, GET, size, ArchReg, eregOfRM(rm), TempReg, tmps);
- uInstr2(cb, GET, size, ArchReg, gregOfRM(rm), TempReg, tmpd);
- uInstr2(cb, CMOV, 4, TempReg, tmps, TempReg, tmpd);
- uCond(cb, cond);
- uFlagsRWU(cb, FlagsOSZACP, FlagsEmpty, FlagsEmpty);
- uInstr2(cb, PUT, size, TempReg, tmpd, ArchReg, gregOfRM(rm));
- DIP("cmov%c%s %s,%s\n", nameISize(size),
- VG_(name_UCondcode)(cond),
- nameIReg(size,eregOfRM(rm)),
- nameIReg(size,gregOfRM(rm)));
- return 1+eip0;
- }
-
- /* E refers to memory */
- {
- UInt pair = disAMode ( cb, sorb, eip0, dis_buf );
- Int tmpa = LOW24(pair);
- uInstr2(cb, LOAD, size, TempReg, tmpa, TempReg, tmps);
- uInstr2(cb, GET, size, ArchReg, gregOfRM(rm), TempReg, tmpd);
- uInstr2(cb, CMOV, 4, TempReg, tmps, TempReg, tmpd);
- uCond(cb, cond);
- uFlagsRWU(cb, FlagsOSZACP, FlagsEmpty, FlagsEmpty);
- uInstr2(cb, PUT, size, TempReg, tmpd, ArchReg, gregOfRM(rm));
- DIP("cmov%c%s %s,%s\n", nameISize(size),
- VG_(name_UCondcode)(cond),
- dis_buf,
- nameIReg(size,gregOfRM(rm)));
- return HI8(pair)+eip0;
- }
-}
-
-
-static
-Addr dis_xadd_G_E ( UCodeBlock* cb,
- UChar sorb,
- Int sz,
- Addr eip0 )
-{
- UChar rm = getUChar(eip0);
- UChar dis_buf[50];
-
- Int tmpd = newTemp(cb);
- Int tmpt = newTemp(cb);
-
- if (epartIsReg(rm)) {
- uInstr2(cb, GET, sz, ArchReg, eregOfRM(rm), TempReg, tmpd);
- uInstr2(cb, GET, sz, ArchReg, gregOfRM(rm), TempReg, tmpt);
- uInstr2(cb, ADD, sz, TempReg, tmpd, TempReg, tmpt);
- setFlagsFromUOpcode(cb, ADD);
- uInstr2(cb, PUT, sz, TempReg, tmpd, ArchReg, gregOfRM(rm));
- uInstr2(cb, PUT, sz, TempReg, tmpt, ArchReg, eregOfRM(rm));
- DIP("xadd%c %s, %s\n",
- nameISize(sz), nameIReg(sz,gregOfRM(rm)), nameIReg(sz,eregOfRM(rm)));
- return 1+eip0;
- } else {
- UInt pair = disAMode ( cb, sorb, eip0, dis_buf );
- Int tmpa = LOW24(pair);
- uInstr2(cb, LOAD, sz, TempReg, tmpa, TempReg, tmpd);
- uInstr2(cb, GET, sz, ArchReg, gregOfRM(rm), TempReg, tmpt);
- uInstr2(cb, ADD, sz, TempReg, tmpd, TempReg, tmpt);
- setFlagsFromUOpcode(cb, ADD);
- uInstr2(cb, STORE, sz, TempReg, tmpt, TempReg, tmpa);
- uInstr2(cb, PUT, sz, TempReg, tmpd, ArchReg, gregOfRM(rm));
- DIP("xadd%c %s, %s\n",
- nameISize(sz), nameIReg(sz,gregOfRM(rm)), dis_buf);
- return HI8(pair)+eip0;
- }
-}
-
-
-/* Moves of Ew into a segment register.
- mov Ew, Sw meaning
- mov reg-or-mem, reg
- Is passed the a ptr to the modRM byte, and the data size. Returns
- the address advanced completely over this instruction.
-
- Ew(src) is reg-or-mem
- Sw(dst) is seg reg.
-
- If E is reg, --> GETw %Ew, tmpv
- PUTSEG tmpv, %Sw
-
- If E is mem --> (getAddr E) -> tmpa
- LDw (tmpa), tmpb
- PUTSEG tmpb, %Sw
-*/
-static
-Addr dis_mov_Ew_Sw ( UCodeBlock* cb,
- UChar sorb,
- Addr eip0 )
-{
- UChar rm = getUChar(eip0);
- UChar dis_buf[50];
-
- if (epartIsReg(rm)) {
- Int tmpv = newTemp(cb);
- uInstr2(cb, GET, 2, ArchReg, eregOfRM(rm), TempReg, tmpv);
- uInstr2(cb, PUTSEG, 2, TempReg, tmpv, ArchRegS, gregOfRM(rm));
- DIP("movw %s,%s\n", nameIReg(2,eregOfRM(rm)), nameSReg(gregOfRM(rm)));
- return 1+eip0;
- }
-
- /* E refers to memory */
- {
- UInt pair = disAMode ( cb, sorb, eip0, dis_buf );
- Int tmpa = LOW24(pair);
- Int tmpb = newTemp(cb);
- uInstr2(cb, LOAD, 2, TempReg, tmpa, TempReg, tmpb);
- uInstr2(cb, PUTSEG, 2, TempReg, tmpb, ArchRegS, gregOfRM(rm));
- DIP("movw %s,%s\n", dis_buf,nameSReg(gregOfRM(rm)));
- return HI8(pair)+eip0;
- }
-}
-
-
-/* Moves of a segment register to Ew.
- mov Sw, Ew meaning
- mov reg, reg-or-mem
- Is passed the a ptr to the modRM byte, and the data size. Returns
- the address advanced completely over this instruction.
-
- Sw(src) is seg reg.
- Ew(dst) is reg-or-mem
-
- If E is reg, --> GETSEG %Sw, tmp
- PUTW tmp, %Ew
-
- If E is mem, --> (getAddr E) -> tmpa
- GETSEG %Sw, tmpv
- STW tmpv, (tmpa)
-*/
-static
-Addr dis_mov_Sw_Ew ( UCodeBlock* cb,
- UChar sorb,
- Addr eip0 )
-{
- UChar rm = getUChar(eip0);
- UChar dis_buf[50];
-
- if (epartIsReg(rm)) {
- Int tmpv = newTemp(cb);
- uInstr2(cb, GETSEG, 2, ArchRegS, gregOfRM(rm), TempReg, tmpv);
- uInstr2(cb, PUT, 2, TempReg, tmpv, ArchReg, eregOfRM(rm));
- DIP("movw %s,%s\n", nameSReg(gregOfRM(rm)), nameIReg(2,eregOfRM(rm)));
- return 1+eip0;
- }
-
- /* E refers to memory */
- {
- UInt pair = disAMode ( cb, sorb, eip0, dis_buf );
- Int tmpa = LOW24(pair);
- Int tmpv = newTemp(cb);
- uInstr2(cb, GETSEG, 2, ArchRegS, gregOfRM(rm), TempReg, tmpv);
- uInstr2(cb, STORE, 2, TempReg, tmpv, TempReg, tmpa);
- DIP("mov %s,%s\n", nameSReg(gregOfRM(rm)), dis_buf);
- return HI8(pair)+eip0;
- }
-}
-
-
-
-/* Simple MMX operations, either
- op (src)mmxreg, (dst)mmxreg
- or
- op (src)address, (dst)mmxreg
- opc is the byte following the 0x0F prefix.
-*/
-static
-Addr dis_MMXop_regmem_to_reg ( UCodeBlock* cb,
- UChar sorb,
- Addr eip,
- UChar opc,
- Char* name,
- Bool show_granularity )
-{
- Char dis_buf[50];
- UChar modrm = getUChar(eip);
- Bool isReg = epartIsReg(modrm);
-
- if (isReg) {
- eip++;
- uInstr1(cb, MMX2, 0,
- Lit16,
- (((UShort)(opc)) << 8) | ((UShort)modrm) );
- } else {
- UInt pair = disAMode ( cb, sorb, eip, dis_buf );
- Int tmpa = LOW24(pair);
- eip += HI8(pair);
- uInstr2(cb, MMX2_MemRd, 8,
- Lit16,
- (((UShort)(opc)) << 8) | ((UShort)modrm),
- TempReg, tmpa);
- }
-
- DIP("%s%s %s, %s\n",
- name, show_granularity ? nameMMXGran(opc & 3) : (Char*)"",
- ( isReg ? nameMMXReg(eregOfRM(modrm)) : dis_buf ),
- nameMMXReg(gregOfRM(modrm)) );
-
- return eip;
-}
-
-
-/* Simple MMX operations, either
- op (src)mmxreg, (dst)mmxreg
- or
- op (src)address, (dst)mmxreg
- opc is the byte following the 0x0F prefix.
-*/
-static
-Addr dis_MMXop_regmem_to_reg_Imm8 ( UCodeBlock* cb,
- UChar sorb,
- Addr eip,
- UChar opc,
- Char* name,
- Bool show_granularity )
-{
- Char dis_buf[50];
- UChar modrm = getUChar(eip);
- UChar imm8;
- Bool isReg = epartIsReg(modrm);
-
- if (isReg) {
- eip++;
- imm8 = getUChar(eip);
- eip++;
- uInstr2(cb, MMX3, 0,
- Lit16,
- (((UShort)(opc)) << 8) | ((UShort)modrm),
- Lit16,
- ((UShort)imm8));
- } else {
- UInt pair = disAMode ( cb, sorb, eip, dis_buf );
- Int tmpa = LOW24(pair);
- eip += HI8(pair);
- imm8 = getUChar(eip);
- eip++;
- uInstr3(cb, MMX2a1_MemRd, 8,
- Lit16,
- (((UShort)(opc)) << 8) | ((UShort)modrm),
- Lit16,
- ((UShort)imm8),
- TempReg, tmpa);
- }
-
- DIP("%s%s %s, %s, $%d\n",
- name, show_granularity ? nameMMXGran(opc & 3) : (Char*)"",
- ( isReg ? nameMMXReg(eregOfRM(modrm)) : dis_buf ),
- nameMMXReg(gregOfRM(modrm)), (Int)imm8 );
-
- return eip;
-}
-
-
-
-/* Simple SSE operations, either
- op (src)xmmreg, (dst)xmmreg
- or
- op (src)address, (dst)xmmreg
- 3 opcode bytes.
- Supplied eip points to the first address mode byte.
-*/
-static
-Addr dis_SSE3_reg_or_mem ( UCodeBlock* cb,
- UChar sorb,
- Addr eip,
- Int sz,
- Char* name,
- UChar opc1,
- UChar opc2,
- UChar opc3 )
-{
- Char dis_buf[50];
- UChar modrm = getUChar(eip);
- Bool isReg = epartIsReg(modrm);
-
- if (isReg) {
- /* Completely internal SSE insn. */
- uInstr2(cb, SSE4, 0, /* ignore sz for internal ops */
- Lit16, (((UShort)opc1) << 8) | (UShort)opc2,
- Lit16, (((UShort)opc3) << 8) | (UShort)modrm );
- eip++;
- } else {
- UInt pair = disAMode ( cb, sorb, eip, dis_buf );
- Int tmpa = LOW24(pair);
- eip += HI8(pair);
- uInstr3(cb, SSE3a_MemRd, sz,
- Lit16, (((UShort)(opc1)) << 8) | ((UShort)opc2),
- Lit16, (((UShort)(opc3)) << 8) | ((UShort)modrm),
- TempReg, tmpa);
- }
-
- DIP("%s %s, %s\n",
- name,
- ( isReg ? nameXMMReg(eregOfRM(modrm)) : dis_buf ),
- nameXMMReg(gregOfRM(modrm)) );
-
- return eip;
-}
-
-
-/* Simple SSE operations, either
- op (src)xmmreg, (dst)xmmreg
- or
- op (src)address, (dst)xmmreg
- 2 opcode bytes.
- Supplied eip points to the first address mode byte.
-*/
-static
-Addr dis_SSE2_reg_or_mem ( UCodeBlock* cb,
- UChar sorb,
- Addr eip,
- Int sz,
- Char* name,
- UChar opc1,
- UChar opc2 )
-{
- Char dis_buf[50];
- UChar modrm = getUChar(eip);
- Bool isReg = epartIsReg(modrm);
-
- if (isReg) {
- /* Completely internal SSE insn. */
- uInstr2(cb, SSE3, 0, /* ignore sz for internal ops */
- Lit16, (((UShort)opc1) << 8) | (UShort)opc2,
- Lit16, (UShort)modrm );
- eip++;
- } else {
- UInt pair = disAMode ( cb, sorb, eip, dis_buf );
- Int tmpa = LOW24(pair);
- eip += HI8(pair);
- uInstr3(cb, SSE2a_MemRd, sz,
- Lit16, (((UShort)(opc1)) << 8) | ((UShort)opc2),
- Lit16, (UShort)modrm,
- TempReg, tmpa);
- }
- DIP("%s %s, %s\n",
- name,
- ( isReg ? nameXMMReg(eregOfRM(modrm)) : dis_buf ),
- nameXMMReg(gregOfRM(modrm)) );
-
- return eip;
-}
-
-
-/* Simple SSE operations, either
- op (src)xmmreg, (dst)xmmreg
- or
- op (src)address, (dst)xmmreg
- 2 opcode bytes and an 8-bit immediate after the amode.
- Supplied eip points to the first address mode byte.
-*/
-static
-Addr dis_SSE2_reg_or_mem_Imm8 ( UCodeBlock* cb,
- UChar sorb,
- Addr eip,
- Int sz,
- Char* name,
- UChar opc1,
- UChar opc2 )
-{
- Char dis_buf[50];
- UChar modrm = getUChar(eip);
- UChar imm8;
- Bool isReg = epartIsReg(modrm);
-
- if (isReg) {
- /* Completely internal SSE insn. */
- eip++;
- imm8 = getUChar(eip);
- uInstr2(cb, SSE4, 0, /* ignore sz for internal ops */
- Lit16, (((UShort)opc1) << 8) | (UShort)opc2,
- Lit16, (((UShort)modrm) << 8) | (UShort)imm8 );
- eip++;
- } else {
- UInt pair = disAMode ( cb, sorb, eip, dis_buf );
- Int tmpa = LOW24(pair);
- eip += HI8(pair);
- imm8 = getUChar(eip);
- eip++;
- uInstr3(cb, SSE2a1_MemRd, sz,
- Lit16, (((UShort)(opc1)) << 8) | ((UShort)opc2),
- Lit16, (((UShort)(modrm)) << 8) | ((UShort)imm8),
- TempReg, tmpa);
- }
- DIP("%s %s, %s, $%d\n",
- name, ( isReg ? nameXMMReg(eregOfRM(modrm)) : dis_buf ),
- nameXMMReg(gregOfRM(modrm)), (Int)imm8 );
- return eip;
-}
-
-
-/* Simple SSE operations, either
- op (src)xmmreg, (dst)xmmreg
- or
- op (src)address, (dst)xmmreg
- 3 opcode bytes and an 8-bit immediate after the amode.
- Supplied eip points to the first address mode byte.
-*/
-static
-Addr dis_SSE3_reg_or_mem_Imm8 ( UCodeBlock* cb,
- UChar sorb,
- Addr eip,
- Int sz,
- Char* name,
- UChar opc1,
- UChar opc2,
- UChar opc3 )
-{
- Char dis_buf[50];
- UChar modrm = getUChar(eip);
- UChar imm8;
- Bool isReg = epartIsReg(modrm);
-
- if (isReg) {
- /* Completely internal SSE insn. */
- eip++;
- imm8 = getUChar(eip);
- uInstr3(cb, SSE5, 0, /* ignore sz for internal ops */
- Lit16, (((UShort)opc1) << 8) | (UShort)opc2,
- Lit16, (((UShort)opc3) << 8) | (UShort)modrm,
- Lit16, (UShort)imm8 );
- eip++;
- } else {
- UInt pair = disAMode ( cb, sorb, eip, dis_buf );
- Int tmpa = LOW24(pair);
- eip += HI8(pair);
- imm8 = getUChar(eip);
- eip++;
- uInstr3(cb, SSE3a1_MemRd, sz,
- Lit16, (((UShort)(opc1)) << 8) | ((UShort)opc2),
- Lit16, (((UShort)(opc3)) << 8) | ((UShort)modrm),
- TempReg, tmpa);
- uLiteral(cb, imm8);
- }
- DIP("%s %s, %s, $%d\n",
- name, ( isReg ? nameXMMReg(eregOfRM(modrm)) : dis_buf ),
- nameXMMReg(gregOfRM(modrm)), (Int)imm8 );
- return eip;
-}
-
-
-/* Disassemble an SSE insn which is either a simple reg-reg move or a
- move between registers and memory. Supplied eip points to the
- first address mode byte.
-*/
-static
-Addr dis_SSE3_load_store_or_mov ( UCodeBlock* cb,
- UChar sorb,
- Addr eip,
- Int sz,
- Bool is_store,
- Char* name,
- UChar insn0,
- UChar insn1,
- UChar insn2 )
-{
- Char dis_buf[50];
- UChar modrm = getUChar(eip);
- Bool isReg = epartIsReg(modrm);
- UInt pair;
- Int t1;
-
- if (isReg) {
- /* Completely internal; we can issue SSE4. */
- eip++;
- uInstr2(cb, SSE4, 0, /* ignore sz for internal ops */
- Lit16, (((UShort)insn0) << 8) | (UShort)insn1,
- Lit16, (((UShort)insn2) << 8) | (UShort)modrm );
- } else {
- pair = disAMode ( cb, sorb, eip, dis_buf );
- t1 = LOW24(pair);
- eip += HI8(pair);
- uInstr3(cb, is_store ? SSE3a_MemWr : SSE3a_MemRd, sz,
- Lit16, (((UShort)insn0) << 8) | (UShort)insn1,
- Lit16, (((UShort)insn2) << 8) | (UShort)modrm,
- TempReg, t1 );
- }
-
- if (is_store) {
- DIP("%s %s, %s\n",
- name,
- nameXMMReg(gregOfRM(modrm)),
- ( isReg ? nameXMMReg(eregOfRM(modrm)) : dis_buf ) );
- } else {
- DIP("%s %s, %s\n",
- name,
- ( isReg ? nameXMMReg(eregOfRM(modrm)) : dis_buf ),
- nameXMMReg(gregOfRM(modrm)) );
- }
- return eip;
-}
-
-
-/* Disassemble an SSE insn which is either a simple reg-reg move or a
- move between registers and memory. Supplied eip points to the
- first address mode byte. */
-static
-Addr dis_SSE2_load_store_or_mov ( UCodeBlock* cb,
- UChar sorb,
- Addr eip,
- Int sz,
- Bool is_store,
- Char* name,
- UChar insn0,
- UChar insn1 )
-{
- Char dis_buf[50];
- UChar modrm = getUChar(eip);
- Bool isReg = epartIsReg(modrm);
- UInt pair;
- Int t1;
-
- if (isReg) {
- /* Completely internal; we can issue SSE3. */
- eip++;
- uInstr2(cb, SSE3, 0, /* ignore sz for internal ops */
- Lit16, (((UShort)insn0) << 8) | (UShort)insn1,
- Lit16, (UShort)modrm );
- } else {
- pair = disAMode ( cb, sorb, eip, dis_buf );
- t1 = LOW24(pair);
- eip += HI8(pair);
- uInstr3(cb, is_store ? SSE2a_MemWr : SSE2a_MemRd, sz,
- Lit16, (((UShort)insn0) << 8) | (UShort)insn1,
- Lit16, (UShort)modrm,
- TempReg, t1 );
- }
-
- if (is_store) {
- DIP("%s %s, %s\n",
- name,
- nameXMMReg(gregOfRM(modrm)),
- ( isReg ? nameXMMReg(eregOfRM(modrm)) : dis_buf ) );
- } else {
- DIP("%s %s, %s\n",
- name,
- ( isReg ? nameXMMReg(eregOfRM(modrm)) : dis_buf ),
- nameXMMReg(gregOfRM(modrm)) );
- }
- return eip;
-}
-
-
-/* Simple SSE operations, either
- op (src)xmmreg, (dst)mmxreg
- or
- op (src)address, (dst)mmxreg
- 2 opcode bytes.
- Supplied eip points to the first address mode byte.
-*/
-static
-Addr dis_SSE2_to_MMX ( UCodeBlock *cb,
- UChar sorb,
- Addr eip,
- Int sz,
- Char* name,
- UChar opc1,
- UChar opc2 )
-{
- UChar dis_buf[50];
- UChar modrm = getUChar(eip);
- if (epartIsReg(modrm)) {
- /* Completely internal SSE insn. */
- uInstr2(cb, SSE3, 0, /* ignore sz for internal ops */
- Lit16, (((UShort)opc1) << 8) | (UShort)opc2,
- Lit16, (UShort)modrm );
- DIP("%s %s, %s\n",
- name, nameXMMReg(eregOfRM(modrm)), nameMMXReg(gregOfRM(modrm)) );
- eip++;
- } else {
- UInt pair = disAMode ( cb, sorb, eip, dis_buf );
- Int tmpa = LOW24(pair);
- eip += HI8(pair);
- uInstr3(cb, SSE2a_MemRd, sz,
- Lit16, (((UShort)(opc1)) << 8) | ((UShort)opc2),
- Lit16, ((UShort)modrm),
- TempReg, tmpa);
- DIP("%s %s, %s\n", name, dis_buf, nameMMXReg(gregOfRM(modrm)));
- }
- return eip;
-}
-
-
-/* Simple SSE operations, either
- op (src)mmxreg, (dst)xmmreg
- or
- op (src)address, (dst)xmmreg
- 2 opcode bytes.
- Supplied eip points to the first address mode byte.
-*/
-static
-Addr dis_SSE2_from_MMX ( UCodeBlock *cb,
- UChar sorb,
- Addr eip,
- Int sz,
- Char* name,
- UChar opc1,
- UChar opc2 )
-{
- UChar dis_buf[50];
- UChar modrm = getUChar(eip);
- if (epartIsReg(modrm)) {
- /* Completely internal SSE insn. */
- uInstr2(cb, SSE3, 0, /* ignore sz for internal ops */
- Lit16, (((UShort)opc1) << 8) | (UShort)opc2,
- Lit16, (UShort)modrm );
- DIP("%s %s, %s\n",
- name, nameMMXReg(eregOfRM(modrm)), nameXMMReg(gregOfRM(modrm)) );
- eip++;
- } else {
- UInt pair = disAMode ( cb, sorb, eip, dis_buf );
- Int tmpa = LOW24(pair);
- eip += HI8(pair);
- uInstr3(cb, SSE2a_MemRd, sz,
- Lit16, (((UShort)(opc1)) << 8) | ((UShort)opc2),
- Lit16, ((UShort)modrm),
- TempReg, tmpa);
- DIP("%s %s, %s\n", name, dis_buf, nameXMMReg(gregOfRM(modrm)));
- }
- return eip;
-}
-
-
-/* Simple SSE operations, either
- op (src)xmmreg, (dst)mmxreg
- or
- op (src)address, (dst)mmxreg
- 3 opcode bytes.
- Supplied eip points to the first address mode byte.
-*/
-static
-Addr dis_SSE3_to_MMX ( UCodeBlock *cb,
- UChar sorb,
- Addr eip,
- Int sz,
- Char* name,
- UChar opc1,
- UChar opc2,
- UChar opc3 )
-{
- UChar dis_buf[50];
- UChar modrm = getUChar(eip);
- if (epartIsReg(modrm)) {
- /* Completely internal SSE insn. */
- uInstr2(cb, SSE4, 0, /* ignore sz for internal ops */
- Lit16, (((UShort)opc1) << 8) | (UShort)opc2,
- Lit16, (((UShort)opc3) << 8) | (UShort)modrm );
- DIP("%s %s, %s\n",
- name, nameXMMReg(eregOfRM(modrm)), nameMMXReg(gregOfRM(modrm)) );
- eip++;
- } else {
- UInt pair = disAMode ( cb, sorb, eip, dis_buf );
- Int tmpa = LOW24(pair);
- eip += HI8(pair);
- uInstr3(cb, SSE3a_MemRd, sz,
- Lit16, (((UShort)(opc1)) << 8) | ((UShort)opc2),
- Lit16, (((UShort)(opc3)) << 8) | ((UShort)modrm),
- TempReg, tmpa);
- DIP("%s %s, %s\n", name, dis_buf, nameMMXReg(gregOfRM(modrm)));
- }
- return eip;
-}
-
-
-/* Simple SSE operations, either
- op (src)mmxreg, (dst)xmmreg
- or
- op (src)address, (dst)xmmreg
- 3 opcode bytes.
- Supplied eip points to the first address mode byte.
-*/
-static
-Addr dis_SSE3_from_MMX ( UCodeBlock *cb,
- UChar sorb,
- Addr eip,
- Int sz,
- Char* name,
- UChar opc1,
- UChar opc2,
- UChar opc3 )
-{
- UChar dis_buf[50];
- UChar modrm = getUChar(eip);
- if (epartIsReg(modrm)) {
- /* Completely internal SSE insn. */
- uInstr2(cb, SSE4, 0, /* ignore sz for internal ops */
- Lit16, (((UShort)opc1) << 8) | (UShort)opc2,
- Lit16, (((UShort)opc3) << 8) | (UShort)modrm );
- DIP("%s %s, %s\n",
- name, nameMMXReg(eregOfRM(modrm)), nameXMMReg(gregOfRM(modrm)) );
- eip++;
- } else {
- UInt pair = disAMode ( cb, sorb, eip, dis_buf );
- Int tmpa = LOW24(pair);
- eip += HI8(pair);
- uInstr3(cb, SSE3a_MemRd, sz,
- Lit16, (((UShort)(opc1)) << 8) | ((UShort)opc2),
- Lit16, (((UShort)(opc3)) << 8) | ((UShort)modrm),
- TempReg, tmpa);
- DIP("%s %s, %s\n", name, dis_buf, nameXMMReg(gregOfRM(modrm)));
- }
- return eip;
-}
-
-
-static
-void dis_push_segreg ( UCodeBlock* cb, UInt sreg, Int sz )
-{
- Int t1 = newTemp(cb), t2 = newTemp(cb);
- vg_assert(sz == 2 || sz == 4);
- uInstr2(cb, GETSEG, 2, ArchRegS, sreg, TempReg, t1);
- uInstr2(cb, GET, 4, ArchReg, R_ESP, TempReg, t2);
- uInstr2(cb, SUB, 4, Literal, 0, TempReg, t2);
- uLiteral(cb, sz);
- uInstr2(cb, PUT, 4, TempReg, t2, ArchReg, R_ESP);
- uInstr2(cb, STORE, 2, TempReg, t1, TempReg, t2);
- DIP("push %s\n", VG_(name_of_seg_reg)(sreg));
-}
-
-static
-void dis_pop_segreg ( UCodeBlock* cb, UInt sreg, Int sz )
-{
- Int t1 = newTemp(cb), t2 = newTemp(cb);
- vg_assert(sz == 2 || sz == 4);
- uInstr2(cb, GET, 4, ArchReg, R_ESP, TempReg, t2);
- uInstr2(cb, LOAD, 2, TempReg, t2, TempReg, t1);
- uInstr2(cb, ADD, 4, Literal, 0, TempReg, t2);
- uLiteral(cb, sz);
- uInstr2(cb, PUT, 4, TempReg, t2, ArchReg, R_ESP);
- uInstr2(cb, PUTSEG, 2, TempReg, t1, ArchRegS, sreg);
- DIP("pop %s\n", VG_(name_of_seg_reg)(sreg));
-}
-
-static
-void dis_ret ( UCodeBlock* cb, UInt d32 )
-{
- Int t1 = newTemp(cb), t2 = newTemp(cb);
- uInstr2(cb, GET, 4, ArchReg, R_ESP, TempReg, t1);
- uInstr2(cb, LOAD, 4, TempReg, t1, TempReg, t2);
- uInstr2(cb, ADD, 4, Literal, 0, TempReg, t1);
- uLiteral(cb, 4+d32);
- uInstr2(cb, PUT, 4, TempReg, t1, ArchReg, R_ESP);
- jmp_treg(cb, t2);
- LAST_UINSTR(cb).jmpkind = JmpRet;
-}
-
-/*------------------------------------------------------------*/
-/*--- Disassembling entire basic blocks ---*/
-/*------------------------------------------------------------*/
-
-/* Disassemble a single instruction into ucode, returning the updated
- eip, and setting *isEnd to True if this is the last insn in a basic
- block. Also do debug printing if necessary. */
-
-static Addr disInstr ( UCodeBlock* cb, Addr eip, Bool* isEnd )
-{
- UChar opc, modrm, abyte;
- UInt d32, pair;
- Int t1, t2, t3, t4;
- UChar dis_buf[50];
- Int am_sz, d_sz;
- static Char loc_buf[M_VG_ERRTXT];
-
- /* Holds eip at the start of the insn, so that we can print
- consistent error messages for unimplemented insns. */
- UChar* eip_start = (UChar*)eip;
-
- /* sz denotes the nominal data-op size of the insn; we change it to
- 2 if an 0x66 prefix is seen */
- Int sz = 4;
-
- /* sorb holds the segment-override-prefix byte, if any. Zero if no
- prefix has been seen, else one of {0x26, 0x3E, 0x64, 0x65}
- indicating the prefix. */
- UChar sorb = 0;
-
- Int first_uinstr = cb->used;
- *isEnd = False;
- t1 = t2 = t3 = t4 = INVALID_TEMPREG;
-
- DIP("\t0x%x: ", eip);
-
- /* Spot the client-request magic sequence. */
- {
- UChar* myeip = (UChar*)eip;
- /* Spot this:
- C1C01D roll $29, %eax
- C1C003 roll $3, %eax
- C1C81B rorl $27, %eax
- C1C805 rorl $5, %eax
- C1C00D roll $13, %eax
- C1C013 roll $19, %eax
- */
- if (myeip[ 0] == 0xC1 && myeip[ 1] == 0xC0 && myeip[ 2] == 0x1D &&
- myeip[ 3] == 0xC1 && myeip[ 4] == 0xC0 && myeip[ 5] == 0x03 &&
- myeip[ 6] == 0xC1 && myeip[ 7] == 0xC8 && myeip[ 8] == 0x1B &&
- myeip[ 9] == 0xC1 && myeip[10] == 0xC8 && myeip[11] == 0x05 &&
- myeip[12] == 0xC1 && myeip[13] == 0xC0 && myeip[14] == 0x0D &&
- myeip[15] == 0xC1 && myeip[16] == 0xC0 && myeip[17] == 0x13
- ) {
- eip += 18;
- jmp_lit(cb, eip);
- LAST_UINSTR(cb).jmpkind = JmpClientReq;
- *isEnd = True;
- DIP("%%edx = client_request ( %%eax )\n");
- return eip;
- }
- }
-
- /* Skip a LOCK prefix. */
- if (getUChar(eip) == 0xF0) {
- /* VG_(printf)("LOCK LOCK LOCK LOCK LOCK \n"); */
- uInstr0(cb, LOCK, 0);
- eip++;
- }
-
- /* Detect operand-size overrides. */
- if (getUChar(eip) == 0x66) { sz = 2; eip++; };
-
- /* segment override prefixes come after the operand-size override,
- it seems */
- switch (getUChar(eip)) {
- case 0x3E: /* %DS: */
- case 0x26: /* %ES: */
- case 0x64: /* %FS: */
- case 0x65: /* %GS: */
- sorb = getUChar(eip); eip++;
- break;
- case 0x2E: /* %CS: */
- /* 2E prefix on a conditional branch instruction is a
- branch-prediction hint, which can safely be ignored. */
- {
- UChar op1 = getUChar(eip+1);
- UChar op2 = getUChar(eip+2);
- if ((op1 >= 0x70 && op1 <= 0x7F)
- || (op1 == 0xE3)
- || (op1 == 0x0F && op2 >= 0x80 && op2 <= 0x8F)) {
- sorb = getUChar(eip); eip++;
- break;
- }
- }
- VG_(unimplemented)("x86 segment override (SEG=CS) prefix");
- /*NOTREACHED*/
- break;
- case 0x36: /* %SS: */
- VG_(unimplemented)("x86 segment override (SEG=SS) prefix");
- /*NOTREACHED*/
- break;
- default:
- break;
- }
-
- /* ---------------------------------------------------- */
- /* --- The SSE/SSE2 decoder. --- */
- /* ---------------------------------------------------- */
-
- /* If it looks like this CPU might support SSE, try decoding SSE
- insns. */
- if (VG_(have_ssestate)) {
- UChar* insn = (UChar*)eip;
-
- /* FXSAVE/FXRSTOR m32 -- load/store the FPU/MMX/SSE state. */
- if (insn[0] == 0x0F && insn[1] == 0xAE
- && (!epartIsReg(insn[2]))
- && (gregOfRM(insn[2]) == 1 || gregOfRM(insn[2]) == 0) ) {
- Bool store = gregOfRM(insn[2]) == 0;
- vg_assert(sz == 4);
- pair = disAMode ( cb, sorb, eip+2, dis_buf );
- t1 = LOW24(pair);
- eip += 2+HI8(pair);
- uInstr3(cb, store ? SSE2a_MemWr : SSE2a_MemRd, 512,
- Lit16, (((UShort)insn[0]) << 8) | (UShort)insn[1],
- Lit16, (UShort)insn[2],
- TempReg, t1 );
- DIP("fx%s %s\n", store ? "save" : "rstor", dis_buf );
- goto decode_success;
- }
-
- /* STMXCSR/LDMXCSR m32 -- load/store the MXCSR register. */
- if (insn[0] == 0x0F && insn[1] == 0xAE
- && (!epartIsReg(insn[2]))
- && (gregOfRM(insn[2]) == 3 || gregOfRM(insn[2]) == 2) ) {
- Bool store = gregOfRM(insn[2]) == 3;
- vg_assert(sz == 4);
- pair = disAMode ( cb, sorb, eip+2, dis_buf );
- t1 = LOW24(pair);
- eip += 2+HI8(pair);
- uInstr3(cb, store ? SSE2a_MemWr : SSE2a_MemRd, 4,
- Lit16, (((UShort)insn[0]) << 8) | (UShort)insn[1],
- Lit16, (UShort)insn[2],
- TempReg, t1 );
- DIP("%smxcsr %s\n", store ? "st" : "ld", dis_buf );
- goto decode_success;
- }
-
- /* LFENCE/MFENCE -- flush pending operations to memory */
- if (insn[0] == 0x0F && insn[1] == 0xAE
- && (epartIsReg(insn[2]))
- && (gregOfRM(insn[2]) >= 5 && gregOfRM(insn[2]) <= 6))
- {
- vg_assert(sz == 4);
- eip += 3;
- uInstr2(cb, SSE3, 0, /* ignore sz for internal ops */
- Lit16, (((UShort)0x0F) << 8) | (UShort)0xAE,
- Lit16, (UShort)insn[2] );
- DIP("%sfence\n", gregOfRM(insn[2]) == 5 ? "l" : "m");
- goto decode_success;
- }
-
- /* CLFLUSH -- flush cache line */
- if (insn[0] == 0x0F && insn[1] == 0xAE
- && (!epartIsReg(insn[2]))
- && (gregOfRM(insn[2]) == 7))
- {
- vg_assert(sz == 4);
- pair = disAMode ( cb, sorb, eip+2, dis_buf );
- t1 = LOW24(pair);
- eip += 2+HI8(pair);
- uInstr3(cb, SSE2a_MemRd, 0, /* ignore sz for internal ops */
- Lit16, (((UShort)0x0F) << 8) | (UShort)0xAE,
- Lit16, (UShort)insn[2],
- TempReg, t1 );
- DIP("clflush %s\n", dis_buf);
- goto decode_success;
- }
-
- /* CVTPI2PS (0x0F,0x2A) -- mm/m64, xmm */
- /* CVTPI2PD (0x66,0x0F,0x2A) -- mm/m64, xmm */
- if (insn[0] == 0x0F && insn[1] == 0x2A) {
- if (sz == 4) {
- eip = dis_SSE2_from_MMX
- ( cb, sorb, eip+2, 8, "cvtpi2ps",
- insn[0], insn[1] );
- } else {
- eip = dis_SSE3_from_MMX
- ( cb, sorb, eip+2, 8, "cvtpi2pd",
- 0x66, insn[0], insn[1] );
- }
- goto decode_success;
- }
-
- /* CVTTPS2PI (0x0F,0x2C) -- xmm/m64, mm */
- /* CVTPS2PI (0x0F,0x2D) -- xmm/m64, mm */
- /* CVTTPD2PI (0x66,0x0F,0x2C) -- xmm/m128, mm */
- /* CVTPD2PI (0x66,0x0F,0x2D) -- xmm/m128, mm */
- if (insn[0] == 0x0F
- && (insn[1] == 0x2C || insn[1] == 0x2D)) {
- if (sz == 4) {
- eip = dis_SSE2_to_MMX
- ( cb, sorb, eip+2, 8, "cvt{t}ps2pi",
- insn[0], insn[1] );
- } else {
- eip = dis_SSE3_to_MMX
- ( cb, sorb, eip+2, 16, "cvt{t}pd2pi",
- 0x66, insn[0], insn[1] );
- }
- goto decode_success;
- }
-
- /* CVTTSD2SI (0xF2,0x0F,0x2C) -- convert a double-precision float
- value in memory or xmm reg to int and put it in an ireg.
- Truncate. */
- /* CVTTSS2SI (0xF3,0x0F,0x2C) -- convert a single-precision float
- value in memory or xmm reg to int and put it in an ireg.
- Truncate. */
- /* CVTSD2SI (0xF2,0x0F,0x2D) -- convert a double-precision float
- value in memory or xmm reg to int and put it in an ireg. Round
- as per MXCSR. */
- /* CVTSS2SI (0xF3,0x0F,0x2D) -- convert a single-precision float
- value in memory or xmm reg to int and put it in an ireg. Round
- as per MXCSR. */
- if ((insn[0] == 0xF2 || insn[0] == 0xF3)
- && insn[1] == 0x0F
- && (insn[2] == 0x2C || insn[2] == 0x2D)) {
- vg_assert(sz == 4);
- modrm = insn[3];
- if (epartIsReg(modrm)) {
- /* We're moving a value in an xmm reg to an ireg. */
- eip += 4;
- t1 = newTemp(cb);
- /* sz is 4 for all 4 insns. */
- vg_assert(epartIsReg(modrm));
- uInstr3(cb, SSE3g_RegWr, 4,
- Lit16, (((UShort)insn[0]) << 8) | (UShort)insn[1],
- Lit16, (((UShort)insn[2]) << 8) | (UShort)modrm,
- TempReg, t1 );
- uInstr2(cb, PUT, 4, TempReg, t1, ArchReg, gregOfRM(modrm));
- DIP("cvt{t}s{s,d}2si %s, %s\n",
- nameXMMReg(eregOfRM(modrm)), nameIReg(4,gregOfRM(modrm)) );
- } else {
- /* So, we're reading memory and writing an ireg. This calls
- for the ultra-horrible SSE3ag_MemRd_RegWr uinstr. We
- can't do it in a roundabout route because it does some
- kind of conversion on the way, which we need to have
- happen too. So our only choice is to re-emit a suitably
- rehashed version of the instruction. */
- /* Destination ireg is GREG. Address goes as EREG as
- usual. */
- t1 = newTemp(cb); /* t1 holds value on its way to ireg */
- pair = disAMode ( cb, sorb, eip+3, dis_buf );
- t2 = LOW24(pair); /* t2 holds addr */
- eip += 3+HI8(pair);
- uInstr2(cb, SSE3ag_MemRd_RegWr, insn[0]==0xF2 ? 8 : 4,
- TempReg, t2, /* address */
- TempReg, t1 /* dest */);
- uLiteral(cb , (((UInt)insn[0]) << 24)
- | (((UInt)insn[1]) << 16)
- | (((UInt)insn[2]) << 8)
- | ((UInt)modrm) );
- uInstr2(cb, PUT, 4, TempReg, t1, ArchReg, gregOfRM(modrm));
- DIP("cvt{t}s{s,d}2si %s, %s\n",
- dis_buf, nameIReg(4,gregOfRM(modrm)) );
- }
- goto decode_success;
- }
-
- /* CVTSI2SS -- convert int reg, or int value in memory, to low 4
- bytes of XMM reg. */
- /* CVTSI2SD -- convert int reg, or int value in memory, to low 8
- bytes of XMM reg. */
- if ((insn[0] == 0xF3 /*CVTSI2SS*/ || insn[0] == 0xF2 /* CVTSI2SD*/)
- && insn[1] == 0x0F && insn[2] == 0x2A) {
- Char* s_or_d = insn[0]==0xF3 ? "s" : "d";
- vg_assert(sz == 4);
- modrm = insn[3];
- t1 = newTemp(cb);
- if (epartIsReg(modrm)) {
- uInstr2(cb, GET, 4, ArchReg, eregOfRM(modrm), TempReg, t1);
- vg_assert(epartIsReg(modrm));
- uInstr3(cb, SSE3e_RegRd, 4,
- Lit16, (((UShort)insn[0]) << 8) | (UShort)insn[1],
- Lit16, (((UShort)insn[2]) << 8) | (UShort)modrm,
- TempReg, t1 );
- eip += 4;
- DIP("cvtsi2s%s %s, %s\n", s_or_d,
- nameIReg(4,eregOfRM(modrm)), nameXMMReg(gregOfRM(modrm)));
- } else {
- pair = disAMode ( cb, sorb, eip+3, dis_buf );
- t2 = LOW24(pair);
- eip += 3+HI8(pair);
- uInstr3(cb, SSE3a_MemRd, 4,
- Lit16, (((UShort)insn[0]) << 8) | (UShort)insn[1],
- Lit16, (((UShort)insn[2]) << 8) | (UShort)modrm,
- TempReg, t2 );
- DIP("cvtsi2s%s %s, %s\n",
- s_or_d, dis_buf, nameXMMReg(gregOfRM(modrm)));
- }
- goto decode_success;
- }
-
- /* CVTPS2PD -- convert two packed floats to two packed doubles. */
- /* 0x66: CVTPD2PS -- convert two packed doubles to two packed floats. */
- if (insn[0] == 0x0F && insn[1] == 0x5A) {
- vg_assert(sz == 2 || sz == 4);
- if (sz == 4) {
- eip = dis_SSE2_reg_or_mem ( cb, sorb, eip+2, 8, "cvtps2pd",
- insn[0], insn[1] );
- } else {
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+2, 16, "cvtpd2ps",
- 0x66, insn[0], insn[1] );
- }
- goto decode_success;
- }
-
- /* CVTSS2SD -- convert one single float to double. */
- if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x5A) {
- vg_assert(sz == 4);
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+3, 4, "cvtss2sd",
- insn[0], insn[1], insn[2] );
- goto decode_success;
- }
-
- /* CVTSD2SS -- convert one single double. to float. */
- if (insn[0] == 0xF2 && insn[1] == 0x0F && insn[2] == 0x5A) {
- vg_assert(sz == 4);
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+3, 8, "cvtsd2ss",
- insn[0], insn[1], insn[2] );
- goto decode_success;
- }
-
- /* CVTDQ2PS -- convert four ints to four packed floats. */
- /* 0x66: CVTPS2DQ -- convert four packed floats to four ints. */
- if (insn[0] == 0x0F && insn[1] == 0x5B) {
- vg_assert(sz == 2 || sz == 4);
- if (sz == 4) {
- eip = dis_SSE2_reg_or_mem ( cb, sorb, eip+2, 16, "cvtdq2ps",
- insn[0], insn[1] );
- } else {
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+2, 16, "cvtps2dq",
- 0x66, insn[0], insn[1] );
- }
- goto decode_success;
- }
-
- /* CVTPD2DQ -- convert two packed doubles to two ints. */
- if (sz == 2
- && insn[0] == 0x0F && insn[1] == 0xE6) {
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+2, 8, "cvtpd2dq",
- 0x66, insn[0], insn[1] );
- goto decode_success;
- }
-
- /* CVTTPD2DQ -- convert two packed doubles to two ints with truncation. */
- if (insn[0] == 0xF2 && insn[1] == 0x0F && insn[2] == 0xE6) {
- vg_assert(sz == 4);
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+3, 8, "cvttpd2dq",
- insn[0], insn[1], insn[2] );
- goto decode_success;
- }
-
- /* CVTDQ2PD -- convert two ints to two packed doubles. */
- if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0xE6) {
- vg_assert(sz == 4);
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+3, 8, "cvtdq2pd",
- insn[0], insn[1], insn[2] );
- goto decode_success;
- }
-
- /* CVTTPS2DQ -- convert four packed floats to four ints with truncation. */
- if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x5B) {
- vg_assert(sz == 4);
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+3, 16, "cvttps2dq",
- insn[0], insn[1], insn[2] );
- goto decode_success;
- }
-
- /* CMPSS -- compare scalar floats. */
- if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0xC2) {
- vg_assert(sz == 4);
- eip = dis_SSE3_reg_or_mem_Imm8 ( cb, sorb, eip+3, 8, "cmpss",
- insn[0], insn[1], insn[2] );
- goto decode_success;
- }
-
- /* CMPSD -- compare scalar doubles. */
- if (insn[0] == 0xF2 && insn[1] == 0x0F && insn[2] == 0xC2) {
- vg_assert(sz == 4);
- eip = dis_SSE3_reg_or_mem_Imm8 ( cb, sorb, eip+3, 8, "cmpsd",
- insn[0], insn[1], insn[2] );
- goto decode_success;
- }
-
- /* sz==4: CMPPS -- compare packed floats */
- /* sz==2: CMPPD -- compare packed doubles */
- if (insn[0] == 0x0F && insn[1] == 0xC2) {
- vg_assert(sz == 4 || sz == 2);
- if (sz == 4) {
- eip = dis_SSE2_reg_or_mem_Imm8 ( cb, sorb, eip+2, 16, "cmpps",
- insn[0], insn[1] );
- } else {
- eip = dis_SSE3_reg_or_mem_Imm8 ( cb, sorb, eip+2, 16, "cmppd",
- 0x66, insn[0], insn[1] );
- }
- goto decode_success;
- }
-
- /* PSHUFD */
- if (sz == 2
- && insn[0] == 0x0F && insn[1] == 0x70) {
- eip = dis_SSE3_reg_or_mem_Imm8 ( cb, sorb, eip+2, 16,
- "pshufd",
- 0x66, insn[0], insn[1] );
- goto decode_success;
- }
-
- /* PSHUFLW */
- if (insn[0] == 0xF2 && insn[1] == 0x0F && insn[2] == 0x70) {
- eip = dis_SSE3_reg_or_mem_Imm8 ( cb, sorb, eip+3, 16,
- "pshuflw",
- insn[0], insn[1], insn[2] );
- goto decode_success;
- }
-
- /* PSHUFHW */
- if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x70) {
- eip = dis_SSE3_reg_or_mem_Imm8 ( cb, sorb, eip+3, 16,
- "pshufhw",
- insn[0], insn[1], insn[2] );
- goto decode_success;
- }
-
- /* SHUFPD */
- if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xC6) {
- eip = dis_SSE3_reg_or_mem_Imm8 ( cb, sorb, eip+2, 16, "shufpd",
- 0x66, insn[0], insn[1] );
- goto decode_success;
- }
-
- /* SHUFPS */
- if (insn[0] == 0x0F && insn[1] == 0xC6) {
- vg_assert(sz == 4);
- eip = dis_SSE2_reg_or_mem_Imm8 ( cb, sorb, eip+2, 16, "shufps",
- insn[0], insn[1] );
- goto decode_success;
- }
-
- /* 0xF2: MULSD */
- /* 0xF3: MULSS -- multiply low 4 bytes of XMM reg. */
- if ((insn[0] == 0xF2 || insn[0] == 0xF3)
- && insn[1] == 0x0F && insn[2] == 0x59) {
- Bool sz8 = insn[0] == 0xF2;
- vg_assert(sz == 4);
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+3, sz8 ? 8 : 4,
- sz8 ? "mulss" : "mulsd",
- insn[0], insn[1], insn[2] );
- goto decode_success;
- }
-
- /* MULPS */
- /* 0x66: MULPD */
- if (insn[0] == 0x0F && insn[1] == 0x59) {
- vg_assert(sz == 4 || sz == 2);
- if (sz == 4) {
- eip = dis_SSE2_reg_or_mem ( cb, sorb, eip+2, 16, "mulps",
- insn[0], insn[1] );
- } else {
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+2, 16, "mulpd",
- 0x66, insn[0], insn[1] );
- }
- goto decode_success;
- }
-
- /* 0xF2: DIVSD */
- /* 0xF3: DIVSS -- divide low 4 bytes of XMM reg. */
- if ((insn[0] == 0xF2 || insn[0] == 0xF3)
- && insn[1] == 0x0F && insn[2] == 0x5E) {
- Bool sz8 = insn[0] == 0xF2;
- vg_assert(sz == 4);
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+3, sz8 ? 8 : 4,
- sz8 ? "divsd" : "divss",
- insn[0], insn[1], insn[2] );
- goto decode_success;
- }
-
- /* DIVPS */
- /* 0x66: DIVPD */
- if (insn[0] == 0x0F && insn[1] == 0x5E) {
- vg_assert(sz == 4 || sz == 2);
- if (sz == 4) {
- eip = dis_SSE2_reg_or_mem ( cb, sorb, eip+2, 16, "divps",
- insn[0], insn[1] );
- } else {
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+2, 16, "divpd",
- 0x66, insn[0], insn[1] );
- }
- goto decode_success;
- }
-
- /* 0xF2: SUBSD */
- /* 0xF3: SUBSS */
- if ((insn[0] == 0xF2 || insn[0] == 0xF3)
- && insn[1] == 0x0F && insn[2] == 0x5C) {
- Bool sz8 = insn[0] == 0xF2;
- vg_assert(sz == 4);
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+3, sz8 ? 8 : 4,
- sz8 ? "subsd" : "subss",
- insn[0], insn[1], insn[2] );
- goto decode_success;
- }
-
- /* SUBPS */
- /* 0x66: SUBPD */
- if (insn[0] == 0x0F && insn[1] == 0x5C) {
- vg_assert(sz == 4 || sz == 2);
- if (sz == 4) {
- eip = dis_SSE2_reg_or_mem ( cb, sorb, eip+2, 16, "subps",
- insn[0], insn[1] );
- } else {
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+2, 16, "subpd",
- 0x66, insn[0], insn[1] );
- }
- goto decode_success;
- }
-
- /* 0xF2: ADDSD */
- /* 0xF3: ADDSS */
- if ((insn[0] == 0xF2 || insn[0] == 0xF3)
- && insn[1] == 0x0F && insn[2] == 0x58) {
- Bool sz8 = insn[0] == 0xF2;
- vg_assert(sz == 4);
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+3, sz8 ? 8 : 4,
- sz8 ? "addsd" : "addss",
- insn[0], insn[1], insn[2] );
- goto decode_success;
- }
-
- /* ADDPS */
- /* 0x66: ADDPD */
- if (insn[0] == 0x0F && insn[1] == 0x58) {
- vg_assert(sz == 4 || sz == 2);
- if (sz == 4) {
- eip = dis_SSE2_reg_or_mem ( cb, sorb, eip+2, 16, "addps",
- insn[0], insn[1] );
- } else {
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+2, 16, "addpd",
- 0x66, insn[0], insn[1] );
- }
- goto decode_success;
- }
-
- /* 0xF2: MINSD */
- /* 0xF3: MINSS */
- if ((insn[0] == 0xF2 || insn[0] == 0xF3)
- && insn[1] == 0x0F && insn[2] == 0x5D) {
- Bool sz8 = insn[0] == 0xF2;
- vg_assert(sz == 4);
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+3, sz8 ? 8 : 4,
- sz8 ? "minsd" : "minss",
- insn[0], insn[1], insn[2] );
- goto decode_success;
- }
-
- /* MINPS */
- /* 0x66: MINPD */
- if (insn[0] == 0x0F && insn[1] == 0x5D) {
- vg_assert(sz == 4 || sz == 2);
- if (sz == 4) {
- eip = dis_SSE2_reg_or_mem ( cb, sorb, eip+2, 16, "minps",
- insn[0], insn[1] );
- } else {
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+2, 16, "minpd",
- 0x66, insn[0], insn[1] );
- }
- goto decode_success;
- }
-
- /* 0xF3: MAXSD */
- /* 0xF3: MAXSS */
- if ((insn[0] == 0xF2 || insn[0] == 0xF3)
- && insn[1] == 0x0F && insn[2] == 0x5F) {
- Bool sz8 = insn[0] == 0xF2;
- vg_assert(sz == 4);
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+3, sz8 ? 8 : 4,
- sz8 ? "maxsd" : "maxss",
- insn[0], insn[1], insn[2] );
- goto decode_success;
- }
-
- /* MAXPS */
- /* 0x66: MAXPD */
- if (insn[0] == 0x0F && insn[1] == 0x5F) {
- vg_assert(sz == 4 || sz == 2);
- if (sz == 4) {
- eip = dis_SSE2_reg_or_mem ( cb, sorb, eip+2, 16, "maxps",
- insn[0], insn[1] );
- } else {
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+2, 16, "maxpd",
- 0x66, insn[0], insn[1] );
- }
- goto decode_success;
- }
-
- /* RCPPS -- reciprocal of packed floats */
- if (insn[0] == 0x0F && insn[1] == 0x53) {
- vg_assert(sz == 4);
- eip = dis_SSE2_reg_or_mem ( cb, sorb, eip+2, 16, "rcpps",
- insn[0], insn[1] );
- goto decode_success;
- }
-
- /* XORPS */
- /* 0x66: XORPD (src)xmmreg-or-mem, (dst)xmmreg */
- if (insn[0] == 0x0F && insn[1] == 0x57) {
- vg_assert(sz == 4 || sz == 2);
- if (sz == 4) {
- eip = dis_SSE2_reg_or_mem ( cb, sorb, eip+2, 16, "xorps",
- insn[0], insn[1] );
- } else {
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+2, 16, "xorpd",
- 0x66, insn[0], insn[1] );
- }
- goto decode_success;
- }
-
- /* ANDPS */
- /* 0x66: ANDPD (src)xmmreg-or-mem, (dst)xmmreg */
- if (insn[0] == 0x0F && insn[1] == 0x54) {
- vg_assert(sz == 4 || sz == 2);
- if (sz == 4) {
- eip = dis_SSE2_reg_or_mem ( cb, sorb, eip+2, 16, "andps",
- insn[0], insn[1] );
- } else {
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+2, 16, "andpd",
- 0x66, insn[0], insn[1] );
- }
- goto decode_success;
- }
-
- /* ORPS */
- /* 0x66: ORPD (src)xmmreg-or-mem, (dst)xmmreg */
- if (insn[0] == 0x0F && insn[1] == 0x56) {
- vg_assert(sz == 4 || sz == 2);
- if (sz == 4) {
- eip = dis_SSE2_reg_or_mem ( cb, sorb, eip+2, 16, "orps",
- insn[0], insn[1] );
- } else {
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+2, 16, "orpd",
- 0x66, insn[0], insn[1] );
- }
- goto decode_success;
- }
-
- /* PXOR (src)xmmreg-or-mem, (dst)xmmreg */
- if (sz == 2
- && insn[0] == 0x0F && insn[1] == 0xEF) {
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+2, 16, "pxor",
- 0x66, insn[0], insn[1] );
- goto decode_success;
- }
-
- /* PAND (src)xmmreg-or-mem, (dst)xmmreg */
- if (sz == 2
- && insn[0] == 0x0F && insn[1] == 0xDB) {
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+2, 16, "pand",
- 0x66, insn[0], insn[1] );
- goto decode_success;
- }
-
- /* PANDN (src)xmmreg-or-mem, (dst)xmmreg */
- if (sz == 2
- && insn[0] == 0x0F && insn[1] == 0xDF) {
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+2, 16, "pandn",
- 0x66, insn[0], insn[1] );
- goto decode_success;
- }
-
- /* POR (src)xmmreg-or-mem, (dst)xmmreg */
- if (sz == 2
- && insn[0] == 0x0F && insn[1] == 0xEB) {
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+2, 16, "por",
- 0x66, insn[0], insn[1] );
- goto decode_success;
- }
-
- /* 0xDA: PMINUB(src)xmmreg-or-mem, (dst)xmmreg */
- /* 0xEA: PMINSW(src)xmmreg-or-mem, (dst)xmmreg */
- if (sz == 2
- && insn[0] == 0x0F
- && (insn[1] == 0xDA || insn[1] == 0xEA)) {
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+2, 16, "pmin{ub,sw}",
- 0x66, insn[0], insn[1] );
- goto decode_success;
- }
-
- /* 0xDE: PMAXUB(src)xmmreg-or-mem, (dst)xmmreg */
- /* 0xEE: PMAXSW(src)xmmreg-or-mem, (dst)xmmreg */
- if (sz == 2
- && insn[0] == 0x0F
- && (insn[1] == 0xDE || insn[1] == 0xEE)) {
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+2, 16, "pmax{ub,sw}",
- 0x66, insn[0], insn[1] );
- goto decode_success;
- }
-
- /* 0xE0: PAVGB(src)xmmreg-or-mem, (dst)xmmreg */
- /* 0xE3: PAVGW(src)xmmreg-or-mem, (dst)xmmreg */
- if (sz == 2
- && insn[0] == 0x0F
- && (insn[1] == 0xE0 || insn[1] == 0xE3)) {
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+2, 16, "pavg{b,w}",
- 0x66, insn[0], insn[1] );
- goto decode_success;
- }
-
- /* 0xF6: PSADBW(src)xmmreg-or-mem, (dst)xmmreg */
- if (sz == 2
- && insn[0] == 0x0F && insn[1] == 0xF6) {
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+2, 16, "psadbw",
- 0x66, insn[0], insn[1] );
- goto decode_success;
- }
-
- /* 0x60: PUNPCKLBW (src)xmmreg-or-mem, (dst)xmmreg */
- /* 0x61: PUNPCKLWD (src)xmmreg-or-mem, (dst)xmmreg */
- /* 0x62: PUNPCKLDQ (src)xmmreg-or-mem, (dst)xmmreg */
- /* 0x6C: PUNPCKQLQDQ (src)xmmreg-or-mem, (dst)xmmreg */
- if (sz == 2
- && insn[0] == 0x0F
- && (insn[1] == 0x60 || insn[1] == 0x61
- || insn[1] == 0x62 || insn[1] == 0x6C)) {
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+2, 16,
- "punpckl{bw,wd,dq,qdq}",
- 0x66, insn[0], insn[1] );
- goto decode_success;
- }
-
- /* 0x68: PUNPCKHBW (src)xmmreg-or-mem, (dst)xmmreg */
- /* 0x69: PUNPCKHWD (src)xmmreg-or-mem, (dst)xmmreg */
- /* 0x6A: PUNPCKHDQ (src)xmmreg-or-mem, (dst)xmmreg */
- /* 0x6D: PUNPCKHQDQ (src)xmmreg-or-mem, (dst)xmmreg */
- if (sz == 2
- && insn[0] == 0x0F
- && (insn[1] == 0x68 || insn[1] == 0x69
- || insn[1] == 0x6A || insn[1] == 0x6D)) {
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+2, 16,
- "punpckh{bw,wd,dq,qdq}",
- 0x66, insn[0], insn[1] );
- goto decode_success;
- }
-
- /* 0x14: UNPCKLPD (src)xmmreg-or-mem, (dst)xmmreg. Reads a+0
- .. a+7, so we can say size 8 */
- /* 0x15: UNPCKHPD (src)xmmreg-or-mem, (dst)xmmreg. Reads a+8
- .. a+15, but we have no way to express this, so better say size
- 16. Sigh. */
- if (sz == 2
- && insn[0] == 0x0F
- && (insn[1] == 0x14 || insn[1] == 0x15)) {
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+2,
- insn[1]==0x14 ? 8 : 16,
- "unpck{l,h}pd",
- 0x66, insn[0], insn[1] );
- goto decode_success;
- }
-
- /* 0x14: UNPCKLPS (src)xmmreg-or-mem, (dst)xmmreg Reads a+0
- .. a+7, so we can say size 8 */
- /* 0x15: UNPCKHPS (src)xmmreg-or-mem, (dst)xmmreg Reads a+8
- .. a+15, but we have no way to express this, so better say size
- 16. Sigh. */
- if (sz == 4
- && insn[0] == 0x0F
- && (insn[1] == 0x14 || insn[1] == 0x15)) {
- eip = dis_SSE2_reg_or_mem ( cb, sorb, eip+2,
- insn[1]==0x14 ? 8 : 16,
- "unpck{l,h}ps",
- insn[0], insn[1] );
- goto decode_success;
- }
-
- /* 0xFC: PADDB (src)xmmreg-or-mem, (dst)xmmreg */
- /* 0xFD: PADDW (src)xmmreg-or-mem, (dst)xmmreg */
- /* 0xFE: PADDD (src)xmmreg-or-mem, (dst)xmmreg */
- /* 0xD4: PADDQ (src)xmmreg-or-mem, (dst)xmmreg */
- if (sz == 2
- && insn[0] == 0x0F
- && (insn[1] == 0xFC || insn[1] == 0xFD
- || insn[1] == 0xFE || insn[1] == 0xD4)) {
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+2, 16, "padd{b,w,d,q}",
- 0x66, insn[0], insn[1] );
- goto decode_success;
- }
-
- /* 0xEC: PADDSB (src)xmmreg-or-mem, (dst)xmmreg */
- /* 0xED: PADDSW (src)xmmreg-or-mem, (dst)xmmreg */
- if (sz == 2
- && insn[0] == 0x0F
- && (insn[1] == 0xEC || insn[1] == 0xED)) {
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+2, 16, "padds{b,w}",
- 0x66, insn[0], insn[1] );
- goto decode_success;
- }
-
- /* 0xDC: PADDUSB (src)xmmreg-or-mem, (dst)xmmreg */
- /* 0xDD: PADDUSW (src)xmmreg-or-mem, (dst)xmmreg */
- if (sz == 2
- && insn[0] == 0x0F
- && (insn[1] == 0xDC || insn[1] == 0xDD)) {
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+2, 16, "paddus{b,w}",
- 0x66, insn[0], insn[1] );
- goto decode_success;
- }
-
- /* 0xF8: PSUBB (src)xmmreg-or-mem, (dst)xmmreg */
- /* 0xF9: PSUBW (src)xmmreg-or-mem, (dst)xmmreg */
- /* 0xFA: PSUBD (src)xmmreg-or-mem, (dst)xmmreg */
- /* 0xFB: PSUBQ (src)xmmreg-or-mem, (dst)xmmreg */
- if (sz == 2
- && insn[0] == 0x0F
- && (insn[1] == 0xF8 || insn[1] == 0xF9
- || insn[1] == 0xFA || insn[1] == 0xFB)) {
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+2, 16, "psub{b,w,d,q}",
- 0x66, insn[0], insn[1] );
- goto decode_success;
- }
-
- /* 0xE8: PSUBSB (src)xmmreg-or-mem, (dst)xmmreg */
- /* 0xE9: PSUBSW (src)xmmreg-or-mem, (dst)xmmreg */
- if (sz == 2
- && insn[0] == 0x0F
- && (insn[1] == 0xE8 || insn[1] == 0xE9)) {
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+2, 16, "psubs{b,w}",
- 0x66, insn[0], insn[1] );
- goto decode_success;
- }
-
- /* 0xD8: PSUBUSB (src)xmmreg-or-mem, (dst)xmmreg */
- /* 0xD9: PSUBUSW (src)xmmreg-or-mem, (dst)xmmreg */
- if (sz == 2
- && insn[0] == 0x0F
- && (insn[1] == 0xD8 || insn[1] == 0xD9)) {
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+2, 16, "psubus{b,w}",
- 0x66, insn[0], insn[1] );
- goto decode_success;
- }
-
- /* 0xE4: PMULHUW(src)xmmreg-or-mem, (dst)xmmreg */
- /* 0xE5: PMULHW(src)xmmreg-or-mem, (dst)xmmreg */
- /* 0xD5: PMULLW(src)xmmreg-or-mem, (dst)xmmreg */
- if (sz == 2
- && insn[0] == 0x0F
- && (insn[1] == 0xE4 || insn[1] == 0xE5 || insn[1] == 0xD5)) {
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+2, 16, "pmul{hu,h,l}w",
- 0x66, insn[0], insn[1] );
- goto decode_success;
- }
-
- /* 0xD5: PMULUDQ(src)xmmreg-or-mem, (dst)xmmreg */
- if (sz == 2
- && insn[0] == 0x0F && insn[1] == 0xF4) {
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+2, 16, "pmuludq",
- 0x66, insn[0], insn[1] );
- goto decode_success;
- }
-
- /* 0xF5: PMADDWD(src)xmmreg-or-mem, (dst)xmmreg */
- if (sz == 2
- && insn[0] == 0x0F
- && insn[1] == 0xF5) {
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+2, 16, "pmaddwd",
- 0x66, insn[0], insn[1] );
- goto decode_success;
- }
-
- /* 0x74: PCMPEQB (src)xmmreg-or-mem, (dst)xmmreg */
- /* 0x75: PCMPEQW (src)xmmreg-or-mem, (dst)xmmreg */
- /* 0x76: PCMPEQD (src)xmmreg-or-mem, (dst)xmmreg */
- if (sz == 2
- && insn[0] == 0x0F
- && (insn[1] == 0x74 || insn[1] == 0x75 || insn[1] == 0x76)) {
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+2, 16, "pcmpeq{b,w,d}",
- 0x66, insn[0], insn[1] );
- goto decode_success;
- }
-
- /* 0x64: PCMPGTB (src)xmmreg-or-mem, (dst)xmmreg */
- /* 0x65: PCMPGTW (src)xmmreg-or-mem, (dst)xmmreg */
- /* 0x66: PCMPGTD (src)xmmreg-or-mem, (dst)xmmreg */
- if (sz == 2
- && insn[0] == 0x0F
- && (insn[1] == 0x64 || insn[1] == 0x65 || insn[1] == 0x66)) {
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+2, 16, "pcmpgt{b,w,d}",
- 0x66, insn[0], insn[1] );
- goto decode_success;
- }
-
- /* 0x63: PACKSSWB (src)xmmreg-or-mem, (dst)xmmreg */
- /* 0x6B: PACKSSDW (src)xmmreg-or-mem, (dst)xmmreg */
- if (sz == 2
- && insn[0] == 0x0F
- && (insn[1] == 0x63 || insn[1] == 0x6B)) {
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+2, 16, "packss{wb,dw}",
- 0x66, insn[0], insn[1] );
- goto decode_success;
- }
-
- /* 0x67: PACKUSWB (src)xmmreg-or-mem, (dst)xmmreg */
- if (sz == 2
- && insn[0] == 0x0F
- && insn[1] == 0x67) {
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+2, 16, "packuswb",
- 0x66, insn[0], insn[1] );
- goto decode_success;
- }
-
- /* 0xF1: PSLLW (src)xmmreg-or-mem, (dst)xmmreg */
- /* 0xF2: PSLLD (src)xmmreg-or-mem, (dst)xmmreg */
- /* 0xF3: PSLLQ (src)xmmreg-or-mem, (dst)xmmreg */
- if (sz == 2
- && insn[0] == 0x0F
- && (insn[1] == 0xF1 || insn[1] == 0xF2 || insn[1] == 0xF3)) {
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+2, 16, "psll{b,w,d}",
- 0x66, insn[0], insn[1] );
- goto decode_success;
- }
-
- /* 0xD1: PSRLW (src)xmmreg-or-mem, (dst)xmmreg */
- /* 0xD2: PSRLD (src)xmmreg-or-mem, (dst)xmmreg */
- /* 0xD3: PSRLQ (src)xmmreg-or-mem, (dst)xmmreg */
- if (sz == 2
- && insn[0] == 0x0F
- && (insn[1] == 0xD1 || insn[1] == 0xD2 || insn[1] == 0xD3)) {
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+2, 16, "psrl{b,w,d}",
- 0x66, insn[0], insn[1] );
- goto decode_success;
- }
-
- /* 0xE1: PSRAW (src)xmmreg-or-mem, (dst)xmmreg */
- /* 0xE2: PSRAD (src)xmmreg-or-mem, (dst)xmmreg */
- if (sz == 2
- && insn[0] == 0x0F
- && (insn[1] == 0xE1 || insn[1] == 0xE2)) {
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+2, 16, "psra{w,d}",
- 0x66, insn[0], insn[1] );
- goto decode_success;
- }
-
- /* (U)COMISD (src)xmmreg-or-mem, (dst)xmmreg */
- if (sz == 2
- && insn[0] == 0x0F
- && ( insn[1] == 0x2E || insn[1] == 0x2F ) ) {
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+2, 8, "{u}comisd",
- 0x66, insn[0], insn[1] );
- vg_assert(LAST_UINSTR(cb).opcode == SSE3a_MemRd
- || LAST_UINSTR(cb).opcode == SSE4);
- uFlagsRWU(cb, FlagsEmpty, FlagsOSZACP, FlagsEmpty);
- goto decode_success;
- }
-
- /* (U)COMISS (src)xmmreg-or-mem, (dst)xmmreg */
- if (sz == 4
- && insn[0] == 0x0F
- && ( insn[1] == 0x2E || insn[ 1 ] == 0x2F )) {
- eip = dis_SSE2_reg_or_mem ( cb, sorb, eip+2, 4, "{u}comiss",
- insn[0], insn[1] );
- vg_assert(LAST_UINSTR(cb).opcode == SSE2a_MemRd
- || LAST_UINSTR(cb).opcode == SSE3);
- uFlagsRWU(cb, FlagsEmpty, FlagsOSZACP, FlagsEmpty);
- goto decode_success;
- }
-
- /* MOVSD -- move 8 bytes of XMM reg to/from XMM reg or mem. */
- if (insn[0] == 0xF2
- && insn[1] == 0x0F
- && (insn[2] == 0x11 || insn[2] == 0x10)) {
- vg_assert(sz == 4);
- eip = dis_SSE3_load_store_or_mov
- ( cb, sorb, eip+3, 8, insn[2]==0x11, "movsd",
- insn[0], insn[1], insn[2] );
- goto decode_success;
- }
-
- /* MOVQ -- move 8 bytes of XMM reg to XMM reg or mem. How
- does this differ from MOVSD ?? */
- if (sz == 2
- && insn[0] == 0x0F
- && insn[1] == 0xD6) {
- eip = dis_SSE3_load_store_or_mov
- ( cb, sorb, eip+2, 8, True /*store*/, "movq",
- 0x66, insn[0], insn[1] );
- goto decode_success;
- }
-
- /* MOVQ -- move 8 bytes of XMM reg or mem to XMM reg. How
- does this differ from MOVSD ?? */
- if (insn[0] == 0xF3
- && insn[1] == 0x0F
- && insn[2] == 0x7E) {
- eip = dis_SSE3_load_store_or_mov
- ( cb, sorb, eip+3, 8, False /*load*/, "movq",
- insn[0], insn[1], insn[2] );
- goto decode_success;
- }
-
- /* MOVDQ2Q -- move low 4 bytes of XMM reg to MMX reg. */
- if (insn[0] == 0xF2
- && insn[1] == 0x0F
- && insn[2] == 0xD6) {
- eip = dis_SSE3_to_MMX
- ( cb, sorb, eip+3, 8, "movdq2q",
- insn[0], insn[1], insn[2] );
- goto decode_success;
- }
-
- /* MOVQ2DQ -- move MMX reg to low 4 bytes of XMM reg. */
- if (insn[0] == 0xF3
- && insn[1] == 0x0F
- && insn[2] == 0xD6) {
- eip = dis_SSE3_from_MMX
- ( cb, sorb, eip+3, 8, "movq2dq",
- insn[0], insn[1], insn[2] );
- goto decode_success;
- }
-
- /* MOVSS -- move 4 bytes of XMM reg to/from XMM reg or mem. */
- if (insn[0] == 0xF3
- && insn[1] == 0x0F
- && (insn[2] == 0x11 || insn[2] == 0x10)) {
- vg_assert(sz == 4);
- eip = dis_SSE3_load_store_or_mov
- ( cb, sorb, eip+3, 4, insn[2]==0x11, "movss",
- insn[0], insn[1], insn[2] );
- goto decode_success;
- }
-
- /* I don't understand how MOVAPD differs from MOVAPS. */
- /* MOVAPD (28,29) -- aligned load/store of xmm reg, or xmm-xmm reg
- move */
- if (sz == 2
- && insn[0] == 0x0F && insn[1] == 0x28) {
- UChar* name = "movapd";
- //(insn[1] == 0x10 || insn[1] == 0x11)
- // ? "movups" : "movaps";
- Bool store = False; //insn[1] == 0x29 || insn[1] == 0x11;
- eip = dis_SSE3_load_store_or_mov
- ( cb, sorb, eip+2, 16, store, name,
- 0x66, insn[0], insn[1] );
- goto decode_success;
- }
-
- /* sz==4: MOVAPS (28,29) -- aligned load/store of xmm reg, or
- xmm-xmm reg move */
- /* sz==4: MOVUPS (10,11) -- unaligned load/store of xmm reg, or
- xmm-xmm reg move */
- /* sz==2: MOVAPD (28,29) -- aligned load/store of xmm reg, or
- xmm-xmm reg move */
- /* sz==2: MOVUPD (10,11) -- unaligned load/store of xmm reg, or
- xmm-xmm reg move */
- if (insn[0] == 0x0F && (insn[1] == 0x28
- || insn[1] == 0x29
- || insn[1] == 0x10
- || insn[1] == 0x11)) {
- UChar* name = (insn[1] == 0x10 || insn[1] == 0x11)
- ? "movups" : "movaps";
- Bool store = insn[1] == 0x29 || insn[1] == 0x11;
- vg_assert(sz == 2 || sz == 4);
- if (sz == 4) {
- eip = dis_SSE2_load_store_or_mov
- ( cb, sorb, eip+2, 16, store, name,
- insn[0], insn[1] );
- } else {
- eip = dis_SSE3_load_store_or_mov
- ( cb, sorb, eip+2, 16, store, name,
- 0x66, insn[0], insn[1] );
- }
- goto decode_success;
- }
-
- /* MOVDQA -- aligned 16-byte load/store. */
- if (sz == 2
- && insn[0] == 0x0F
- && (insn[1] == 0x6F || insn[1] == 0x7F)) {
- Bool is_store = insn[1]==0x7F;
- eip = dis_SSE3_load_store_or_mov
- (cb, sorb, eip+2, 16, is_store, "movdqa",
- 0x66, insn[0], insn[1] );
- goto decode_success;
- }
-
- /* MOVDQU -- unaligned 16-byte load/store. */
- if (insn[0] == 0xF3
- && insn[1] == 0x0F
- && (insn[2] == 0x6F || insn[2] == 0x7F)) {
- Bool is_store = insn[2]==0x7F;
- eip = dis_SSE3_load_store_or_mov
- (cb, sorb, eip+3, 16, is_store, "movdqu",
- insn[0], insn[1], insn[2] );
- goto decode_success;
- }
-
- /* MOVNTDQ -- 16-byte store with temporal hint (which we
- ignore). */
- if (sz == 2
- && insn[0] == 0x0F
- && insn[1] == 0xE7) {
- eip = dis_SSE3_load_store_or_mov
- (cb, sorb, eip+2, 16, True /* is_store */, "movntdq",
- 0x66, insn[0], insn[1] );
- goto decode_success;
- }
-
- /* MOVNTPS -- 16-byte store with temporal hint (which we
- ignore). */
- if (insn[0] == 0x0F
- && insn[1] == 0x2B) {
- eip = dis_SSE2_load_store_or_mov
- (cb, sorb, eip+2, 16, True /* is_store */, "movntps",
- insn[0], insn[1] );
- goto decode_success;
- }
-
- /* MOVNTPD -- 16-byte store with temporal hint (which we
- ignore). */
- if (sz == 2
- && insn[0] == 0x0F
- && insn[1] == 0x2B) {
- eip = dis_SSE3_load_store_or_mov
- (cb, sorb, eip+2, 16, True /* is_store */, "movntpd",
- 0x66, insn[0], insn[1] );
- goto decode_success;
- }
-
- /* MOVD -- 4-byte move between xmmregs and (ireg or memory). */
- if (sz == 2
- && insn[0] == 0x0F
- && (insn[1] == 0x6E || insn[1] == 0x7E)) {
- Bool is_store = insn[1]==0x7E;
- modrm = insn[2];
- if (epartIsReg(modrm) && is_store) {
- t1 = newTemp(cb);
- uInstr3(cb, SSE3e_RegWr, 4,
- Lit16, (((UShort)0x66) << 8) | (UShort)insn[0],
- Lit16, (((UShort)insn[1]) << 8) | (UShort)modrm,
- TempReg, t1 );
- uInstr2(cb, PUT, 4, TempReg, t1, ArchReg, eregOfRM(modrm));
- DIP("movd %s, %s\n",
- nameXMMReg(gregOfRM(modrm)), nameIReg(4,eregOfRM(modrm)));
- eip += 3;
- } else
- if (epartIsReg(modrm) && !is_store) {
- t1 = newTemp(cb);
- uInstr2(cb, GET, 4, ArchReg, eregOfRM(modrm), TempReg, t1);
- uInstr3(cb, SSE3e_RegRd, 4,
- Lit16, (((UShort)0x66) << 8) | (UShort)insn[0],
- Lit16, (((UShort)insn[1]) << 8) | (UShort)modrm,
- TempReg, t1 );
- DIP("movd %s, %s\n",
- nameIReg(4,eregOfRM(modrm)), nameXMMReg(gregOfRM(modrm)));
- eip += 3;
- } else {
- eip = dis_SSE3_load_store_or_mov
- (cb, sorb, eip+2, 4, is_store, "movd",
- 0x66, insn[0], insn[1] );
- }
- goto decode_success;
- }
-
- /* PEXTRW from SSE register; writes ireg */
- if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xC5) {
- t1 = newTemp(cb);
- modrm = insn[2];
- vg_assert(epartIsReg(modrm));
- vg_assert((modrm & 0xC0) == 0xC0);
- uInstr3(cb, SSE3g1_RegWr, 4,
- Lit16, (((UShort)0x66) << 8) | (UShort)insn[0],
- Lit16, (((UShort)insn[1]) << 8) | (UShort)modrm,
- TempReg, t1 );
- uLiteral(cb, insn[3]);
- uInstr2(cb, PUT, 4, TempReg, t1, ArchReg, gregOfRM(modrm));
- DIP("pextrw %s, %d, %s\n",
- nameXMMReg(eregOfRM(modrm)), (Int)insn[3],
- nameIReg(4, gregOfRM(modrm)));
- eip += 4;
- goto decode_success;
- }
-
- /* PINSRW to SSE register; reads mem or ireg */
- if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xC4) {
- t1 = newTemp(cb);
- modrm = insn[2];
- if (epartIsReg(modrm)) {
- uInstr2(cb, GET, 2, ArchReg, eregOfRM(modrm), TempReg, t1);
- vg_assert(epartIsReg(modrm));
- uInstr3(cb, SSE3e1_RegRd, 2,
- Lit16, (((UShort)0x66) << 8) | (UShort)insn[0],
- Lit16, (((UShort)insn[1]) << 8) | (UShort)modrm,
- TempReg, t1 );
- uLiteral(cb, insn[3]);
- DIP("pinsrw %s, %d, %s\n",
- nameIReg(2, eregOfRM(modrm)), (Int)insn[3],
- nameXMMReg(gregOfRM(modrm)));
- eip += 4;
- } else {
- VG_(core_panic)("PINSRW mem");
- }
- goto decode_success;
- }
-
- /* SQRTSD: square root of scalar double. */
- if (insn[0] == 0xF2 && insn[1] == 0x0F && insn[2] == 0x51) {
- vg_assert(sz == 4);
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+3, 8,
- "sqrtsd",
- insn[0], insn[1], insn[2] );
- goto decode_success;
- }
-
- /* SQRTSS: square root of scalar float. */
- if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x51) {
- vg_assert(sz == 4);
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+3, 4,
- "sqrtss",
- insn[0], insn[1], insn[2] );
- goto decode_success;
- }
-
- /* RSQRTSS: square root reciprocal of scalar float. */
- if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x52) {
- vg_assert(sz == 4);
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+3, 4,
- "sqrtss",
- insn[0], insn[1], insn[2] );
- goto decode_success;
- }
-
- /* 0xF3: RCPSS -- reciprocal of scalar float */
- if (insn[0] == 0xF3 && insn[1] == 0x0F && insn[2] == 0x53) {
- vg_assert(sz == 4);
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+3, 4,
- "rcpss",
- insn[0], insn[1], insn[2] );
- goto decode_success;
- }
-
- /* MOVMSKPD -- extract 2 sign bits from a xmm reg and copy them to
- an ireg. Top 30 bits of ireg are set to zero. */
- /* MOVMSKPS -- extract 4 sign bits from a xmm reg and copy them to
- an ireg. Top 28 bits of ireg are set to zero. */
- if (insn[0] == 0x0F && insn[1] == 0x50) {
- vg_assert(sz == 4 || sz == 2);
- modrm = insn[2];
- /* Intel docs don't say anything about a memory source being
- allowed here. */
- vg_assert(epartIsReg(modrm));
- t1 = newTemp(cb);
- if (sz == 4) {
- uInstr3(cb, SSE2g_RegWr, 4,
- Lit16, (((UShort)insn[0]) << 8) | (UShort)insn[1],
- Lit16, (UShort)modrm,
- TempReg, t1 );
- uInstr2(cb, PUT, 4, TempReg, t1, ArchReg, gregOfRM(modrm));
- } else {
- uInstr3(cb, SSE3g_RegWr, 4,
- Lit16, (((UShort)0x66) << 8) | (UShort)insn[0],
- Lit16, (((UShort)insn[1]) << 8) | (UShort)modrm,
- TempReg, t1 );
- uInstr2(cb, PUT, 4, TempReg, t1, ArchReg, gregOfRM(modrm));
- }
- DIP("movmskp%c %s, %s\n", sz == 4 ? 's' : 'd',
- nameXMMReg(eregOfRM(modrm)), nameIReg(4,gregOfRM(modrm)));
- eip += 3;
- goto decode_success;
- }
-
- /* ANDNPS */
- /* 0x66: ANDNPD (src)xmmreg-or-mem, (dst)xmmreg */
- if (insn[0] == 0x0F && insn[1] == 0x55) {
- vg_assert(sz == 4 || sz == 2);
- if (sz == 4) {
- eip = dis_SSE2_reg_or_mem ( cb, sorb, eip+2, 16, "andnps",
- insn[0], insn[1] );
- } else {
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+2, 16, "andnpd",
- 0x66, insn[0], insn[1] );
- }
- goto decode_success;
- }
-
- /* MOVHLPS -- move two packed floats from high quadword to low quadword */
- /* MOVLPS -- load/store two packed floats to/from low quadword. */
- /* MOVLPD -- load/store packed double to/from low quadword. */
- if (insn[0] == 0x0F
- && (insn[1] == 0x12 || insn[1] == 0x13)) {
- Bool is_store = insn[1]==0x13;
- vg_assert(sz == 4 || sz == 2);
- if (sz == 4) {
- if (epartIsReg(insn[2])) {
- vg_assert(insn[1]==0x12);
- eip = dis_SSE2_reg_or_mem ( cb, sorb, eip+2, 16, "movhlps",
- insn[0], insn[1] );
- } else {
- eip = dis_SSE2_load_store_or_mov
- (cb, sorb, eip+2, 8, is_store, "movlps",
- insn[0], insn[1] );
- }
- } else {
- vg_assert(!epartIsReg(insn[2]));
- eip = dis_SSE3_load_store_or_mov
- (cb, sorb, eip+2, 8, is_store, "movlpd",
- 0x66, insn[0], insn[1] );
- }
- goto decode_success;
- }
-
- /* MOVLHPS -- move two packed floats from low quadword to high quadword */
- /* MOVHPS -- load/store two packed floats to/from high quadword. */
- /* MOVHPD -- load/store packed double to/from high quadword. */
- if (insn[0] == 0x0F
- && (insn[1] == 0x16 || insn[1] == 0x17)) {
- Bool is_store = insn[1]==0x17;
- vg_assert(sz == 4 || sz == 2);
- if (sz == 4) {
- if (epartIsReg(insn[2])) {
- vg_assert(insn[1]==0x16);
- eip = dis_SSE2_reg_or_mem ( cb, sorb, eip+2, 16, "movlhps",
- insn[0], insn[1] );
- } else {
- eip = dis_SSE2_load_store_or_mov
- (cb, sorb, eip+2, 8, is_store, "movhps",
- insn[0], insn[1] );
- }
- } else {
- vg_assert(!epartIsReg(insn[2]));
- eip = dis_SSE3_load_store_or_mov
- (cb, sorb, eip+2, 8, is_store, "movhpd",
- 0x66, insn[0], insn[1] );
- }
- goto decode_success;
- }
-
- /* PMOVMSKB -- extract 16 sign bits from a xmm reg and copy them to
- an ireg. Top 16 bits of ireg are set to zero. */
- if (sz == 2 && insn[0] == 0x0F && insn[1] == 0xD7) {
- modrm = insn[2];
- /* Intel docs don't say anything about a memory source being
- allowed here. */
- vg_assert(epartIsReg(modrm));
- t1 = newTemp(cb);
- uInstr3(cb, SSE3g_RegWr, 4,
- Lit16, (((UShort)0x66) << 8) | (UShort)insn[0],
- Lit16, (((UShort)insn[1]) << 8) | (UShort)modrm,
- TempReg, t1 );
- uInstr2(cb, PUT, 4, TempReg, t1, ArchReg, gregOfRM(modrm));
- DIP("pmovmskb %s, %s\n",
- nameXMMReg(eregOfRM(modrm)), nameIReg(4,gregOfRM(modrm)));
- eip += 3;
- goto decode_success;
- }
-
- /* sz==4: SQRTPS: square root of packed float. */
- /* sz==2: SQRTPD: square root of packed double. */
- if (insn[0] == 0x0F && insn[1] == 0x51) {
- vg_assert(sz == 2 || sz == 4);
- if (sz == 4) {
- eip = dis_SSE2_reg_or_mem ( cb, sorb, eip+2, 16,
- "sqrtps",
- insn[0], insn[1] );
- } else {
- eip = dis_SSE3_reg_or_mem ( cb, sorb, eip+2, 16,
- "sqrtpd",
- 0x66, insn[0], insn[1] );
- }
- goto decode_success;
- }
-
- /* RSQRTPS: square root reciprocal of packed float. */
- if (insn[0] == 0x0F && insn[1] == 0x52) {
- vg_assert(sz == 4);
- eip = dis_SSE2_reg_or_mem ( cb, sorb, eip+2, 16,
- "rsqrtps",
- insn[0], insn[1] );
- goto decode_success;
- }
-
- /* Fall through into the non-SSE decoder. */
-
- } /* if (VG_(have_ssestate)) */
-
-
- /* ---------------------------------------------------- */
- /* --- end of the SSE/SSE2 decoder. --- */
- /* ---------------------------------------------------- */
-
- /* Get the primary opcode. */
- opc = getUChar(eip); eip++;
-
- /* We get here if the current insn isn't SSE, or this CPU doesn't
- support SSE. */
-
- switch (opc) {
-
- /* ------------------------ Control flow --------------- */
-
- case 0xC2: /* RET imm16 */
- d32 = getUDisp16(eip); eip += 2;
- dis_ret(cb, d32);
- *isEnd = True;
- DIP("ret %d\n", d32);
- break;
- case 0xC3: /* RET */
- dis_ret(cb, 0);
- *isEnd = True;
- DIP("ret\n");
- break;
-
- case 0xE8: /* CALL J4 */
- d32 = getUDisp32(eip); eip += 4;
- d32 += eip; /* eip now holds return-to addr, d32 is call-to addr */
- if (d32 == eip && getUChar(eip) >= 0x58
- && getUChar(eip) <= 0x5F) {
- /* Specially treat the position-independent-code idiom
- call X
- X: popl %reg
- as
- movl %eip, %reg.
- since this generates better code, but for no other reason. */
- Int archReg = getUChar(eip) - 0x58;
- /* VG_(printf)("-- fPIC thingy\n"); */
- t1 = newTemp(cb);
- uInstr2(cb, MOV, 4, Literal, 0, TempReg, t1);
- uLiteral(cb, eip);
- uInstr2(cb, PUT, 4, TempReg, t1, ArchReg, archReg);
- eip++; /* Step over the POP */
- DIP("call 0x%x ; popl %s\n",d32,nameIReg(4,archReg));
- } else {
- /* The normal sequence for a call. */
- t1 = newTemp(cb); t2 = newTemp(cb); t3 = newTemp(cb);
- uInstr2(cb, GET, 4, ArchReg, R_ESP, TempReg, t3);
- uInstr2(cb, MOV, 4, TempReg, t3, TempReg, t1);
- uInstr2(cb, SUB, 4, Literal, 0, TempReg, t1);
- uLiteral(cb, 4);
- uInstr2(cb, PUT, 4, TempReg, t1, ArchReg, R_ESP);
- uInstr2(cb, MOV, 4, Literal, 0, TempReg, t2);
- uLiteral(cb, eip);
- uInstr2(cb, STORE, 4, TempReg, t2, TempReg, t1);
- jmp_lit(cb, d32);
- LAST_UINSTR(cb).jmpkind = JmpCall;
- *isEnd = True;
- DIP("call 0x%x\n",d32);
- }
- break;
-
- case 0xC8: /* ENTER */
- d32 = getUDisp16(eip); eip += 2;
- abyte = getUChar(eip); eip++;
-
- vg_assert(sz == 4);
- vg_assert(abyte == 0);
-
- t1 = newTemp(cb); t2 = newTemp(cb);
- uInstr2(cb, GET, sz, ArchReg, R_EBP, TempReg, t1);
- uInstr2(cb, GET, 4, ArchReg, R_ESP, TempReg, t2);
- uInstr2(cb, SUB, 4, Literal, 0, TempReg, t2);
- uLiteral(cb, sz);
- uInstr2(cb, PUT, 4, TempReg, t2, ArchReg, R_ESP);
- uInstr2(cb, STORE, 4, TempReg, t1, TempReg, t2);
- uInstr2(cb, PUT, 4, TempReg, t2, ArchReg, R_EBP);
- if (d32) {
- uInstr2(cb, SUB, 4, Literal, 0, TempReg, t2);
- uLiteral(cb, d32);
- uInstr2(cb, PUT, 4, TempReg, t2, ArchReg, R_ESP);
- }
- DIP("enter 0x%x, 0x%x", d32, abyte);
- break;
-
- case 0xC9: /* LEAVE */
- t1 = newTemp(cb); t2 = newTemp(cb);
- uInstr2(cb, GET, 4, ArchReg, R_EBP, TempReg, t1);
- /* First PUT ESP looks redundant, but need it because ESP must
- always be up-to-date for Memcheck to work... */
- uInstr2(cb, PUT, 4, TempReg, t1, ArchReg, R_ESP);
- uInstr2(cb, LOAD, 4, TempReg, t1, TempReg, t2);
- uInstr2(cb, PUT, 4, TempReg, t2, ArchReg, R_EBP);
- uInstr2(cb, ADD, 4, Literal, 0, TempReg, t1);
- uLiteral(cb, 4);
- uInstr2(cb, PUT, 4, TempReg, t1, ArchReg, R_ESP);
- DIP("leave");
- break;
-
- /* ---------------- Misc weird-ass insns --------------- */
-
- case 0x27: /* DAA */
- case 0x2F: /* DAS */
- t1 = newTemp(cb);
- uInstr2(cb, GET, 1, ArchReg, R_AL, TempReg, t1);
- /* Widen %AL to 32 bits, so it's all defined when we push it. */
- uInstr1(cb, WIDEN, 4, TempReg, t1);
- uWiden(cb, 1, False);
- uInstr0(cb, CALLM_S, 0);
- uInstr1(cb, PUSH, 4, TempReg, t1);
- uInstr1(cb, CALLM, 0, Lit16,
- opc == 0x27 ? VGOFF_(helper_DAA) : VGOFF_(helper_DAS) );
- uFlagsRWU(cb, FlagsAC, FlagsSZACP, FlagO);
- uInstr1(cb, POP, 4, TempReg, t1);
- uInstr0(cb, CALLM_E, 0);
- uInstr2(cb, PUT, 1, TempReg, t1, ArchReg, R_AL);
- DIP(opc == 0x27 ? "daa\n" : "das\n");
- break;
-
- case 0x37: /* AAA */
- case 0x3F: /* AAS */
- t1 = newTemp(cb);
- uInstr2(cb, GET, 2, ArchReg, R_EAX, TempReg, t1);
- /* Widen %AL to 32 bits, so it's all defined when we push it. */
- uInstr1(cb, WIDEN, 4, TempReg, t1);
- uWiden(cb, 2, False);
- uInstr0(cb, CALLM_S, 0);
- uInstr1(cb, PUSH, 4, TempReg, t1);
- uInstr1(cb, CALLM, 0, Lit16,
- opc == 0x37 ? VGOFF_(helper_AAA) : VGOFF_(helper_AAS) );
- uFlagsRWU(cb, FlagA, FlagsAC, FlagsEmpty);
- uInstr1(cb, POP, 4, TempReg, t1);
- uInstr0(cb, CALLM_E, 0);
- uInstr2(cb, PUT, 2, TempReg, t1, ArchReg, R_EAX);
- DIP(opc == 0x37 ? "aaa\n" : "aas\n");
- break;
-
- case 0xD4: /* AAM */
- case 0xD5: /* AAD */
- d32 = getUChar(eip); eip++;
- if (d32 != 10) VG_(core_panic)("disInstr: AAM/AAD but base not 10 !");
- t1 = newTemp(cb);
- uInstr2(cb, GET, 2, ArchReg, R_EAX, TempReg, t1);
- /* Widen %AX to 32 bits, so it's all defined when we push it. */
- uInstr1(cb, WIDEN, 4, TempReg, t1);
- uWiden(cb, 2, False);
- uInstr0(cb, CALLM_S, 0);
- uInstr1(cb, PUSH, 4, TempReg, t1);
- uInstr1(cb, CALLM, 0, Lit16,
- opc == 0xD4 ? VGOFF_(helper_AAM) : VGOFF_(helper_AAD) );
- uFlagsRWU(cb, FlagsEmpty, FlagsSZP, FlagsEmpty);
- uInstr1(cb, POP, 4, TempReg, t1);
- uInstr0(cb, CALLM_E, 0);
- uInstr2(cb, PUT, 2, TempReg, t1, ArchReg, R_EAX);
- DIP(opc == 0xD4 ? "aam\n" : "aad\n");
- break;
-
- /* ------------------------ CWD/CDQ -------------------- */
-
- case 0x98: /* CBW */
- t1 = newTemp(cb);
- if (sz == 4) {
- uInstr2(cb, GET, 2, ArchReg, R_EAX, TempReg, t1);
- uInstr1(cb, WIDEN, 4, TempReg, t1); /* 4 == dst size */
- uWiden(cb, 2, True);
- uInstr2(cb, PUT, 4, TempReg, t1, ArchReg, R_EAX);
- DIP("cwd\n");
- } else {
- vg_assert(sz == 2);
- uInstr2(cb, GET, 1, ArchReg, R_EAX, TempReg, t1);
- uInstr1(cb, WIDEN, 2, TempReg, t1); /* 2 == dst size */
- uWiden(cb, 1, True);
- uInstr2(cb, PUT, 2, TempReg, t1, ArchReg, R_EAX);
- DIP("cbw\n");
- }
- break;
-
- case 0x99: /* CWD/CDQ */
- t1 = newTemp(cb);
- uInstr2(cb, GET, sz, ArchReg, R_EAX, TempReg, t1);
- uInstr2(cb, SAR, sz, Literal, 0, TempReg, t1);
- uLiteral(cb, sz == 2 ? 15 : 31);
- uInstr2(cb, PUT, sz, TempReg, t1, ArchReg, R_EDX);
- DIP(sz == 2 ? "cwdq\n" : "cdqq\n");
- break;
-
- /* ------------------------ FPU ops -------------------- */
-
- case 0x9E: /* SAHF */
- codegen_SAHF ( cb );
- DIP("sahf\n");
- break;
-
- case 0x9F: /* LAHF */
- codegen_LAHF ( cb );
- DIP("lahf\n");
- break;
-
- case 0x9B: /* FWAIT */
- /* ignore? */
- DIP("fwait\n");
- break;
-
- case 0xD8:
- case 0xD9:
- case 0xDA:
- case 0xDB:
- case 0xDC:
- case 0xDD:
- case 0xDE:
- case 0xDF:
- eip = dis_fpu ( cb, sorb, opc, eip );
- break;
-
- /* ------------------------ INC & DEC ------------------ */
-
- case 0x40: /* INC eAX */
- case 0x41: /* INC eCX */
- case 0x42: /* INC eDX */
- case 0x43: /* INC eBX */
- case 0x44: /* INC eSP */
- case 0x45: /* INC eBP */
- case 0x46: /* INC eSI */
- case 0x47: /* INC eDI */
- t1 = newTemp(cb);
- uInstr2(cb, GET, sz, ArchReg, (UInt)(opc - 0x40),
- TempReg, t1);
- uInstr1(cb, INC, sz, TempReg, t1);
- setFlagsFromUOpcode(cb, INC);
- uInstr2(cb, PUT, sz, TempReg, t1, ArchReg,
- (UInt)(opc - 0x40));
- DIP("inc%c %s\n", nameISize(sz), nameIReg(sz,opc-0x40));
- break;
-
- case 0x48: /* DEC eAX */
- case 0x49: /* DEC eCX */
- case 0x4A: /* DEC eDX */
- case 0x4B: /* DEC eBX */
- case 0x4C: /* DEC eSP */
- case 0x4D: /* DEC eBP */
- case 0x4E: /* DEC eSI */
- case 0x4F: /* DEC eDI */
- t1 = newTemp(cb);
- uInstr2(cb, GET, sz, ArchReg, (UInt)(opc - 0x48),
- TempReg, t1);
- uInstr1(cb, DEC, sz, TempReg, t1);
- setFlagsFromUOpcode(cb, DEC);
- uInstr2(cb, PUT, sz, TempReg, t1, ArchReg,
- (UInt)(opc - 0x48));
- DIP("dec%c %s\n", nameISize(sz), nameIReg(sz,opc-0x48));
- break;
-
- /* ------------------------ INT ------------------------ */
-
- case 0xCD: /* INT imm8 */
- d32 = getUChar(eip); eip++;
- if (d32 != 0x80) goto decode_failure;
- /* It's important that all ArchRegs carry their up-to-date value
- at this point. So we declare an end-of-block here, which
- forces any TempRegs caching ArchRegs to be flushed. */
- jmp_lit(cb, eip);
- LAST_UINSTR(cb).jmpkind = JmpSyscall;
- *isEnd = True;
- DIP("int $0x80\n");
- break;
-
- /* ------------------------ Jcond, byte offset --------- */
-
- case 0xEB: /* Jb (jump, byte offset) */
- d32 = (eip+1) + getSDisp8(eip); eip++;
- jmp_lit(cb, d32);
- *isEnd = True;
- DIP("jmp-8 0x%x\n", d32);
- break;
-
- case 0xE9: /* Jv (jump, 16/32 offset) */
- d32 = (eip+sz) + getSDisp(sz,eip); eip += sz;
- jmp_lit(cb, d32);
- *isEnd = True;
- DIP("jmp 0x%x\n", d32);
- break;
-
- case 0x70:
- case 0x71:
- case 0x72: /* JBb/JNAEb (jump below) */
- case 0x73: /* JNBb/JAEb (jump not below) */
- case 0x74: /* JZb/JEb (jump zero) */
- case 0x75: /* JNZb/JNEb (jump not zero) */
- case 0x76: /* JBEb/JNAb (jump below or equal) */
- case 0x77: /* JNBEb/JAb (jump not below or equal) */
- case 0x78: /* JSb (jump negative) */
- case 0x79: /* JSb (jump not negative) */
- case 0x7A: /* JP (jump parity even) */
- case 0x7B: /* JNP/JPO (jump parity odd) */
- case 0x7C: /* JLb/JNGEb (jump less) */
- case 0x7D: /* JGEb/JNLb (jump greater or equal) */
- case 0x7E: /* JLEb/JNGb (jump less or equal) */
- case 0x7F: /* JGb/JNLEb (jump greater) */
- d32 = (eip+1) + getSDisp8(eip); eip++;
- jcc_lit(cb, d32, (Condcode)(opc - 0x70));
- /* It's actually acceptable not to end this basic block at a
- control transfer, reducing the number of jumps through
- vg_dispatch, at the expense of possibly translating the insns
- following this jump twice. This does give faster code, but
- on the whole I don't think the effort is worth it. */
- jmp_lit(cb, eip);
- *isEnd = True;
- /* The above 3 lines would be removed if the bb was not to end
- here. */
- DIP("j%s-8 0x%x\n", VG_(name_UCondcode)(opc - 0x70), d32);
- break;
-
- case 0xE3: /* JECXZ or perhaps JCXZ, depending on OSO ? Intel
- manual says it depends on address size override,
- which doesn't sound right to me. */
- d32 = (eip+1) + getSDisp8(eip); eip++;
- t1 = newTemp(cb);
- uInstr2(cb, GET, 4, ArchReg, R_ECX, TempReg, t1);
- uInstr2(cb, JIFZ, 4, TempReg, t1, Literal, 0);
- uLiteral(cb, d32);
- DIP("j%sz 0x%x\n", nameIReg(sz, R_ECX), d32);
- break;
-
- case 0xE0: /* LOOPNE disp8 */
- case 0xE1: /* LOOPE disp8 */
- case 0xE2: /* LOOP disp8 */
- /* Again, the docs say this uses ECX/CX as a count depending on
- the address size override, not the operand one. Since we
- don't handle address size overrides, I guess that means
- ECX. */
- d32 = (eip+1) + getSDisp8(eip); eip++;
- t1 = newTemp(cb);
- uInstr2(cb, GET, 4, ArchReg, R_ECX, TempReg, t1);
- uInstr1(cb, DEC, 4, TempReg, t1);
- uInstr2(cb, PUT, 4, TempReg, t1, ArchReg, R_ECX);
- uInstr2(cb, JIFZ, 4, TempReg, t1, Literal, 0);
- uLiteral(cb, eip);
- if (opc == 0xE0 || opc == 0xE1) { /* LOOPE/LOOPNE */
- jcc_lit(cb, eip, (opc == 0xE1 ? CondNZ : CondZ));
- }
- jmp_lit(cb, d32);
- *isEnd = True;
- DIP("loop 0x%x\n", d32);
- break;
-
- /* ------------------------ IMUL ----------------------- */
-
- case 0x69: /* IMUL Iv, Ev, Gv */
- eip = dis_imul_I_E_G ( cb, sorb, sz, eip, sz );
- break;
- case 0x6B: /* IMUL Ib, Ev, Gv */
- eip = dis_imul_I_E_G ( cb, sorb, sz, eip, 1 );
- break;
-
- /* ------------------------ MOV ------------------------ */
-
- case 0x88: /* MOV Gb,Eb */
- eip = dis_mov_G_E(cb, sorb, 1, eip);
- break;
-
- case 0x89: /* MOV Gv,Ev */
- eip = dis_mov_G_E(cb, sorb, sz, eip);
- break;
-
- case 0x8A: /* MOV Eb,Gb */
- eip = dis_mov_E_G(cb, sorb, 1, eip);
- break;
-
- case 0x8B: /* MOV Ev,Gv */
- eip = dis_mov_E_G(cb, sorb, sz, eip);
- break;
-
- case 0x8D: /* LEA M,Gv */
- modrm = getUChar(eip);
- if (epartIsReg(modrm))
- VG_(core_panic)("LEA M,Gv: modRM refers to register");
- /* NOTE! this is the one place where a segment override prefix
- has no effect on the address calculation. Therefore we pass
- zero instead of sorb here. */
- pair = disAMode ( cb, /*sorb*/ 0, eip, dis_buf );
- eip += HI8(pair);
- t1 = LOW24(pair);
- uInstr2(cb, PUT, sz, TempReg, t1, ArchReg, gregOfRM(modrm));
- DIP("lea%c %s, %s\n", nameISize(sz), dis_buf,
- nameIReg(sz,gregOfRM(modrm)));
- break;
-
- case 0x8C: /* MOV Sw,Ew -- MOV from a SEGMENT REGISTER */
- eip = dis_mov_Sw_Ew(cb, sorb, eip);
- break;
-
- case 0x8E: /* MOV Ew,Sw -- MOV to a SEGMENT REGISTER */
- eip = dis_mov_Ew_Sw(cb, sorb, eip);
- break;
-
- case 0xA0: /* MOV Ob,AL */
- sz = 1;
- /* Fall through ... */
- case 0xA1: /* MOV Ov,eAX */
- d32 = getUDisp32(eip); eip += 4;
- t1 = newTemp(cb); t2 = newTemp(cb);
- uInstr2(cb, MOV, 4, Literal, 0, TempReg, t2);
- uLiteral(cb, d32);
- handleSegOverride(cb, sorb, t2);
- uInstr2(cb, LOAD, sz, TempReg, t2, TempReg, t1);
- uInstr2(cb, PUT, sz, TempReg, t1, ArchReg, R_EAX);
- DIP("mov%c %s0x%x, %s\n", nameISize(sz), sorbTxt(sorb),
- d32, nameIReg(sz,R_EAX));
- break;
-
- case 0xA2: /* MOV AL,Ob */
- sz = 1;
- /* Fall through ... */
- case 0xA3: /* MOV eAX,Ov */
- d32 = getUDisp32(eip); eip += 4;
- t1 = newTemp(cb); t2 = newTemp(cb);
- uInstr2(cb, GET, sz, ArchReg, R_EAX, TempReg, t1);
- uInstr2(cb, MOV, 4, Literal, 0, TempReg, t2);
- uLiteral(cb, d32);
- handleSegOverride(cb, sorb, t2);
- uInstr2(cb, STORE, sz, TempReg, t1, TempReg, t2);
- DIP("mov%c %s, %s0x%x\n", nameISize(sz), nameIReg(sz,R_EAX),
- sorbTxt(sorb), d32);
- break;
-
- case 0xB0: /* MOV imm,AL */
- case 0xB1: /* MOV imm,CL */
- case 0xB2: /* MOV imm,DL */
- case 0xB3: /* MOV imm,BL */
- case 0xB4: /* MOV imm,AH */
- case 0xB5: /* MOV imm,CH */
- case 0xB6: /* MOV imm,DH */
- case 0xB7: /* MOV imm,BH */
- d32 = getUChar(eip); eip += 1;
- t1 = newTemp(cb);
- uInstr2(cb, MOV, 1, Literal, 0, TempReg, t1);
- uLiteral(cb, d32);
- uInstr2(cb, PUT, 1, TempReg, t1, ArchReg, opc-0xB0);
- DIP("movb $0x%x,%s\n", d32, nameIReg(1,opc-0xB0));
- break;
-
- case 0xB8: /* MOV imm,eAX */
- case 0xB9: /* MOV imm,eCX */
- case 0xBA: /* MOV imm,eDX */
- case 0xBB: /* MOV imm,eBX */
- case 0xBC: /* MOV imm,eSP */
- case 0xBD: /* MOV imm,eBP */
- case 0xBE: /* MOV imm,eSI */
- case 0xBF: /* MOV imm,eDI */
- d32 = getUDisp(sz,eip); eip += sz;
- t1 = newTemp(cb);
- uInstr2(cb, MOV, sz, Literal, 0, TempReg, t1);
- uLiteral(cb, d32);
- uInstr2(cb, PUT, sz, TempReg, t1, ArchReg, opc-0xB8);
- DIP("mov%c $0x%x,%s\n", nameISize(sz), d32, nameIReg(sz,opc-0xB8));
- break;
-
- case 0xC6: /* MOV Ib,Eb */
- sz = 1;
- goto do_Mov_I_E;
- case 0xC7: /* MOV Iv,Ev */
- goto do_Mov_I_E;
-
- do_Mov_I_E:
- modrm = getUChar(eip);
- if (epartIsReg(modrm)) {
- eip++; /* mod/rm byte */
- d32 = getUDisp(sz,eip); eip += sz;
- t1 = newTemp(cb);
- uInstr2(cb, MOV, sz, Literal, 0, TempReg, t1);
- uLiteral(cb, d32);
- uInstr2(cb, PUT, sz, TempReg, t1, ArchReg, eregOfRM(modrm));
- DIP("mov%c $0x%x, %s\n", nameISize(sz), d32,
- nameIReg(sz,eregOfRM(modrm)));
- } else {
- pair = disAMode ( cb, sorb, eip, dis_buf );
- eip += HI8(pair);
- d32 = getUDisp(sz,eip); eip += sz;
- t1 = newTemp(cb);
- t2 = LOW24(pair);
- uInstr2(cb, MOV, sz, Literal, 0, TempReg, t1);
- uLiteral(cb, d32);
- uInstr2(cb, STORE, sz, TempReg, t1, TempReg, t2);
- DIP("mov%c $0x%x, %s\n", nameISize(sz), d32, dis_buf);
- }
- break;
-
- /* ------------------------ opl imm, A ----------------- */
-
- case 0x04: /* ADD Ib, AL */
- eip = dis_op_imm_A(cb, 1, ADD, True, eip, "add" );
- break;
- case 0x05: /* ADD Iv, eAX */
- eip = dis_op_imm_A(cb, sz, ADD, True, eip, "add" );
- break;
-
- case 0x0C: /* OR Ib, AL */
- eip = dis_op_imm_A(cb, 1, OR, True, eip, "or" );
- break;
- case 0x0D: /* OR Iv, eAX */
- eip = dis_op_imm_A(cb, sz, OR, True, eip, "or" );
- break;
-
- case 0x14: /* ADC Ib, AL */
- eip = dis_op_imm_A(cb, 1, ADC, True, eip, "adc" );
- break;
- case 0x15: /* ADC Iv, eAX */
- eip = dis_op_imm_A(cb, sz, ADC, True, eip, "adc" );
- break;
-
- case 0x1C: /* SBB Ib, AL */
- eip = dis_op_imm_A(cb, 1, SBB, True, eip, "sbb" );
- break;
- case 0x1D: /* SBB Iv, eAX */
- eip = dis_op_imm_A(cb, sz, SBB, True, eip, "sbb" );
- break;
-
- case 0x24: /* AND Ib, AL */
- eip = dis_op_imm_A(cb, 1, AND, True, eip, "and" );
- break;
- case 0x25: /* AND Iv, eAX */
- eip = dis_op_imm_A(cb, sz, AND, True, eip, "and" );
- break;
-
- case 0x2C: /* SUB Ib, AL */
- eip = dis_op_imm_A(cb, 1, SUB, True, eip, "sub" );
- break;
- case 0x2D: /* SUB Iv, eAX */
- eip = dis_op_imm_A(cb, sz, SUB, True, eip, "sub" );
- break;
-
- case 0x34: /* XOR Ib, AL */
- eip = dis_op_imm_A(cb, 1, XOR, True, eip, "xor" );
- break;
- case 0x35: /* XOR Iv, eAX */
- eip = dis_op_imm_A(cb, sz, XOR, True, eip, "xor" );
- break;
-
- case 0x3C: /* CMP Ib, AL */
- eip = dis_op_imm_A(cb, 1, SUB, False, eip, "cmp" );
- break;
- case 0x3D: /* CMP Iv, eAX */
- eip = dis_op_imm_A(cb, sz, SUB, False, eip, "cmp" );
- break;
-
- case 0xA8: /* TEST Ib, AL */
- eip = dis_op_imm_A(cb, 1, AND, False, eip, "test" );
- break;
- case 0xA9: /* TEST Iv, eAX */
- eip = dis_op_imm_A(cb, sz, AND, False, eip, "test" );
- break;
-
- /* ------------------------ opl Ev, Gv ----------------- */
-
- case 0x02: /* ADD Eb,Gb */
- eip = dis_op2_E_G ( cb, sorb, ADD, True, 1, eip, "add" );
- break;
- case 0x03: /* ADD Ev,Gv */
- eip = dis_op2_E_G ( cb, sorb, ADD, True, sz, eip, "add" );
- break;
-
- case 0x0A: /* OR Eb,Gb */
- eip = dis_op2_E_G ( cb, sorb, OR, True, 1, eip, "or" );
- break;
- case 0x0B: /* OR Ev,Gv */
- eip = dis_op2_E_G ( cb, sorb, OR, True, sz, eip, "or" );
- break;
-
- case 0x12: /* ADC Eb,Gb */
- eip = dis_op2_E_G ( cb, sorb, ADC, True, 1, eip, "adc" );
- break;
- case 0x13: /* ADC Ev,Gv */
- eip = dis_op2_E_G ( cb, sorb, ADC, True, sz, eip, "adc" );
- break;
-
- case 0x1A: /* SBB Eb,Gb */
- eip = dis_op2_E_G ( cb, sorb, SBB, True, 1, eip, "sbb" );
- break;
- case 0x1B: /* SBB Ev,Gv */
- eip = dis_op2_E_G ( cb, sorb, SBB, True, sz, eip, "sbb" );
- break;
-
- case 0x22: /* AND Eb,Gb */
- eip = dis_op2_E_G ( cb, sorb, AND, True, 1, eip, "and" );
- break;
- case 0x23: /* AND Ev,Gv */
- eip = dis_op2_E_G ( cb, sorb, AND, True, sz, eip, "and" );
- break;
-
- case 0x2A: /* SUB Eb,Gb */
- eip = dis_op2_E_G ( cb, sorb, SUB, True, 1, eip, "sub" );
- break;
- case 0x2B: /* SUB Ev,Gv */
- eip = dis_op2_E_G ( cb, sorb, SUB, True, sz, eip, "sub" );
- break;
-
- case 0x32: /* XOR Eb,Gb */
- eip = dis_op2_E_G ( cb, sorb, XOR, True, 1, eip, "xor" );
- break;
- case 0x33: /* XOR Ev,Gv */
- eip = dis_op2_E_G ( cb, sorb, XOR, True, sz, eip, "xor" );
- break;
-
- case 0x3A: /* CMP Eb,Gb */
- eip = dis_op2_E_G ( cb, sorb, SUB, False, 1, eip, "cmp" );
- break;
- case 0x3B: /* CMP Ev,Gv */
- eip = dis_op2_E_G ( cb, sorb, SUB, False, sz, eip, "cmp" );
- break;
-
- case 0x84: /* TEST Eb,Gb */
- eip = dis_op2_E_G ( cb, sorb, AND, False, 1, eip, "test" );
- break;
- case 0x85: /* TEST Ev,Gv */
- eip = dis_op2_E_G ( cb, sorb, AND, False, sz, eip, "test" );
- break;
-
- /* ------------------------ opl Gv, Ev ----------------- */
-
- case 0x00: /* ADD Gb,Eb */
- eip = dis_op2_G_E ( cb, sorb, ADD, True, 1, eip, "add" );
- break;
- case 0x01: /* ADD Gv,Ev */
- eip = dis_op2_G_E ( cb, sorb, ADD, True, sz, eip, "add" );
- break;
-
- case 0x08: /* OR Gb,Eb */
- eip = dis_op2_G_E ( cb, sorb, OR, True, 1, eip, "or" );
- break;
- case 0x09: /* OR Gv,Ev */
- eip = dis_op2_G_E ( cb, sorb, OR, True, sz, eip, "or" );
- break;
-
- case 0x10: /* ADC Gb,Eb */
- eip = dis_op2_G_E ( cb, sorb, ADC, True, 1, eip, "adc" );
- break;
- case 0x11: /* ADC Gv,Ev */
- eip = dis_op2_G_E ( cb, sorb, ADC, True, sz, eip, "adc" );
- break;
-
- case 0x18: /* SBB Gb,Eb */
- eip = dis_op2_G_E ( cb, sorb, SBB, True, 1, eip, "sbb" );
- break;
- case 0x19: /* SBB Gv,Ev */
- eip = dis_op2_G_E ( cb, sorb, SBB, True, sz, eip, "sbb" );
- break;
-
- case 0x20: /* AND Gb,Eb */
- eip = dis_op2_G_E ( cb, sorb, AND, True, 1, eip, "and" );
- break;
- case 0x21: /* AND Gv,Ev */
- eip = dis_op2_G_E ( cb, sorb, AND, True, sz, eip, "and" );
- break;
-
- case 0x28: /* SUB Gb,Eb */
- eip = dis_op2_G_E ( cb, sorb, SUB, True, 1, eip, "sub" );
- break;
- case 0x29: /* SUB Gv,Ev */
- eip = dis_op2_G_E ( cb, sorb, SUB, True, sz, eip, "sub" );
- break;
-
- case 0x30: /* XOR Gb,Eb */
- eip = dis_op2_G_E ( cb, sorb, XOR, True, 1, eip, "xor" );
- break;
- case 0x31: /* XOR Gv,Ev */
- eip = dis_op2_G_E ( cb, sorb, XOR, True, sz, eip, "xor" );
- break;
-
- case 0x38: /* CMP Gb,Eb */
- eip = dis_op2_G_E ( cb, sorb, SUB, False, 1, eip, "cmp" );
- break;
- case 0x39: /* CMP Gv,Ev */
- eip = dis_op2_G_E ( cb, sorb, SUB, False, sz, eip, "cmp" );
- break;
-
- /* ------------------------ POP ------------------------ */
-
- case 0x58: /* POP eAX */
- case 0x59: /* POP eCX */
- case 0x5A: /* POP eDX */
- case 0x5B: /* POP eBX */
- case 0x5D: /* POP eBP */
- case 0x5E: /* POP eSI */
- case 0x5F: /* POP eDI */
- case 0x5C: /* POP eSP */
- t1 = newTemp(cb); t2 = newTemp(cb);
- uInstr2(cb, GET, 4, ArchReg, R_ESP, TempReg, t2);
- uInstr2(cb, LOAD, sz, TempReg, t2, TempReg, t1);
- uInstr2(cb, ADD, 4, Literal, 0, TempReg, t2);
- uLiteral(cb, sz);
- uInstr2(cb, PUT, 4, TempReg, t2, ArchReg, R_ESP);
- uInstr2(cb, PUT, sz, TempReg, t1, ArchReg, opc-0x58);
- DIP("pop%c %s\n", nameISize(sz), nameIReg(sz,opc-0x58));
- break;
-
- case 0x9D: /* POPF */
- vg_assert(sz == 2 || sz == 4);
- t1 = newTemp(cb); t2 = newTemp(cb);
- uInstr2(cb, GET, 4, ArchReg, R_ESP, TempReg, t2);
- uInstr2(cb, LOAD, sz, TempReg, t2, TempReg, t1);
- uInstr2(cb, ADD, 4, Literal, 0, TempReg, t2);
- uLiteral(cb, sz);
- uInstr2(cb, PUT, 4, TempReg, t2, ArchReg, R_ESP);
- uInstr1(cb, PUTF, sz, TempReg, t1);
- /* PUTF writes all the flags we are interested in */
- uFlagsRWU(cb, FlagsEmpty, FlagsALL, FlagsEmpty);
- DIP("popf%c\n", nameISize(sz));
- break;
-
- case 0x61: /* POPA */
- { Int reg;
- /* Just to keep things sane, we assert for a size 4. It's
- probably OK for size 2 as well, but I'd like to find a test
- case; ie, have the assertion fail, before committing to it.
- If it fails for you, uncomment the sz == 2 bit, try again,
- and let me know whether or not it works. (jseward@acm.org). */
- vg_assert(sz == 4 /* || sz == 2 */);
-
- /* Eight values are popped, one per register, but the value of
- %esp on the stack is ignored and instead incremented (in one
- hit at the end) for each of the values. */
- t1 = newTemp(cb); t2 = newTemp(cb); t3 = newTemp(cb);
- uInstr2(cb, GET, 4, ArchReg, R_ESP, TempReg, t2);
- uInstr2(cb, MOV, 4, TempReg, t2, TempReg, t3);
-
- /* Do %edi, %esi, %ebp */
- for (reg = 7; reg >= 5; reg--) {
- uInstr2(cb, LOAD, sz, TempReg, t2, TempReg, t1);
- uInstr2(cb, ADD, 4, Literal, 0, TempReg, t2);
- uLiteral(cb, sz);
- uInstr2(cb, PUT, sz, TempReg, t1, ArchReg, reg);
- }
- /* Ignore (skip) value of %esp on stack. */
- uInstr2(cb, ADD, 4, Literal, 0, TempReg, t2);
- uLiteral(cb, sz);
- /* Do %ebx, %edx, %ecx, %eax */
- for (reg = 3; reg >= 0; reg--) {
- uInstr2(cb, LOAD, sz, TempReg, t2, TempReg, t1);
- uInstr2(cb, ADD, 4, Literal, 0, TempReg, t2);
- uLiteral(cb, sz);
- uInstr2(cb, PUT, sz, TempReg, t1, ArchReg, reg);
- }
- uInstr2(cb, ADD, 4, Literal, 0, TempReg, t3);
- uLiteral(cb, sz * 8); /* One 'sz' per register */
- uInstr2(cb, PUT, 4, TempReg, t3, ArchReg, R_ESP);
- DIP("popa%c\n", nameISize(sz));
- break;
- }
-
- case 0x8F: /* POPL/POPW m32 */
- { UInt pair1;
- Int tmpa;
- UChar rm = getUChar(eip);
-
- /* make sure this instruction is correct POP */
- vg_assert(!epartIsReg(rm) && (gregOfRM(rm) == 0));
- /* and has correct size */
- vg_assert(sz == 4);
-
- t1 = newTemp(cb); t3 = newTemp(cb);
- /* set t1 to ESP: t1 = ESP */
- uInstr2(cb, GET, 4, ArchReg, R_ESP, TempReg, t1);
- /* load M[ESP] to virtual register t3: t3 = M[t1] */
- uInstr2(cb, LOAD, 4, TempReg, t1, TempReg, t3);
-
- /* increase ESP; must be done before the STORE. Intel manual says:
- If the ESP register is used as a base register for addressing
- a destination operand in memory, the POP instruction computes
- the effective address of the operand after it increments the
- ESP register.
- */
- uInstr2(cb, ADD, 4, Literal, 0, TempReg, t1);
- uLiteral(cb, sz);
- uInstr2(cb, PUT, 4, TempReg, t1, ArchReg, R_ESP);
-
- /* resolve MODR/M */
- pair1 = disAMode ( cb, sorb, eip, dis_buf );
-
- tmpa = LOW24(pair1);
- /* uInstr2(cb, LOAD, sz, TempReg, tmpa, TempReg, tmpa); */
- /* store value from stack in memory, M[m32] = t3 */
- uInstr2(cb, STORE, 4, TempReg, t3, TempReg, tmpa);
-
- DIP("popl %s\n", dis_buf);
-
- eip += HI8(pair1);
- break;
- }
-
- case 0x1F: /* POP %DS */
- dis_pop_segreg( cb, R_DS, sz ); break;
- case 0x07: /* POP %ES */
- dis_pop_segreg( cb, R_ES, sz ); break;
- case 0x17: /* POP %SS */
- dis_pop_segreg( cb, R_SS, sz ); break;
-
- /* ------------------------ PUSH ----------------------- */
-
- case 0x50: /* PUSH eAX */
- case 0x51: /* PUSH eCX */
- case 0x52: /* PUSH eDX */
- case 0x53: /* PUSH eBX */
- case 0x55: /* PUSH eBP */
- case 0x56: /* PUSH eSI */
- case 0x57: /* PUSH eDI */
- case 0x54: /* PUSH eSP */
- /* This is the Right Way, in that the value to be pushed is
- established before %esp is changed, so that pushl %esp
- correctly pushes the old value. */
- t1 = newTemp(cb); t2 = newTemp(cb); t3 = newTemp(cb);
- uInstr2(cb, GET, sz, ArchReg, opc-0x50, TempReg, t1);
- uInstr2(cb, GET, 4, ArchReg, R_ESP, TempReg, t3);
- uInstr2(cb, MOV, 4, TempReg, t3, TempReg, t2);
- uInstr2(cb, SUB, 4, Literal, 0, TempReg, t2);
- uLiteral(cb, sz);
- uInstr2(cb, PUT, 4, TempReg, t2, ArchReg, R_ESP);
- uInstr2(cb, STORE, sz, TempReg, t1, TempReg, t2);
- DIP("push%c %s\n", nameISize(sz), nameIReg(sz,opc-0x50));
- break;
-
- case 0x68: /* PUSH Iv */
- d32 = getUDisp(sz,eip); eip += sz;
- goto do_push_I;
- case 0x6A: /* PUSH Ib, sign-extended to sz */
- d32 = getSDisp8(eip); eip += 1;
- goto do_push_I;
- do_push_I:
- t1 = newTemp(cb); t2 = newTemp(cb);
- uInstr2(cb, GET, 4, ArchReg, R_ESP, TempReg, t1);
- uInstr2(cb, SUB, 4, Literal, 0, TempReg, t1);
- uLiteral(cb, sz);
- uInstr2(cb, PUT, 4, TempReg, t1, ArchReg, R_ESP);
- uInstr2(cb, MOV, sz, Literal, 0, TempReg, t2);
- uLiteral(cb, d32);
- uInstr2(cb, STORE, sz, TempReg, t2, TempReg, t1);
- DIP("push%c $0x%x\n", nameISize(sz), d32);
- break;
-
- case 0x9C: /* PUSHF */
- vg_assert(sz == 2 || sz == 4);
- t1 = newTemp(cb); t2 = newTemp(cb); t3 = newTemp(cb);
- uInstr1(cb, GETF, sz, TempReg, t1);
- /* GETF reads all the flags we are interested in */
- uFlagsRWU(cb, FlagsALL, FlagsEmpty, FlagsEmpty);
- uInstr2(cb, GET, 4, ArchReg, R_ESP, TempReg, t3);
- uInstr2(cb, MOV, 4, TempReg, t3, TempReg, t2);
- uInstr2(cb, SUB, 4, Literal, 0, TempReg, t2);
- uLiteral(cb, sz);
- uInstr2(cb, PUT, 4, TempReg, t2, ArchReg, R_ESP);
- uInstr2(cb, STORE, sz, TempReg, t1, TempReg, t2);
- DIP("pushf%c\n", nameISize(sz));
- break;
-
- case 0x60: /* PUSHA */
- { Int reg;
- /* Just to keep things sane, we assert for a size 4. It's
- probably OK for size 2 as well, but I'd like to find a test
- case; ie, have the assertion fail, before committing to it.
- If it fails for you, uncomment the sz == 2 bit, try again,
- and let me know whether or not it works. (jseward@acm.org). */
- vg_assert(sz == 4 /* || sz == 2 */);
-
- /* This is the Right Way, in that the value to be pushed is
- established before %esp is changed, so that pusha
- correctly pushes the old %esp value. New value of %esp is
- pushed at start. */
- t1 = newTemp(cb); t2 = newTemp(cb); t3 = newTemp(cb);
- t4 = newTemp(cb);
- uInstr2(cb, GET, 4, ArchReg, R_ESP, TempReg, t3);
- uInstr2(cb, MOV, 4, TempReg, t3, TempReg, t2);
- uInstr2(cb, MOV, 4, TempReg, t3, TempReg, t4);
- uInstr2(cb, SUB, 4, Literal, 0, TempReg, t4);
- uLiteral(cb, sz * 8); /* One 'sz' per register. */
- uInstr2(cb, PUT, 4, TempReg, t4, ArchReg, R_ESP);
- /* Do %eax, %ecx, %edx, %ebx */
- for (reg = 0; reg <= 3; reg++) {
- uInstr2(cb, GET, sz, ArchReg, reg, TempReg, t1);
- uInstr2(cb, SUB, 4, Literal, 0, TempReg, t2);
- uLiteral(cb, sz);
- uInstr2(cb, STORE, sz, TempReg, t1, TempReg, t2);
- }
- /* Push old value of %esp */
- uInstr2(cb, SUB, 4, Literal, 0, TempReg, t2);
- uLiteral(cb, sz);
- uInstr2(cb, STORE, sz, TempReg, t3, TempReg, t2);
- /* Do %ebp, %esi, %edi */
- for (reg = 5; reg <= 7; reg++) {
- uInstr2(cb, GET, sz, ArchReg, reg, TempReg, t1);
- uInstr2(cb, SUB, 4, Literal, 0, TempReg, t2);
- uLiteral(cb, sz);
- uInstr2(cb, STORE, sz, TempReg, t1, TempReg, t2);
- }
- DIP("pusha%c\n", nameISize(sz));
- break;
- }
-
- case 0x0E: /* PUSH %CS */
- dis_push_segreg( cb, R_CS, sz ); break;
- case 0x1E: /* PUSH %DS */
- dis_push_segreg( cb, R_DS, sz ); break;
- case 0x06: /* PUSH %ES */
- dis_push_segreg( cb, R_ES, sz ); break;
- case 0x16: /* PUSH %SS */
- dis_push_segreg( cb, R_SS, sz ); break;
-
- /* ------------------------ SCAS et al ----------------- */
-
- case 0xA4: /* MOVS, no REP prefix */
- case 0xA5:
- dis_string_op( cb, dis_MOVS, ( opc == 0xA4 ? 1 : sz ), "movs", sorb );
- break;
-
- case 0xA6: /* CMPSb, no REP prefix */
- case 0xA7:
- dis_string_op( cb, dis_CMPS, ( opc == 0xA6 ? 1 : sz ), "cmps", sorb );
- break;
-
- case 0xAA: /* STOS, no REP prefix */
- case 0xAB:
- dis_string_op( cb, dis_STOS, ( opc == 0xAA ? 1 : sz ), "stos", sorb );
- break;
-
- case 0xAC: /* LODS, no REP prefix */
- case 0xAD:
- dis_string_op( cb, dis_LODS, ( opc == 0xAC ? 1 : sz ), "lods", sorb );
- break;
-
- case 0xAE: /* SCAS, no REP prefix */
- case 0xAF:
- dis_string_op( cb, dis_SCAS, ( opc == 0xAE ? 1 : sz ), "scas", sorb );
- break;
-
-
- case 0xFC: /* CLD */
- uInstr0(cb, CALLM_S, 0);
- uInstr1(cb, CALLM, 0, Lit16, VGOFF_(helper_CLD));
- uFlagsRWU(cb, FlagsEmpty, FlagD, FlagsEmpty);
- uInstr0(cb, CALLM_E, 0);
- DIP("cld\n");
- break;
-
- case 0xFD: /* STD */
- uInstr0(cb, CALLM_S, 0);
- uInstr1(cb, CALLM, 0, Lit16, VGOFF_(helper_STD));
- uFlagsRWU(cb, FlagsEmpty, FlagD, FlagsEmpty);
- uInstr0(cb, CALLM_E, 0);
- DIP("std\n");
- break;
-
- case 0xF8: /* CLC */
- uInstr0(cb, CALLM_S, 0);
- uInstr1(cb, CALLM, 0, Lit16, VGOFF_(helper_CLC));
- uFlagsRWU(cb, FlagsEmpty, FlagC, FlagsOSZAP);
- uInstr0(cb, CALLM_E, 0);
- DIP("clc\n");
- break;
-
- case 0xF9: /* STC */
- uInstr0(cb, CALLM_S, 0);
- uInstr1(cb, CALLM, 0, Lit16, VGOFF_(helper_STC));
- uFlagsRWU(cb, FlagsEmpty, FlagC, FlagsOSZAP);
- uInstr0(cb, CALLM_E, 0);
- DIP("stc\n");
- break;
-
- case 0xF5: /* CMC */
- uInstr0(cb, CALLM_S, 0);
- uInstr1(cb, CALLM, 0, Lit16, VGOFF_(helper_CMC));
- uFlagsRWU(cb, FlagC, FlagC, FlagsOSZAP);
- uInstr0(cb, CALLM_E, 0);
- DIP("cmc\n");
- break;
-
- /* REPNE prefix insn */
- case 0xF2: {
- Addr eip_orig = eip - 1;
- vg_assert(sorb == 0);
- abyte = getUChar(eip); eip++;
-
- if (abyte == 0x66) { sz = 2; abyte = getUChar(eip); eip++; }
- *isEnd = True;
-
- switch (abyte) {
- /* According to the Intel manual, "repne movs" should never occur, but
- * in practice it has happened, so allow for it here... */
- case 0xA4: sz = 1; /* REPNE MOVS<sz> */
- case 0xA5:
- dis_REP_op ( cb, CondNZ, dis_MOVS, sz, eip_orig, eip, "repne movs" );
- break;
-
- case 0xA6: sz = 1; /* REPNE CMPS<sz> */
- case 0xA7:
- dis_REP_op ( cb, CondNZ, dis_CMPS, sz, eip_orig, eip, "repne cmps" );
- break;
-
- case 0xAE: sz = 1; /* REPNE SCAS<sz> */
- case 0xAF:
- dis_REP_op ( cb, CondNZ, dis_SCAS, sz, eip_orig, eip, "repne scas" );
- break;
-
- default:
- goto decode_failure;
- }
- break;
- }
-
- /* REP/REPE prefix insn (for SCAS and CMPS, 0xF3 means REPE,
- for the rest, it means REP) */
- case 0xF3: {
- Addr eip_orig = eip - 1;
- vg_assert(sorb == 0);
- abyte = getUChar(eip); eip++;
-
- if (abyte == 0x66) { sz = 2; abyte = getUChar(eip); eip++; }
- *isEnd = True;
-
- switch (abyte) {
- case 0xA4: sz = 1; /* REP MOVS<sz> */
- case 0xA5:
- dis_REP_op ( cb, CondAlways, dis_MOVS, sz, eip_orig, eip, "rep movs" );
- break;
-
- case 0xA6: sz = 1; /* REPE CMP<sz> */
- case 0xA7:
- dis_REP_op ( cb, CondZ, dis_CMPS, sz, eip_orig, eip, "repe cmps" );
- break;
-
- case 0xAA: sz = 1; /* REP STOS<sz> */
- case 0XAB:
- dis_REP_op ( cb, CondAlways, dis_STOS, sz, eip_orig, eip, "rep stos" );
- break;
-
- case 0xAE: sz = 1; /* REPE SCAS<sz> */
- case 0xAF:
- dis_REP_op ( cb, CondZ, dis_SCAS, sz, eip_orig, eip, "repe scas" );
- break;
-
- case 0x90: /* REP NOP (PAUSE) */
- /* a hint to the P4 re spin-wait loop */
- DIP("rep nop (P4 pause)\n");
- jmp_lit(cb, eip);
- LAST_UINSTR(cb).jmpkind = JmpYield;
- break;
-
- case 0xC3: /* REP RET */
- /* AMD K7/K8-specific optimisation; faster than vanilla RET */
- dis_ret(cb, 0);
- DIP("rep ret\n");
- break;
-
- default:
- goto decode_failure;
- }
- break;
- }
-
- /* ------------------------ XCHG ----------------------- */
-
- case 0x86: /* XCHG Gb,Eb */
- sz = 1;
- /* Fall through ... */
- case 0x87: /* XCHG Gv,Ev */
- modrm = getUChar(eip);
- t1 = newTemp(cb); t2 = newTemp(cb);
- if (epartIsReg(modrm)) {
- uInstr2(cb, GET, sz, ArchReg, eregOfRM(modrm), TempReg, t1);
- uInstr2(cb, GET, sz, ArchReg, gregOfRM(modrm), TempReg, t2);
- uInstr2(cb, PUT, sz, TempReg, t1, ArchReg, gregOfRM(modrm));
- uInstr2(cb, PUT, sz, TempReg, t2, ArchReg, eregOfRM(modrm));
- eip++;
- DIP("xchg%c %s, %s\n",
- nameISize(sz), nameIReg(sz,gregOfRM(modrm)),
- nameIReg(sz,eregOfRM(modrm)));
- } else {
- pair = disAMode ( cb, sorb, eip, dis_buf );
- t3 = LOW24(pair);
- uInstr2(cb, LOAD, sz, TempReg, t3, TempReg, t1);
- uInstr2(cb, GET, sz, ArchReg, gregOfRM(modrm), TempReg, t2);
- uInstr2(cb, STORE, sz, TempReg, t2, TempReg, t3);
- uInstr2(cb, PUT, sz, TempReg, t1, ArchReg, gregOfRM(modrm));
- eip += HI8(pair);
- DIP("xchg%c %s, %s\n", nameISize(sz),
- nameIReg(sz,gregOfRM(modrm)), dis_buf);
- }
- break;
-
- case 0x90: /* XCHG eAX,eAX */
- DIP("nop\n");
- break;
- case 0x91: /* XCHG eAX,eCX */
- case 0x92: /* XCHG eAX,eDX */
- case 0x93: /* XCHG eAX,eBX */
- case 0x94: /* XCHG eAX,eSP */
- case 0x95: /* XCHG eAX,eBP */
- case 0x96: /* XCHG eAX,eSI */
- case 0x97: /* XCHG eAX,eDI */
- codegen_xchg_eAX_Reg ( cb, sz, opc - 0x90 );
- break;
-
- /* ------------------------ XLAT ----------------------- */
-
- case 0xD7: /* XLAT */
- t1 = newTemp(cb); t2 = newTemp(cb);
- uInstr2(cb, GET, sz, ArchReg, R_EBX, TempReg, t1); /* get eBX */
- handleSegOverride( cb, sorb, t1 ); /* make t1 DS:eBX */
- uInstr2(cb, GET, 1, ArchReg, R_AL, TempReg, t2); /* get AL */
- /* Widen %AL to 32 bits, so it's all defined when we add it. */
- uInstr1(cb, WIDEN, 4, TempReg, t2);
- uWiden(cb, 1, False);
- uInstr2(cb, ADD, sz, TempReg, t2, TempReg, t1); /* add AL to eBX */
- uInstr2(cb, LOAD, 1, TempReg, t1, TempReg, t2); /* get byte at t1 into t2 */
- uInstr2(cb, PUT, 1, TempReg, t2, ArchReg, R_AL); /* put byte into AL */
-
- DIP("xlat%c [ebx]\n", nameISize(sz));
- break;
-
- /* ------------------------ IN / OUT ----------------------- */
-
- case 0xE4: /* IN ib, %al */
- case 0xE5: /* IN ib, %{e}ax */
- case 0xEC: /* IN (%dx),%al */
- case 0xED: /* IN (%dx),%{e}ax */
- t1 = newTemp(cb);
- t2 = newTemp(cb);
- t3 = newTemp(cb);
-
- uInstr0(cb, CALLM_S, 0);
- /* operand size? */
- uInstr2(cb, MOV, 4, Literal, 0, TempReg, t1);
- uLiteral(cb, ( opc == 0xE4 || opc == 0xEC ) ? 1 : sz);
- uInstr1(cb, PUSH, 4, TempReg, t1);
- /* port number ? */
- if ( opc == 0xE4 || opc == 0xE5 ) {
- abyte = getUChar(eip); eip++;
- uInstr2(cb, MOV, 4, Literal, 0, TempReg, t2);
- uLiteral(cb, abyte);
- }
- else
- uInstr2(cb, GET, 4, ArchReg, R_EDX, TempReg, t2);
-
- uInstr1(cb, PUSH, 4, TempReg, t2);
- uInstr1(cb, CALLM, 0, Lit16, VGOFF_(helper_IN));
- uFlagsRWU(cb, FlagsEmpty, FlagsEmpty, FlagsEmpty);
- uInstr1(cb, POP, 4, TempReg, t2);
- uInstr1(cb, CLEAR, 0, Lit16, 4);
- uInstr0(cb, CALLM_E, 0);
- uInstr2(cb, PUT, 4, TempReg, t2, ArchReg, R_EAX);
- if ( opc == 0xE4 || opc == 0xE5 ) {
- DIP("in 0x%x, %%eax/%%ax/%%al\n", getUChar(eip-1) );
- } else {
- DIP("in (%%dx), %%eax/%%ax/%%al\n");
- }
- break;
- case 0xE6: /* OUT %al,ib */
- case 0xE7: /* OUT %{e}ax,ib */
- case 0xEE: /* OUT %al,(%dx) */
- case 0xEF: /* OUT %{e}ax,(%dx) */
- t1 = newTemp(cb);
- t2 = newTemp(cb);
- t3 = newTemp(cb);
-
- uInstr0(cb, CALLM_S, 0);
- /* operand size? */
- uInstr2(cb, MOV, 4, Literal, 0, TempReg, t1);
- uLiteral(cb, ( opc == 0xE6 || opc == 0xEE ) ? 1 : sz);
- uInstr1(cb, PUSH, 4, TempReg, t1);
- /* port number ? */
- if ( opc == 0xE6 || opc == 0xE7 ) {
- abyte = getUChar(eip); eip++;
- uInstr2(cb, MOV, 4, Literal, 0, TempReg, t2);
- uLiteral(cb, abyte);
- }
- else
- uInstr2(cb, GET, 4, ArchReg, R_EDX, TempReg, t2);
- uInstr1(cb, PUSH, 4, TempReg, t2);
- uInstr2(cb, GET, 4, ArchReg, R_EAX, TempReg, t3);
- uInstr1(cb, PUSH, 4, TempReg, t3);
- uInstr1(cb, CALLM, 0, Lit16, VGOFF_(helper_OUT));
- uFlagsRWU(cb, FlagsEmpty, FlagsEmpty, FlagsEmpty);
- uInstr1(cb, CLEAR, 0, Lit16, 12);
- uInstr0(cb, CALLM_E, 0);
- if ( opc == 0xE4 || opc == 0xE5 ) {
- DIP("out %%eax/%%ax/%%al, 0x%x\n", getUChar(eip-1) );
- } else {
- DIP("out %%eax/%%ax/%%al, (%%dx)\n");
- }
- break;
-
- /* ------------------------ (Grp1 extensions) ---------- */
-
- case 0x80: /* Grp1 Ib,Eb */
- modrm = getUChar(eip);
- am_sz = lengthAMode(eip);
- sz = 1;
- d_sz = 1;
- d32 = getSDisp8(eip + am_sz);
- eip = dis_Grp1 ( cb, sorb, eip, modrm, am_sz, d_sz, sz, d32 );
- break;
-
- case 0x81: /* Grp1 Iv,Ev */
- modrm = getUChar(eip);
- am_sz = lengthAMode(eip);
- d_sz = sz;
- d32 = getUDisp(d_sz, eip + am_sz);
- eip = dis_Grp1 ( cb, sorb, eip, modrm, am_sz, d_sz, sz, d32 );
- break;
-
- case 0x83: /* Grp1 Ib,Ev */
- modrm = getUChar(eip);
- am_sz = lengthAMode(eip);
- d_sz = 1;
- d32 = getSDisp8(eip + am_sz);
- eip = dis_Grp1 ( cb, sorb, eip, modrm, am_sz, d_sz, sz, d32 );
- break;
-
- /* ------------------------ (Grp2 extensions) ---------- */
-
- case 0xC0: /* Grp2 Ib,Eb */
- modrm = getUChar(eip);
- am_sz = lengthAMode(eip);
- d_sz = 1;
- d32 = getSDisp8(eip + am_sz);
- sz = 1;
- eip = dis_Grp2 ( cb, sorb, eip, modrm, am_sz, d_sz, sz, Literal, d32 );
- break;
-
- case 0xC1: /* Grp2 Ib,Ev */
- modrm = getUChar(eip);
- am_sz = lengthAMode(eip);
- d_sz = 1;
- d32 = getSDisp8(eip + am_sz);
- eip = dis_Grp2 ( cb, sorb, eip, modrm, am_sz, d_sz, sz, Literal, d32 );
- break;
-
- case 0xD0: /* Grp2 1,Eb */
- modrm = getUChar(eip);
- am_sz = lengthAMode(eip);
- d_sz = 0;
- d32 = 1;
- sz = 1;
- eip = dis_Grp2 ( cb, sorb, eip, modrm, am_sz, d_sz, sz, Literal, d32 );
- break;
-
- case 0xD1: /* Grp2 1,Ev */
- modrm = getUChar(eip);
- am_sz = lengthAMode(eip);
- d_sz = 0;
- d32 = 1;
- eip = dis_Grp2 ( cb, sorb, eip, modrm, am_sz, d_sz, sz, Literal, d32 );
- break;
-
- case 0xD2: /* Grp2 CL,Eb */
- modrm = getUChar(eip);
- am_sz = lengthAMode(eip);
- d_sz = 0;
- sz = 1;
- eip = dis_Grp2 ( cb, sorb, eip, modrm, am_sz, d_sz, sz, ArchReg, R_ECX );
- break;
-
- case 0xD3: /* Grp2 CL,Ev */
- modrm = getUChar(eip);
- am_sz = lengthAMode(eip);
- d_sz = 0;
- eip = dis_Grp2 ( cb, sorb, eip, modrm, am_sz, d_sz, sz, ArchReg, R_ECX );
- break;
-
- /* ------------------------ (Grp3 extensions) ---------- */
-
- case 0xF6: /* Grp3 Eb */
- eip = dis_Grp3 ( cb, sorb, 1, eip );
- break;
- case 0xF7: /* Grp3 Ev */
- eip = dis_Grp3 ( cb, sorb, sz, eip );
- break;
-
- /* ------------------------ (Grp4 extensions) ---------- */
-
- case 0xFE: /* Grp4 Eb */
- eip = dis_Grp4 ( cb, sorb, eip );
- break;
-
- /* ------------------------ (Grp5 extensions) ---------- */
-
- case 0xFF: /* Grp5 Ev */
- eip = dis_Grp5 ( cb, sorb, sz, eip, isEnd );
- break;
-
- /* ------------------------ Escapes to 2-byte opcodes -- */
-
- case 0x0F: {
- opc = getUChar(eip); eip++;
- switch (opc) {
-
- /* =-=-=-=-=-=-=-=-=- Grp8 =-=-=-=-=-=-=-=-=-=-=-= */
-
- case 0xBA: /* Grp8 Ib,Ev */
- modrm = getUChar(eip);
- am_sz = lengthAMode(eip);
- d32 = getSDisp8(eip + am_sz);
- eip = dis_Grp8_BT ( cb, sorb, eip, modrm, am_sz, sz, d32 );
- break;
-
- /* =-=-=-=-=-=-=-=-=- BSF/BSR -=-=-=-=-=-=-=-=-=-= */
-
- case 0xBC: /* BSF Gv,Ev */
- eip = dis_bs_E_G ( cb, sorb, sz, eip, True );
- break;
- case 0xBD: /* BSR Gv,Ev */
- eip = dis_bs_E_G ( cb, sorb, sz, eip, False );
- break;
-
- /* =-=-=-=-=-=-=-=-=- BSWAP -=-=-=-=-=-=-=-=-=-=-= */
-
- case 0xC8: /* BSWAP %eax */
- case 0xC9:
- case 0xCA:
- case 0xCB:
- case 0xCC:
- case 0xCD:
- case 0xCE:
- case 0xCF: /* BSWAP %edi */
- /* AFAICS from the Intel docs, this only exists at size 4. */
- vg_assert(sz == 4);
- t1 = newTemp(cb);
- uInstr2(cb, GET, 4, ArchReg, opc-0xC8, TempReg, t1);
- uInstr1(cb, BSWAP, 4, TempReg, t1);
- uInstr2(cb, PUT, 4, TempReg, t1, ArchReg, opc-0xC8);
- DIP("bswapl %s\n", nameIReg(4, opc-0xC8));
- break;
-
- /* =-=-=-=-=-=-=-=-=- BT/BTS/BTR/BTC =-=-=-=-=-=-= */
-
- case 0xA3: /* BT Gv,Ev */
- eip = dis_bt_G_E ( cb, sorb, sz, eip, BtOpNone );
- break;
- case 0xB3: /* BTR Gv,Ev */
- eip = dis_bt_G_E ( cb, sorb, sz, eip, BtOpReset );
- break;
- case 0xAB: /* BTS Gv,Ev */
- eip = dis_bt_G_E ( cb, sorb, sz, eip, BtOpSet );
- break;
- case 0xBB: /* BTC Gv,Ev */
- eip = dis_bt_G_E ( cb, sorb, sz, eip, BtOpComp );
- break;
-
- /* =-=-=-=-=-=-=-=-=- CMOV =-=-=-=-=-=-=-=-=-=-=-= */
-
- case 0x40:
- case 0x41:
- case 0x42: /* CMOVBb/CMOVNAEb (cmov below) */
- case 0x43: /* CMOVNBb/CMOVAEb (cmov not below) */
- case 0x44: /* CMOVZb/CMOVEb (cmov zero) */
- case 0x45: /* CMOVNZb/CMOVNEb (cmov not zero) */
- case 0x46: /* CMOVBEb/CMOVNAb (cmov below or equal) */
- case 0x47: /* CMOVNBEb/CMOVAb (cmov not below or equal) */
- case 0x48: /* CMOVSb (cmov negative) */
- case 0x49: /* CMOVSb (cmov not negative) */
- case 0x4A: /* CMOVP (cmov parity even) */
- case 0x4B: /* CMOVNP (cmov parity odd) */
- case 0x4C: /* CMOVLb/CMOVNGEb (cmov less) */
- case 0x4D: /* CMOVGEb/CMOVNLb (cmov greater or equal) */
- case 0x4E: /* CMOVLEb/CMOVNGb (cmov less or equal) */
- case 0x4F: /* CMOVGb/CMOVNLEb (cmov greater) */
- eip = dis_cmov_E_G(cb, sorb, sz, (Condcode)(opc - 0x40), eip);
- break;
-
- /* =-=-=-=-=-=-=-=-=- CMPXCHG -=-=-=-=-=-=-=-=-=-= */
-
- case 0xB0: /* CMPXCHG Gv,Ev */
- eip = dis_cmpxchg_G_E ( cb, sorb, 1, eip );
- break;
- case 0xB1: /* CMPXCHG Gv,Ev */
- eip = dis_cmpxchg_G_E ( cb, sorb, sz, eip );
- break;
- case 0xC7: /* CMPXCHG8B Gv */
- eip = dis_cmpxchg8b ( cb, sorb, eip );
- break;
-
- /* =-=-=-=-=-=-=-=-=- CPUID -=-=-=-=-=-=-=-=-=-=-= */
-
- case 0xA2: /* CPUID */
- if (!VG_(cpu_has_feature)(VG_X86_FEAT_CPUID))
- goto decode_failure;
-
- t1 = newTemp(cb);
- t2 = newTemp(cb);
- t3 = newTemp(cb);
- t4 = newTemp(cb);
- uInstr0(cb, CALLM_S, 0);
-
- uInstr2(cb, GET, 4, ArchReg, R_EAX, TempReg, t1);
- uInstr1(cb, PUSH, 4, TempReg, t1);
-
- uInstr2(cb, MOV, 4, Literal, 0, TempReg, t2);
- uLiteral(cb, 0);
- uInstr1(cb, PUSH, 4, TempReg, t2);
-
- uInstr2(cb, MOV, 4, Literal, 0, TempReg, t3);
- uLiteral(cb, 0);
- uInstr1(cb, PUSH, 4, TempReg, t3);
-
- uInstr2(cb, MOV, 4, Literal, 0, TempReg, t4);
- uLiteral(cb, 0);
- uInstr1(cb, PUSH, 4, TempReg, t4);
-
- uInstr1(cb, CALLM, 0, Lit16, VGOFF_(helper_CPUID));
- uFlagsRWU(cb, FlagsEmpty, FlagsEmpty, FlagsEmpty);
-
- uInstr1(cb, POP, 4, TempReg, t4);
- uInstr2(cb, PUT, 4, TempReg, t4, ArchReg, R_EDX);
-
- uInstr1(cb, POP, 4, TempReg, t3);
- uInstr2(cb, PUT, 4, TempReg, t3, ArchReg, R_ECX);
-
- uInstr1(cb, POP, 4, TempReg, t2);
- uInstr2(cb, PUT, 4, TempReg, t2, ArchReg, R_EBX);
-
- uInstr1(cb, POP, 4, TempReg, t1);
- uInstr2(cb, PUT, 4, TempReg, t1, ArchReg, R_EAX);
-
- uInstr0(cb, CALLM_E, 0);
- DIP("cpuid\n");
- break;
-
- /* =-=-=-=-=-=-=-=-=- MOVZX, MOVSX =-=-=-=-=-=-=-= */
-
- case 0xB6: /* MOVZXb Eb,Gv */
- eip = dis_movx_E_G ( cb, sorb, eip, 1, 4, False );
- break;
- case 0xB7: /* MOVZXw Ew,Gv */
- eip = dis_movx_E_G ( cb, sorb, eip, 2, 4, False );
- break;
-
- case 0xBE: /* MOVSXb Eb,Gv */
- eip = dis_movx_E_G ( cb, sorb, eip, 1, 4, True );
- break;
- case 0xBF: /* MOVSXw Ew,Gv */
- eip = dis_movx_E_G ( cb, sorb, eip, 2, 4, True );
- break;
-
- /* =-=-=-=-=-=-=-=-=-=-= MOVNTI -=-=-=-=-=-=-=-=-= */
-
- case 0xC3: /* MOVNTI Gv,Ev */
- vg_assert(sz == 4);
- modrm = getUChar(eip);
- vg_assert(!epartIsReg(modrm));
- t1 = newTemp(cb);
- uInstr2(cb, GET, 4, ArchReg, gregOfRM(modrm), TempReg, t1);
- pair = disAMode ( cb, sorb, eip, dis_buf );
- t2 = LOW24(pair);
- eip += HI8(pair);
- uInstr2(cb, STORE, 4, TempReg, t1, TempReg, t2);
- DIP("movnti %s,%s\n", nameIReg(4,gregOfRM(modrm)), dis_buf);
- break;
-
- /* =-=-=-=-=-=-=-=-=- MUL/IMUL =-=-=-=-=-=-=-=-=-= */
-
- case 0xAF: /* IMUL Ev, Gv */
- eip = dis_mul_E_G ( cb, sorb, sz, eip, True );
- break;
-
- /* =-=-=-=-=-=-=-=-=- Jcond d32 -=-=-=-=-=-=-=-=-= */
- case 0x80:
- case 0x81:
- case 0x82: /* JBb/JNAEb (jump below) */
- case 0x83: /* JNBb/JAEb (jump not below) */
- case 0x84: /* JZb/JEb (jump zero) */
- case 0x85: /* JNZb/JNEb (jump not zero) */
- case 0x86: /* JBEb/JNAb (jump below or equal) */
- case 0x87: /* JNBEb/JAb (jump not below or equal) */
- case 0x88: /* JSb (jump negative) */
- case 0x89: /* JSb (jump not negative) */
- case 0x8A: /* JP (jump parity even) */
- case 0x8B: /* JNP/JPO (jump parity odd) */
- case 0x8C: /* JLb/JNGEb (jump less) */
- case 0x8D: /* JGEb/JNLb (jump greater or equal) */
- case 0x8E: /* JLEb/JNGb (jump less or equal) */
- case 0x8F: /* JGb/JNLEb (jump greater) */
- d32 = (eip+4) + getUDisp32(eip); eip += 4;
- jcc_lit(cb, d32, (Condcode)(opc - 0x80));
- jmp_lit(cb, eip);
- *isEnd = True;
- DIP("j%s-32 0x%x\n", VG_(name_UCondcode)(opc - 0x80), d32);
- break;
-
- /* =-=-=-=-=-=-=-=-=- RDTSC -=-=-=-=-=-=-=-=-=-=-= */
-
- case 0x31: /* RDTSC */
- t1 = newTemp(cb);
- t2 = newTemp(cb);
- t3 = newTemp(cb);
- uInstr0(cb, CALLM_S, 0);
- // Nb: even though these args aren't used by RDTSC_helper, need
- // them to be defined (for Memcheck). The TempRegs pushed must
- // also be distinct.
- uInstr2(cb, MOV, 4, Literal, 0, TempReg, t1);
- uLiteral(cb, 0);
- uInstr1(cb, PUSH, 4, TempReg, t1);
- uInstr2(cb, MOV, 4, Literal, 0, TempReg, t2);
- uLiteral(cb, 0);
- uInstr1(cb, PUSH, 4, TempReg, t2);
- uInstr1(cb, CALLM, 0, Lit16, VGOFF_(helper_RDTSC));
- uFlagsRWU(cb, FlagsEmpty, FlagsEmpty, FlagsEmpty);
- uInstr1(cb, POP, 4, TempReg, t3);
- uInstr2(cb, PUT, 4, TempReg, t3, ArchReg, R_EDX);
- uInstr1(cb, POP, 4, TempReg, t3);
- uInstr2(cb, PUT, 4, TempReg, t3, ArchReg, R_EAX);
- uInstr0(cb, CALLM_E, 0);
- DIP("rdtsc\n");
- break;
-
- /* =-=-=-=-=-=-=-=-=- SETcc Eb =-=-=-=-=-=-=-=-=-= */
- case 0x90:
- case 0x91:
- case 0x92: /* set-Bb/set-NAEb (jump below) */
- case 0x93: /* set-NBb/set-AEb (jump not below) */
- case 0x94: /* set-Zb/set-Eb (jump zero) */
- case 0x95: /* set-NZb/set-NEb (jump not zero) */
- case 0x96: /* set-BEb/set-NAb (jump below or equal) */
- case 0x97: /* set-NBEb/set-Ab (jump not below or equal) */
- case 0x98: /* set-Sb (jump negative) */
- case 0x99: /* set-Sb (jump not negative) */
- case 0x9A: /* set-P (jump parity even) */
- case 0x9B: /* set-NP (jump parity odd) */
- case 0x9C: /* set-Lb/set-NGEb (jump less) */
- case 0x9D: /* set-GEb/set-NLb (jump greater or equal) */
- case 0x9E: /* set-LEb/set-NGb (jump less or equal) */
- case 0x9F: /* set-Gb/set-NLEb (jump greater) */
- modrm = getUChar(eip);
- t1 = newTemp(cb);
- if (epartIsReg(modrm)) {
- eip++;
- uInstr1(cb, CC2VAL, 1, TempReg, t1);
- uCond(cb, (Condcode)(opc-0x90));
- uFlagsRWU(cb, FlagsOSZACP, FlagsEmpty, FlagsEmpty);
- uInstr2(cb, PUT, 1, TempReg, t1, ArchReg, eregOfRM(modrm));
- DIP("set%s %s\n", VG_(name_UCondcode)(opc-0x90),
- nameIReg(1,eregOfRM(modrm)));
- } else {
- pair = disAMode ( cb, sorb, eip, dis_buf );
- t2 = LOW24(pair);
- eip += HI8(pair);
- uInstr1(cb, CC2VAL, 1, TempReg, t1);
- uCond(cb, (Condcode)(opc-0x90));
- uFlagsRWU(cb, FlagsOSZACP, FlagsEmpty, FlagsEmpty);
- uInstr2(cb, STORE, 1, TempReg, t1, TempReg, t2);
- DIP("set%s %s\n", VG_(name_UCondcode)(opc-0x90), dis_buf);
- }
- break;
-
- /* =-=-=-=-=-=-=-=-=- SHLD/SHRD -=-=-=-=-=-=-=-=-= */
-
- case 0xA4: /* SHLDv imm8,Gv,Ev */
- modrm = getUChar(eip);
- eip = dis_SHLRD_Gv_Ev (
- cb, sorb, eip, modrm, sz,
- Literal, getUChar(eip + lengthAMode(eip)),
- True );
- break;
- case 0xA5: /* SHLDv %cl,Gv,Ev */
- modrm = getUChar(eip);
- eip = dis_SHLRD_Gv_Ev (
- cb, sorb, eip, modrm, sz, ArchReg, R_CL, True );
- break;
-
- case 0xAC: /* SHRDv imm8,Gv,Ev */
- modrm = getUChar(eip);
- eip = dis_SHLRD_Gv_Ev (
- cb, sorb, eip, modrm, sz,
- Literal, getUChar(eip + lengthAMode(eip)),
- False );
- break;
- case 0xAD: /* SHRDv %cl,Gv,Ev */
- modrm = getUChar(eip);
- eip = dis_SHLRD_Gv_Ev (
- cb, sorb, eip, modrm, sz, ArchReg, R_CL, False );
- break;
-
- /* =-=-=-=-=-=-=-=-=- CMPXCHG -=-=-=-=-=-=-=-=-=-= */
-
- case 0xC0: /* XADD Gb,Eb */
- eip = dis_xadd_G_E ( cb, sorb, 1, eip );
- break;
- case 0xC1: /* XADD Gv,Ev */
- eip = dis_xadd_G_E ( cb, sorb, sz, eip );
- break;
-
- /* =-=-=-=-=-=-=-=-=- MMXery =-=-=-=-=-=-=-=-=-=-= */
-
- case 0x0D: /* PREFETCH / PREFETCHW - 3Dnow!ery*/
- case 0x18: /* PREFETCHT0/PREFETCHT1/PREFETCHT2/PREFETCHNTA */
-
- vg_assert(sz == 4);
- modrm = getUChar(eip);
- if (epartIsReg(modrm)) {
- goto decode_failure;
- }
- if (gregOfRM(modrm) > 3) {
- goto decode_failure;
- }
- eip += lengthAMode(eip);
- if (VG_(print_codegen)) {
- UChar* hintstr;
- if (opc == 0x0D) {
- switch (gregOfRM(modrm)) {
- case 0: hintstr = ""; break;
- case 1: hintstr = "w"; break;
- default: goto decode_failure;
- }
- }
- else {
- switch (gregOfRM(modrm)) {
- case 0: hintstr = "nta"; break;
- case 1: hintstr = "t0"; break;
- case 2: hintstr = "t1"; break;
- case 3: hintstr = "t2"; break;
- default: goto decode_failure;
- }
- }
- VG_(printf)("prefetch%s ...\n", hintstr);
- }
- break;
-
- case 0xAE: /* SFENCE */
- vg_assert(sz == 4);
- modrm = getUChar(eip);
- if (!epartIsReg(modrm)) {
- goto decode_failure;
- }
- if (gregOfRM(modrm) != 7) {
- goto decode_failure;
- }
- eip += lengthAMode(eip);
- uInstr2(cb, SSE3, 0, /* ignore sz for internal ops */
- Lit16, (((UShort)0x0F) << 8) | (UShort)0xAE,
- Lit16, (UShort)modrm );
- DIP("sfence\n");
- break;
-
- case 0x71: case 0x72: case 0x73: {
- /* (sz==4): PSLL/PSRA/PSRL mmxreg by imm8 */
- /* (sz==2): PSLL/PSRA/PSRL xmmreg by imm8 */
- UChar byte1, byte2, byte3, subopc, mmreg;
- vg_assert(sz == 4 || sz == 2);
- byte1 = opc; /* 0x71/72/73 */
- byte2 = getUChar(eip); eip++; /* amode / sub-opcode */
- byte3 = getUChar(eip); eip++; /* imm8 */
- mmreg = byte2 & 7;
- subopc = (byte2 >> 3) & 7;
- if (subopc == 2 || subopc == 6 || subopc == 4) {
- /* 2 == 010 == SRL, 6 == 110 == SLL, 4 == 100 == SRA */
- /* ok */
- } else
- if (sz == 2 && opc == 0x73 && (subopc == 7 || subopc == 3)) {
- /* 3 == PSRLDQ, 7 == PSLLDQ */
- /* This is allowable in SSE. Because sz==2 we fall thru to
- SSE5 below. */
- } else {
- eip -= (sz==2 ? 3 : 2);
- goto decode_failure;
- }
- if (sz == 4) {
- /* The leading 0x0F is implied for MMX*, so we don't
- include it. */
- uInstr2(cb, MMX3, 0,
- Lit16, (((UShort)byte1) << 8) | ((UShort)byte2),
- Lit16, ((UShort)byte3) );
- DIP("ps%s%s $%d, %s\n",
- ( subopc == 2 ? "rl"
- : subopc == 6 ? "ll"
- : subopc == 4 ? "ra"
- : "??"),
- nameMMXGran(opc & 3), (Int)byte3, nameMMXReg(mmreg) );
- } else {
- /* Whereas we have to include it for SSE. */
- uInstr3(cb, SSE5, 0,
- Lit16, (((UShort)0x66) << 8) | ((UShort)0x0F),
- Lit16, (((UShort)byte1) << 8) | ((UShort)byte2),
- Lit16, ((UShort)byte3) );
- DIP("ps%s%s $%d, %s\n",
- ( subopc == 2 ? "rl"
- : subopc == 6 ? "ll"
- : subopc == 4 ? "ra"
- : subopc == 3 ? "(PSRLDQ)"
- : subopc == 7 ? "(PSLLDQ)"
- : "??"),
- nameMMXGran(opc & 3), (Int)byte3, nameXMMReg(mmreg) );
- }
- break;
- }
-
- case 0x77: /* EMMS */
- vg_assert(sz == 4);
- uInstr1(cb, MMX1, 0, Lit16, ((UShort)(opc)) );
- DIP("emms\n");
- break;
-
- case 0x7E: /* MOVD (src)mmxreg, (dst)ireg-or-mem */
- vg_assert(sz == 4);
- modrm = getUChar(eip);
- if (epartIsReg(modrm)) {
- eip++;
- t1 = newTemp(cb);
- uInstr2(cb, MMX2_ERegWr, 4,
- Lit16,
- (((UShort)(opc)) << 8) | ((UShort)modrm),
- TempReg, t1 );
- uInstr2(cb, PUT, 4, TempReg, t1, ArchReg, eregOfRM(modrm));
- DIP("movd %s, %s\n",
- nameMMXReg(gregOfRM(modrm)), nameIReg(4,eregOfRM(modrm)));
- } else {
- Int tmpa;
- pair = disAMode ( cb, sorb, eip, dis_buf );
- tmpa = LOW24(pair);
- eip += HI8(pair);
- uInstr2(cb, MMX2_MemWr, 4,
- Lit16,
- (((UShort)(opc)) << 8) | ((UShort)modrm),
- TempReg, tmpa);
- DIP("movd %s, %s\n", nameMMXReg(gregOfRM(modrm)), dis_buf);
- }
- break;
-
- case 0x6E: /* MOVD (src)ireg-or-mem, (dst)mmxreg */
- vg_assert(sz == 4);
- modrm = getUChar(eip);
- if (epartIsReg(modrm)) {
- eip++;
- t1 = newTemp(cb);
- uInstr2(cb, GET, 4, ArchReg, eregOfRM(modrm), TempReg, t1);
- uInstr2(cb, MMX2_ERegRd, 4,
- Lit16,
- (((UShort)(opc)) << 8) | ((UShort)modrm),
- TempReg, t1 );
- DIP("movd %s, %s\n",
- nameIReg(4,eregOfRM(modrm)), nameMMXReg(gregOfRM(modrm)));
- } else {
- Int tmpa;
- pair = disAMode ( cb, sorb, eip, dis_buf );
- tmpa = LOW24(pair);
- eip += HI8(pair);
- uInstr2(cb, MMX2_MemRd, 4,
- Lit16,
- (((UShort)(opc)) << 8) | ((UShort)modrm),
- TempReg, tmpa);
- DIP("movd %s, %s\n", dis_buf, nameMMXReg(gregOfRM(modrm)));
- }
- break;
-
- case 0x6F: /* MOVQ (src)mmxreg-or-mem, (dst)mmxreg */
- vg_assert(sz == 4);
- modrm = getUChar(eip);
- if (epartIsReg(modrm)) {
- eip++;
- uInstr1(cb, MMX2, 0,
- Lit16,
- (((UShort)(opc)) << 8) | ((UShort)modrm) );
- DIP("movq %s, %s\n",
- nameMMXReg(eregOfRM(modrm)), nameMMXReg(gregOfRM(modrm)));
- } else {
- Int tmpa;
- pair = disAMode ( cb, sorb, eip, dis_buf );
- tmpa = LOW24(pair);
- eip += HI8(pair);
- uInstr2(cb, MMX2_MemRd, 8,
- Lit16,
- (((UShort)(opc)) << 8) | ((UShort)modrm),
- TempReg, tmpa);
- DIP("movq %s, %s\n",
- dis_buf, nameMMXReg(gregOfRM(modrm)));
- }
- break;
-
- case 0x7F: /* MOVQ (src)mmxreg, (dst)mmxreg-or-mem */
- case 0xE7: /* MOVNTQ (src)mmxreg, (dst)mmxreg-or-mem */
- vg_assert(sz == 4);
- modrm = getUChar(eip);
- if (epartIsReg(modrm)) {
- eip++;
- uInstr1(cb, MMX2, 0,
- Lit16,
- (((UShort)(opc)) << 8) | ((UShort)modrm) );
- DIP("movq %s, %s\n",
- nameMMXReg(gregOfRM(modrm)), nameMMXReg(eregOfRM(modrm)));
- } else {
- Int tmpa;
- pair = disAMode ( cb, sorb, eip, dis_buf );
- tmpa = LOW24(pair);
- eip += HI8(pair);
- uInstr2(cb, MMX2_MemWr, 8,
- Lit16,
- (((UShort)(opc)) << 8) | ((UShort)modrm),
- TempReg, tmpa);
- DIP("mov(nt)q %s, %s\n",
- nameMMXReg(gregOfRM(modrm)), dis_buf);
- }
- break;
-
- case 0xFC: case 0xFD: case 0xFE:
- /* PADDgg (src)mmxreg-or-mem, (dst)mmxreg */
- vg_assert(sz == 4);
- eip = dis_MMXop_regmem_to_reg ( cb, sorb, eip, opc, "padd", True );
- break;
-
- case 0xD4:
- /* PADDQ (src)mmxreg-or-mem, (dst)mmxreg */
- vg_assert(sz == 4);
- eip = dis_MMXop_regmem_to_reg ( cb, sorb, eip, opc, "paddq", False );
- break;
-
- case 0xEC: case 0xED:
- /* PADDSgg (src)mmxreg-or-mem, (dst)mmxreg */
- vg_assert(sz == 4);
- eip = dis_MMXop_regmem_to_reg ( cb, sorb, eip, opc, "padds", True );
- break;
-
- case 0xDC: case 0xDD:
- /* PADDUSgg (src)mmxreg-or-mem, (dst)mmxreg */
- vg_assert(sz == 4);
- eip = dis_MMXop_regmem_to_reg ( cb, sorb, eip, opc, "paddus", True );
- break;
-
- case 0xF8: case 0xF9: case 0xFA: case 0xFB:
- /* PSUBgg (src)mmxreg-or-mem, (dst)mmxreg */
- vg_assert(sz == 4);
- eip = dis_MMXop_regmem_to_reg ( cb, sorb, eip, opc, "psub", True );
- break;
-
- case 0xE8: case 0xE9:
- /* PSUBSgg (src)mmxreg-or-mem, (dst)mmxreg */
- vg_assert(sz == 4);
- eip = dis_MMXop_regmem_to_reg ( cb, sorb, eip, opc, "psubs", True );
- break;
-
- case 0xD8: case 0xD9:
- /* PSUBUSgg (src)mmxreg-or-mem, (dst)mmxreg */
- vg_assert(sz == 4);
- eip = dis_MMXop_regmem_to_reg ( cb, sorb, eip, opc, "psubus", True );
- break;
-
- case 0xE4: /* PMULHUW (src)mmxreg-or-mem, (dst)mmxreg */
- vg_assert(sz == 4);
- eip = dis_MMXop_regmem_to_reg ( cb, sorb, eip, opc, "pmulhuw", False );
- break;
-
- case 0xE5: /* PMULHW (src)mmxreg-or-mem, (dst)mmxreg */
- vg_assert(sz == 4);
- eip = dis_MMXop_regmem_to_reg ( cb, sorb, eip, opc, "pmulhw", False );
- break;
-
- case 0xD5: /* PMULLW (src)mmxreg-or-mem, (dst)mmxreg */
- vg_assert(sz == 4);
- eip = dis_MMXop_regmem_to_reg ( cb, sorb, eip, opc, "pmullw", False );
- break;
-
- case 0xF4: /* PMULUDQ (src)mmxreg-or-mem, (dst)mmxreg */
- vg_assert(sz == 4);
- eip = dis_MMXop_regmem_to_reg ( cb, sorb, eip, opc, "pmuludq", False );
- break;
-
- case 0xF5: /* PMADDWD (src)mmxreg-or-mem, (dst)mmxreg */
- vg_assert(sz == 4);
- eip = dis_MMXop_regmem_to_reg ( cb, sorb, eip, opc, "pmaddwd", False );
- break;
-
- case 0x74: case 0x75: case 0x76:
- /* PCMPEQgg (src)mmxreg-or-mem, (dst)mmxreg */
- vg_assert(sz == 4);
- eip = dis_MMXop_regmem_to_reg ( cb, sorb, eip, opc, "pcmpeq", True );
- break;
-
- case 0x64: case 0x65: case 0x66:
- /* PCMPGTgg (src)mmxreg-or-mem, (dst)mmxreg */
- vg_assert(sz == 4);
- eip = dis_MMXop_regmem_to_reg ( cb, sorb, eip, opc, "pcmpgt", True );
- break;
-
- case 0x6B: /* PACKSSDW (src)mmxreg-or-mem, (dst)mmxreg */
- vg_assert(sz == 4);
- eip = dis_MMXop_regmem_to_reg ( cb, sorb, eip, opc, "packssdw", False );
- break;
-
- case 0x63: /* PACKSSWB (src)mmxreg-or-mem, (dst)mmxreg */
- vg_assert(sz == 4);
- eip = dis_MMXop_regmem_to_reg ( cb, sorb, eip, opc, "packsswb", False );
- break;
-
- case 0x67: /* PACKUSWB (src)mmxreg-or-mem, (dst)mmxreg */
- vg_assert(sz == 4);
- eip = dis_MMXop_regmem_to_reg ( cb, sorb, eip, opc, "packuswb", False );
- break;
-
- case 0x68: case 0x69: case 0x6A:
- /* PUNPCKHgg (src)mmxreg-or-mem, (dst)mmxreg */
- vg_assert(sz == 4);
- eip = dis_MMXop_regmem_to_reg ( cb, sorb, eip, opc, "punpckh", True );
- break;
-
- case 0x60: case 0x61: case 0x62:
- /* PUNPCKLgg (src)mmxreg-or-mem, (dst)mmxreg */
- vg_assert(sz == 4);
- eip = dis_MMXop_regmem_to_reg ( cb, sorb, eip, opc, "punpckl", True );
- break;
-
- case 0xDB: /* PAND (src)mmxreg-or-mem, (dst)mmxreg */
- vg_assert(sz == 4);
- eip = dis_MMXop_regmem_to_reg ( cb, sorb, eip, opc, "pand", False );
- break;
-
- case 0xDF: /* PANDN (src)mmxreg-or-mem, (dst)mmxreg */
- vg_assert(sz == 4);
- eip = dis_MMXop_regmem_to_reg ( cb, sorb, eip, opc, "pandn", False );
- break;
-
- case 0xEB: /* POR (src)mmxreg-or-mem, (dst)mmxreg */
- vg_assert(sz == 4);
- eip = dis_MMXop_regmem_to_reg ( cb, sorb, eip, opc, "por", False );
- break;
-
- case 0xEF: /* PXOR (src)mmxreg-or-mem, (dst)mmxreg */
- vg_assert(sz == 4);
- eip = dis_MMXop_regmem_to_reg ( cb, sorb, eip, opc, "pxor", False );
- break;
-
- case 0xF1: case 0xF2: case 0xF3:
- /* PSLLgg (src)mmxreg-or-mem, (dst)mmxreg */
- vg_assert(sz == 4);
- eip = dis_MMXop_regmem_to_reg ( cb, sorb, eip, opc, "psll", True );
- break;
-
- case 0xD1: case 0xD2: case 0xD3:
- /* PSRLgg (src)mmxreg-or-mem, (dst)mmxreg */
- vg_assert(sz == 4);
- eip = dis_MMXop_regmem_to_reg ( cb, sorb, eip, opc, "psrl", True );
- break;
-
- case 0xE1: case 0xE2:
- /* PSRAgg (src)mmxreg-or-mem, (dst)mmxreg */
- vg_assert(sz == 4);
- eip = dis_MMXop_regmem_to_reg ( cb, sorb, eip, opc, "psra", True );
- break;
-
- case 0xDA:
- /* PMINUB (src)mmxreg-or-mem, (dst)mmxreg */
- vg_assert(sz == 4);
- eip = dis_MMXop_regmem_to_reg ( cb, sorb, eip, opc, "pminub", False );
- break;
-
- case 0xDE:
- /* PMAXUB (src)mmxreg-or-mem, (dst)mmxreg */
- vg_assert(sz == 4);
- eip = dis_MMXop_regmem_to_reg ( cb, sorb, eip, opc, "pmaxub", False );
- break;
-
- case 0xEA:
- /* PMINSW (src)mmxreg-or-mem, (dst)mmxreg */
- vg_assert(sz == 4);
- eip = dis_MMXop_regmem_to_reg ( cb, sorb, eip, opc, "pminsw", False );
- break;
-
- case 0xEE:
- /* PMAXSW (src)mmxreg-or-mem, (dst)mmxreg */
- vg_assert(sz == 4);
- eip = dis_MMXop_regmem_to_reg ( cb, sorb, eip, opc, "pmaxsw", False );
- break;
-
- case 0xE0:
- /* PAVGB (src)mmxreg-or-mem, (dst)mmxreg */
- vg_assert(sz == 4);
- eip = dis_MMXop_regmem_to_reg ( cb, sorb, eip, opc, "pavgb", False );
- break;
-
- case 0xE3:
- /* PAVGW (src)mmxreg-or-mem, (dst)mmxreg */
- vg_assert(sz == 4);
- eip = dis_MMXop_regmem_to_reg ( cb, sorb, eip, opc, "pavgw", False );
- break;
-
- case 0xF6:
- /* PSADBW (src)mmxreg-or-mem, (dst)mmxreg */
- vg_assert(sz == 4);
- eip = dis_MMXop_regmem_to_reg ( cb, sorb, eip, opc, "psadbw", False );
- break;
-
- case 0x70:
- /* PSHUFW imm8, (src)mmxreg-or-mem, (dst)mmxreg */
- vg_assert(sz == 4);
- eip = dis_MMXop_regmem_to_reg_Imm8 ( cb, sorb, eip, opc, "pshufw", False );
- break;
-
- case 0xD7:
- /* PMOVMSKB (src)mmxreg, (dst)ireg */
- vg_assert(sz == 4);
- modrm = getUChar(eip);
- vg_assert(epartIsReg(modrm));
- t1 = newTemp(cb);
- uInstr3(cb, SSE2g_RegWr, 4,
- Lit16, (((UShort)(0x0F)) << 8) | (UShort)(opc),
- Lit16, (UShort)modrm,
- TempReg, t1 );
- uInstr2(cb, PUT, 4, TempReg, t1, ArchReg, gregOfRM(modrm));
- DIP("pmovmskb %s, %s\n",
- nameMMXReg(eregOfRM(modrm)), nameIReg(4,gregOfRM(modrm)));
- eip++;
- break;
-
- case 0xC5:
- /* PEXTRW (src)mmxreg, (dst)ireg */
- vg_assert(sz == 4);
- t1 = newTemp(cb);
- modrm = getUChar(eip); eip++;
- abyte = getUChar(eip); eip++;
- vg_assert(epartIsReg(modrm));
- uInstr3(cb, SSE2g1_RegWr, 4,
- Lit16, (((UShort)(0x0F)) << 8) | (UShort)(opc),
- Lit16, (UShort)modrm,
- TempReg, t1 );
- uLiteral(cb, abyte);
- uInstr2(cb, PUT, 4, TempReg, t1, ArchReg, gregOfRM(modrm));
- DIP("pextrw %s, %d, %s\n",
- nameMMXReg(eregOfRM(modrm)), (Int)abyte,
- nameIReg(4, gregOfRM(modrm)));
- break;
-
- case 0xC4:
- /* PINSRW (src)ireg, (dst)mmxreg */
- vg_assert(sz == 4);
- t1 = newTemp(cb);
- modrm = getUChar(eip); eip++;
- abyte = getUChar(eip); eip++;
- vg_assert(epartIsReg(modrm));
- uInstr2(cb, GET, 2, ArchReg, eregOfRM(modrm), TempReg, t1);
- uInstr3(cb, SSE2e1_RegRd, 2,
- Lit16, (((UShort)(0x0F)) << 8) | (UShort)(opc),
- Lit16, (UShort)modrm,
- TempReg, t1 );
- uLiteral(cb, abyte);
- DIP("pinsrw %s, %d, %s\n", nameIReg(2, eregOfRM(modrm)),
- (Int)abyte, nameMMXReg(gregOfRM(modrm)));
- break;
-
- case 0xA1: /* POP %FS */
- dis_pop_segreg( cb, R_FS, sz ); break;
- case 0xA9: /* POP %GS */
- dis_pop_segreg( cb, R_GS, sz ); break;
-
- case 0xA0: /* PUSH %FS */
- dis_push_segreg( cb, R_FS, sz ); break;
- case 0xA8: /* PUSH %GS */
- dis_push_segreg( cb, R_GS, sz ); break;
-
- /* =-=-=-=-=-=-=-=-=- unimp2 =-=-=-=-=-=-=-=-=-=-= */
-
- default:
- goto decode_failure;
- } /* switch (opc) for the 2-byte opcodes */
- goto decode_success;
- } /* case 0x0F: of primary opcode */
-
- /* ------------------------ ??? ------------------------ */
-
- default:
- decode_failure:
- /* All decode failures end up here. */
- VG_(printf)("disInstr: unhandled instruction bytes: "
- "0x%x 0x%x 0x%x 0x%x\n",
- (Int)eip_start[0],
- (Int)eip_start[1],
- (Int)eip_start[2],
- (Int)eip_start[3] );
-
- /* Print address of failing instruction. */
- VG_(describe_eip)((Addr)eip_start, loc_buf, M_VG_ERRTXT);
- VG_(printf)(" at %s\n", loc_buf);
-
- uInstr0(cb, CALLM_S, 0);
- uInstr1(cb, CALLM, 0, Lit16,
- VGOFF_(helper_undefined_instruction));
- uInstr0(cb, CALLM_E, 0);
-
- /* just because everything else insists the last instruction of
- a BB is a jmp */
- jmp_lit(cb, eip);
- *isEnd = True;
- break;
- return eip;
-
- } /* switch (opc) for the main (primary) opcode switch. */
-
- decode_success:
- /* All decode successes end up here. */
- DIP("\n");
- for (; first_uinstr < cb->used; first_uinstr++) {
- VG_(sanity_check_UInstr)( first_uinstr, &cb->instrs[first_uinstr] );
- if (VG_(print_codegen))
- VG_(pp_UInstr)(first_uinstr, &cb->instrs[first_uinstr]);
- }
- return eip;
-}
-
-
-/* Disassemble a complete basic block, starting at eip, and dumping
- the ucode into cb. Returns the size, in bytes, of the basic
- block. */
-
-Int VG_(disBB) ( UCodeBlock* cb, Addr eip0 )
-{
- Addr eip = eip0;
- Bool isEnd = False;
- Int delta = 0;
-
- DIP("Original x86 code to UCode:\n\n");
-
- /* After every x86 instruction do an INCEIP, except for the final one
- * in the basic block. For them we patch in the x86 instruction size
- * into the `extra4b' field of the basic-block-ending JMP.
- *
- * The INCEIPs and JMP.extra4b fields allows a tool to track x86
- * instruction sizes, important for some tools (eg. Cachegrind).
- */
- if (VG_(clo_single_step)) {
- eip = disInstr ( cb, eip, &isEnd );
-
- /* Add a JMP to the next (single x86 instruction) BB if it doesn't
- * already end with a JMP instr. We also need to check for no UCode,
- * which occurs if the x86 instr was a nop */
- if (cb->used == 0 || LAST_UINSTR(cb).opcode != JMP) {
- jmp_lit(cb, eip);
- /* Print added JMP */
- if (VG_(print_codegen))
- VG_(pp_UInstr)(cb->used-1, &cb->instrs[cb->used-1]);
- }
- DIP("\n");
- delta = eip - eip0;
-
- } else {
- Addr eip2;
- while (!isEnd) {
- eip2 = disInstr ( cb, eip, &isEnd );
- delta = (eip2 - eip);
- eip = eip2;
- /* Split up giant basic blocks into pieces, so the
- translations fall within 64k. */
- if (eip - eip0 > 2000 && !isEnd) {
- if (VG_(clo_verbosity) > 2)
- VG_(message)(Vg_DebugMsg,
- "Warning: splitting giant basic block into pieces at %p %(y",
- eip, eip);
- jmp_lit(cb, eip);
- /* Print added JMP */
- if (VG_(print_codegen))
- VG_(pp_UInstr)(cb->used-1, &cb->instrs[cb->used-1]);
- isEnd = True;
-
- } else if (!isEnd) {
- uInstr1(cb, INCEIP, 0, Lit16, delta);
- /* Print added INCEIP */
- if (VG_(print_codegen))
- VG_(pp_UInstr)(cb->used-1, &cb->instrs[cb->used-1]);
- }
- DIP("\n");
- }
- }
-
- /* Patch instruction size into final JMP. */
- LAST_UINSTR(cb).extra4b = delta;
-
- return eip - eip0;
-}
-
-#undef DIP
-#undef DIS
-
/*--------------------------------------------------------------------*/
/*--- end vg_to_ucode.c ---*/
/*--------------------------------------------------------------------*/
#include "core.h"
-/*------------------------------------------------------------*/
-/*--- Renamings of frequently-used global functions. ---*/
-/*------------------------------------------------------------*/
-
-#define dis VG_(print_codegen)
/*------------------------------------------------------------*/
-/*--- Reg-alloc stats ---*/
+/*--- %SP-update pass ---*/
/*------------------------------------------------------------*/
-static UInt n_uinstrs_prealloc; // # uinstrs input to reg-alloc
-static UInt n_uinstrs_spill; // # uinstrs added due to spill code
-static UInt n_translations_needing_spill; // # bbs requiring spill code
-static UInt n_total_reg_rank; // total of register ranks over all translations
-
-void VG_(print_reg_alloc_stats)(void)
-{
- VG_(message)(Vg_DebugMsg,
- "reg-alloc: %d t-req-spill, %d+%d orig+spill uis,",
- n_translations_needing_spill,
- n_uinstrs_prealloc, n_uinstrs_spill );
- VG_(message)(Vg_DebugMsg,
- " %d total-reg-rank",
- n_total_reg_rank );
-}
-
-/*------------------------------------------------------------*/
-/*--- Basics ---*/
-/*------------------------------------------------------------*/
-
-#define VG_IS_FLAG_SUBSET(set1,set2) \
- (( ((FlagSet)set1) & ((FlagSet)set2) ) == ((FlagSet)set1) )
-
-#define VG_UNION_FLAG_SETS(set1,set2) \
- ( ((FlagSet)set1) | ((FlagSet)set2) )
-
-// This one is local.
-static UCodeBlock* alloc_UCodeBlock ( Addr orig_eip )
-{
- UCodeBlock* cb = VG_(arena_malloc)(VG_AR_CORE, sizeof(UCodeBlock));
- cb->orig_eip = orig_eip;
- cb->used = 0;
- cb->size = 0;
- cb->instrs = NULL;
- cb->nextTemp = 0;
- return cb;
-}
-
-// This one is called by tools.
-UCodeBlock* VG_(setup_UCodeBlock) ( UCodeBlock* cb_in )
-{
- UCodeBlock* cb = alloc_UCodeBlock( cb_in->orig_eip );
- cb->nextTemp = cb_in->nextTemp;
- return cb;
-}
-
-void VG_(free_UCodeBlock) ( UCodeBlock* cb )
-{
- if (cb->instrs) VG_(arena_free)(VG_AR_CORE, cb->instrs);
- VG_(arena_free)(VG_AR_CORE, cb);
-}
-
-
-/* Ensure there's enough space in a block to add one uinstr. */
-static
-void ensureUInstr ( UCodeBlock* cb )
-{
- if (cb->used == cb->size) {
- if (cb->instrs == NULL) {
- vg_assert(cb->size == 0);
- vg_assert(cb->used == 0);
- cb->size = 8;
- cb->instrs = VG_(arena_malloc)(VG_AR_CORE, 8 * sizeof(UInstr));
- } else {
- Int i;
- UInstr* instrs2 = VG_(arena_malloc)(VG_AR_CORE,
- 2 * sizeof(UInstr) * cb->size);
- for (i = 0; i < cb->used; i++)
- instrs2[i] = cb->instrs[i];
- cb->size *= 2;
- VG_(arena_free)(VG_AR_CORE, cb->instrs);
- cb->instrs = instrs2;
- }
- }
-
- vg_assert(cb->used < cb->size);
-}
-
-
-__inline__
-void VG_(new_NOP) ( UInstr* u )
-{
- u->val1 = u->val2 = u->val3 = 0;
- u->tag1 = u->tag2 = u->tag3 = NoValue;
- u->flags_r = u->flags_w = FlagsEmpty;
- u->jmpkind = JmpBoring;
- u->signed_widen = u->has_ret_val = False;
- u->regs_live_after = ALL_RREGS_LIVE;
- u->lit32 = 0;
- u->opcode = NOP;
- u->size = 0;
- u->cond = 0;
- u->extra4b = 0;
- u->argc = u->regparms_n = 0;
-}
-
-
-/* Add an instruction to a ucode block, and return the index of the
- instruction. */
-__inline__
-void VG_(new_UInstr3) ( UCodeBlock* cb, Opcode opcode, Int sz,
- Tag tag1, UInt val1,
- Tag tag2, UInt val2,
- Tag tag3, UInt val3 )
-{
- UInstr* ui;
- ensureUInstr(cb);
- ui = & cb->instrs[cb->used];
- cb->used++;
- VG_(new_NOP)(ui);
- ui->val1 = val1;
- ui->val2 = val2;
- ui->val3 = val3;
- ui->opcode = opcode;
- ui->tag1 = tag1;
- ui->tag2 = tag2;
- ui->tag3 = tag3;
- ui->size = sz;
- if (tag1 == TempReg) vg_assert(val1 != INVALID_TEMPREG);
- if (tag2 == TempReg) vg_assert(val2 != INVALID_TEMPREG);
- if (tag3 == TempReg) vg_assert(val3 != INVALID_TEMPREG);
-}
-
-
-__inline__
-void VG_(new_UInstr2) ( UCodeBlock* cb, Opcode opcode, Int sz,
- Tag tag1, UInt val1,
- Tag tag2, UInt val2 )
-{
- UInstr* ui;
- ensureUInstr(cb);
- ui = & cb->instrs[cb->used];
- cb->used++;
- VG_(new_NOP)(ui);
- ui->val1 = val1;
- ui->val2 = val2;
- ui->opcode = opcode;
- ui->tag1 = tag1;
- ui->tag2 = tag2;
- ui->size = sz;
- if (tag1 == TempReg) vg_assert(val1 != INVALID_TEMPREG);
- if (tag2 == TempReg) vg_assert(val2 != INVALID_TEMPREG);
-}
-
-
-__inline__
-void VG_(new_UInstr1) ( UCodeBlock* cb, Opcode opcode, Int sz,
- Tag tag1, UInt val1 )
-{
- UInstr* ui;
- ensureUInstr(cb);
- ui = & cb->instrs[cb->used];
- cb->used++;
- VG_(new_NOP)(ui);
- ui->val1 = val1;
- ui->opcode = opcode;
- ui->tag1 = tag1;
- ui->size = sz;
- if (tag1 == TempReg) vg_assert(val1 != INVALID_TEMPREG);
-}
-
-
-__inline__
-void VG_(new_UInstr0) ( UCodeBlock* cb, Opcode opcode, Int sz )
-{
- UInstr* ui;
- ensureUInstr(cb);
- ui = & cb->instrs[cb->used];
- cb->used++;
- VG_(new_NOP)(ui);
- ui->opcode = opcode;
- ui->size = sz;
-}
-
-/* Copy an instruction into the given codeblock. */
-__inline__
-void VG_(copy_UInstr) ( UCodeBlock* cb, UInstr* instr )
-{
- ensureUInstr(cb);
- cb->instrs[cb->used] = *instr;
- cb->used++;
-}
-
-/* Set the lit32 field of the most recent uinsn. */
-void VG_(set_lit_field) ( UCodeBlock* cb, UInt lit32 )
-{
- LAST_UINSTR(cb).lit32 = lit32;
-}
-
-
-/* Set the C call info fields of the most recent uinsn. */
-void VG_(set_ccall_fields) ( UCodeBlock* cb, Addr fn, UChar argc, UChar
- regparms_n, Bool has_ret_val )
-{
- vg_assert(argc < 4);
- vg_assert(regparms_n <= argc);
- LAST_UINSTR(cb).lit32 = fn;
- LAST_UINSTR(cb).argc = argc;
- LAST_UINSTR(cb).regparms_n = regparms_n;
- LAST_UINSTR(cb).has_ret_val = has_ret_val;
-}
-
-/* For the last uinsn inserted into cb, set the read, written and
- undefined flags. Undefined flags are counted as written, but it
- seems worthwhile to distinguish them.
-*/
-__inline__
-void VG_(set_flag_fields) ( UCodeBlock* cb,
- FlagSet rr, FlagSet ww, FlagSet uu )
-{
- FlagSet uw = VG_UNION_FLAG_SETS(ww,uu);
-
- vg_assert(rr == (rr & FlagsALL));
- vg_assert(uw == (uw & FlagsALL));
- LAST_UINSTR(cb).flags_r = rr;
- LAST_UINSTR(cb).flags_w = uw;
-}
-
-void VG_(set_cond_field) ( UCodeBlock* cb, Condcode cond )
-{
- LAST_UINSTR(cb).cond = cond;
-}
-
-void VG_(set_widen_fields) ( UCodeBlock* cb, UInt szs, Bool is_signed )
-{
- LAST_UINSTR(cb).extra4b = szs;
- LAST_UINSTR(cb).signed_widen = is_signed;
-}
-
-
-Bool VG_(any_flag_use) ( UInstr* u )
-{
- return (u->flags_r != FlagsEmpty
- || u->flags_w != FlagsEmpty);
-}
-
-#if 1
-# define BEST_ALLOC_ORDER
-#endif
-
-/* Convert a rank in the range 0 .. VG_MAX_REALREGS-1 into an Intel
- register number. This effectively defines the order in which real
- registers are allocated. %ebp is excluded since it is permanently
- reserved for pointing at VG_(baseBlock).
-
- Important! This function must correspond with the value of
- VG_MAX_REALREGS (actually, VG_MAX_REALREGS can be reduced without
- a problem, except the generated code will obviously be worse).
-*/
-__inline__
-Int VG_(rank_to_realreg) ( Int rank )
-{
- switch (rank) {
-# ifdef BEST_ALLOC_ORDER
- /* Probably the best allocation ordering. */
- case 0: return R_EAX;
- case 1: return R_EBX;
- case 2: return R_ECX;
- case 3: return R_EDX;
- case 4: return R_ESI;
- case 5: return R_EDI;
-# else
- /* Contrary; probably the worst. Helpful for debugging, tho. */
- case 5: return R_EAX;
- case 4: return R_EBX;
- case 3: return R_ECX;
- case 2: return R_EDX;
- case 1: return R_ESI;
- case 0: return R_EDI;
-# endif
- default: VG_(core_panic)("VG_(rank_to_realreg)");
- }
-}
-
-/* Convert an Intel register number into a rank in the range 0 ..
- VG_MAX_REALREGS-1. See related comments for rank_to_realreg()
- above. */
-__inline__
-Int VG_(realreg_to_rank) ( Int realReg )
-{
- switch (realReg) {
-# ifdef BEST_ALLOC_ORDER
- case R_EAX: return 0;
- case R_EBX: return 1;
- case R_ECX: return 2;
- case R_EDX: return 3;
- case R_ESI: return 4;
- case R_EDI: return 5;
-# else
- case R_EAX: return 5;
- case R_EBX: return 4;
- case R_ECX: return 3;
- case R_EDX: return 2;
- case R_ESI: return 1;
- case R_EDI: return 0;
-# endif
- default: VG_(core_panic)("VG_(realreg_to_rank)");
- }
-}
-
-Int VG_(get_num_instrs) ( UCodeBlock* cb )
-{
- return cb->used;
-}
-
-Int VG_(get_num_temps) ( UCodeBlock* cb )
-{
- return cb->nextTemp;
-}
-
-UInstr* VG_(get_instr) ( UCodeBlock* cb, Int i )
-{
- return & cb->instrs[i];
-}
-
-UInstr* VG_(get_last_instr) ( UCodeBlock* cb )
-{
- return & cb->instrs[cb->used-1];
-}
-
-
-/*------------------------------------------------------------*/
-/*--- Sanity checking uinstrs. ---*/
-/*------------------------------------------------------------*/
-
-// Global variables that indicate where we are in the translation of a basic
-// block, and affect exactly how UInstrs are sanity-checked.
-static Bool beforeRA = True;
-static Bool beforeLiveness = True;
-
-/* This seems as good a place as any to record some important stuff
- about ucode semantics.
-
- * TempRegs are 32 bits wide. LOADs of 8/16 bit values into a
- TempReg are defined to zero-extend the loaded value to 32 bits.
- This is needed to make the translation of movzbl et al work
- properly.
-
- * Similarly, GETs of a 8/16 bit ArchRegs are zero-extended.
-
- * Arithmetic on TempRegs is at the specified size. For example,
- SUBW t1, t2 has to result in a real 16 bit x86 subtraction
- being emitted -- not a 32 bit one.
-
- * On some insns we allow the cc bit to be set. If so, the
- intention is that the simulated machine's %eflags register
- is copied into that of the real machine before the insn,
- and copied back again afterwards. This means that the
- code generated for that insn must be very careful only to
- update %eflags in the intended way. This is particularly
- important for the routines referenced by CALL insns.
-*/
-
-/* Meaning of operand kinds is as follows:
-
- ArchReg is a register of the simulated CPU, stored in memory,
- in vg_m_state.m_eax .. m_edi. These values are stored
- using the Intel register encoding.
-
- RealReg is a register of the real CPU. There are VG_MAX_REALREGS
- available for allocation. As with ArchRegs, these values
- are stored using the Intel register encoding.
-
- TempReg is a temporary register used to express the results of
- disassembly. There is an unlimited supply of them --
- register allocation and spilling eventually assigns them
- to RealRegs.
-
- SpillNo is a spill slot number. The number of required spill
- slots is VG_MAX_PSEUDOS, in general. Only allowed
- as the ArchReg operand of GET and PUT.
-
- Lit16 is a signed 16-bit literal value.
-
- Literal is a 32-bit literal value. Each uinstr can only hold
- one of these.
-
- The disassembled code is expressed purely in terms of ArchReg,
- TempReg and Literal operands. Eventually, register allocation
- removes all the TempRegs, giving a result using ArchRegs, RealRegs,
- and Literals. New x86 code can easily be synthesised from this.
- There are carefully designed restrictions on which insns can have
- which operands, intended to make it possible to generate x86 code
- from the result of register allocation on the ucode efficiently and
- without need of any further RealRegs.
-
- Restrictions for the individual UInstrs are clear from the checks below.
- Abbreviations: A=ArchReg S=SpillNo T=TempReg L=Literal
- Ls=Lit16 R=RealReg N=NoValue
- As=ArchRegS
-
- Before register allocation, S operands should not appear anywhere.
- After register allocation, all T operands should have been
- converted into Rs, and S operands are allowed in GET and PUT --
- denoting spill saves/restores.
-
- Before liveness analysis, save_e[acd]x fields should all be True.
- Afterwards, they may be False.
-
- The size field should be 0 for insns for which it is meaningless,
- ie those which do not directly move/operate on data.
-*/
-static Bool is_sane_UInstr ( UInstr* u )
-{
-# define LIT0 (u->lit32 == 0)
-# define LIT8 (((u->lit32) & 0xFFFFFF00) == 0)
-# define LIT1 (!(LIT0))
-# define LITm (u->tag1 == Literal ? True : LIT0 )
-# define SZ16 (u->size == 16)
-# define SZ8 (u->size == 8)
-# define SZ4 (u->size == 4)
-# define SZ2 (u->size == 2)
-# define SZ1 (u->size == 1)
-# define SZ0 (u->size == 0)
-# define SZ42 (u->size == 4 || u->size == 2)
-# define SZ48 (u->size == 4 || u->size == 8)
-# define SZ416 (u->size == 4 || u->size == 16)
-# define SZ816 (u->size == 8 || u->size == 16)
-# define SZsse2 (u->size == 4 || u->size == 8 || u->size == 16 || u->size == 512)
-# define SZsse3 (u->size == 4 || u->size == 8 || u->size == 16)
-# define SZi (u->size == 4 || u->size == 2 || u->size == 1)
-# define SZf ( u->size == 4 || u->size == 8 || u->size == 2 \
- || u->size == 10 || u->size == 28 || u->size == 108)
-# define SZ4m ((u->tag1 == TempReg || u->tag1 == RealReg) \
- ? (u->size == 4) : SZi)
-
-/* For these ones, two cases:
- *
- * 1. They are transliterations of the corresponding x86 instruction, in
- * which case they should have its flags (except that redundant write
- * flags can be annulled by the optimisation pass).
- *
- * 2. They are being used generally for other purposes, eg. helping with a
- * 'rep'-prefixed instruction, in which case should have empty flags .
- */
-# define emptyR (u->flags_r == FlagsEmpty)
-# define emptyW (u->flags_w == FlagsEmpty)
-# define CC0 (emptyR && emptyW)
-# define CCr (u->flags_r == FlagsALL && emptyW)
-# define CCw (emptyR && u->flags_w == FlagsALL)
-# define CCa (emptyR && (u->flags_w == FlagsOSZACP || emptyW))
-# define CCc (emptyR && (u->flags_w == FlagsOC || emptyW))
-# define CCe (emptyR && (u->flags_w == FlagsOSZAP || emptyW))
-# define CCb ((u->flags_r==FlagC || emptyR) && \
- (u->flags_w==FlagsOSZACP || emptyW))
-# define CCd ((u->flags_r==FlagC || emptyR) && \
- (u->flags_w==FlagsOC || emptyW))
-# define CCf (CC0 || (emptyR && u->flags_w==FlagsZCP) \
- || (u->flags_r==FlagsZCP && emptyW))
-# define CCg ((u->flags_r==FlagsOSZACP || emptyR) && emptyW)
-# define CCj (u->cond==CondAlways ? CC0 : CCg)
-
-# define TR1 (beforeRA ? (u->tag1 == TempReg) : (u->tag1 == RealReg))
-# define TR2 (beforeRA ? (u->tag2 == TempReg) : (u->tag2 == RealReg))
-# define TR3 (beforeRA ? (u->tag3 == TempReg) : (u->tag3 == RealReg))
-# define A1 (u->tag1 == ArchReg)
-# define A2 (u->tag2 == ArchReg)
-# define AS1 ((u->tag1 == ArchReg) || ((!beforeRA && (u->tag1 == SpillNo))))
-# define AS2 ((u->tag2 == ArchReg) || ((!beforeRA && (u->tag2 == SpillNo))))
-# define AS3 ((u->tag3 == ArchReg) || ((!beforeRA && (u->tag3 == SpillNo))))
-# define L1 (u->tag1 == Literal && u->val1 == 0)
-# define L2 (u->tag2 == Literal && u->val2 == 0)
-# define Ls1 (u->tag1 == Lit16)
-# define Ls2 (u->tag2 == Lit16)
-# define Ls3 (u->tag3 == Lit16)
-# define TRL1 (TR1 || L1)
-# define TRAL1 (TR1 || A1 || L1)
-# define TRA1 (TR1 || A1)
-# define TRA2 (TR2 || A2)
-# define N1 (u->tag1 == NoValue)
-# define N2 (u->tag2 == NoValue)
-# define N3 (u->tag3 == NoValue)
-# define Se1 (u->tag1 == ArchRegS)
-# define Se2 (u->tag2 == ArchRegS)
-
-# define COND0 (u->cond == 0)
-# define EXTRA4b0 (u->extra4b == 0)
-# define EXTRA4b12 (u->extra4b == 1 || u->extra4b == 2)
-# define SG_WD0 (u->signed_widen == 0)
-# define JMPKIND0 (u->jmpkind == 0)
-# define CCALL0 (u->argc==0 && u->regparms_n==0 && u->has_ret_val==0 && \
- ( beforeLiveness \
- ? u->regs_live_after == ALL_RREGS_LIVE \
- : True ))
-
-# define XCONDi ( EXTRA4b0 && SG_WD0 && JMPKIND0 && CCALL0)
-# define XLEA2 (COND0 && SG_WD0 && JMPKIND0 && CCALL0)
-# define XWIDEN (COND0 && EXTRA4b12 && JMPKIND0 && CCALL0)
-# define XJMP ( SG_WD0 && CCALL0)
-# define XCCALL (COND0 && EXTRA4b0 && SG_WD0 && JMPKIND0 )
-# define XOTHER (COND0 && EXTRA4b0 && SG_WD0 && JMPKIND0 && CCALL0)
-
- /* 0 or 1 Literal args per UInstr */
- Int n_lits = 0;
- if (u->tag1 == Literal) n_lits++;
- if (u->tag2 == Literal) n_lits++;
- if (u->tag3 == Literal) n_lits++;
- if (n_lits > 1)
- return False;
-
- /* Fields not checked: val1, val2, val3 */
-
- switch (u->opcode) {
-
- /* Fields checked: lit32 size flags_r/w tag1 tag2 tag3 (rest) */
- case PUTSEG: return LIT0 && SZ2 && CC0 && TR1 && Se2 && N3 && XOTHER;
- case GETSEG: return LIT0 && SZ2 && CC0 && Se1 && TR2 && N3 && XOTHER;
- case USESEG: return LIT0 && SZ0 && CC0 && TR1 && TR2 && N3 && XOTHER;
- case NOP: return LIT0 && SZ0 && CC0 && N1 && N2 && N3 && XOTHER;
- case LOCK: return LIT0 && SZ0 && CC0 && N1 && N2 && N3 && XOTHER;
- case GETF: return LIT0 && SZ42 && CCr && TR1 && N2 && N3 && XOTHER;
- case PUTF: return LIT0 && SZ42 && CCw && TR1 && N2 && N3 && XOTHER;
- case GET: return LIT0 && SZi && CC0 && AS1 && TR2 && N3 && XOTHER;
- case PUT: return LIT0 && SZi && CC0 && TR1 && AS2 && N3 && XOTHER;
- case LOAD:
- case STORE: return LIT0 && SZi && CC0 && TR1 && TR2 && N3 && XOTHER;
- case MOV: return LITm && SZ4m && CC0 && TRL1 && TR2 && N3 && XOTHER;
- case CMOV: return LIT0 && SZ4 && CCg && TR1 && TR2 && N3 && XCONDi;
- case WIDEN: return LIT0 && SZ42 && CC0 && TR1 && N2 && N3 && XWIDEN;
- case JMP: return LITm && SZ0 && CCj && TRL1 && N2 && N3 && XJMP;
- case CALLM: return LIT0 && SZ0 /*any*/ && Ls1 && N2 && N3 && XOTHER;
- case CALLM_S:
- case CALLM_E:return LIT0 && SZ0 && CC0 && N1 && N2 && N3 && XOTHER;
- case PUSH:
- case POP: return LIT0 && SZi && CC0 && TR1 && N2 && N3 && XOTHER;
- case CLEAR: return LIT0 && SZ0 && CC0 && Ls1 && N2 && N3 && XOTHER;
- case AND:
- case OR: return LIT0 && SZi && CCa && TR1 && TR2 && N3 && XOTHER;
- case MUL: return LIT0 && SZ42 && CCa && TRA1 &&TRA2 && N3 && XOTHER;
- case ADD:
- case XOR:
- case SUB: return LITm && SZi && CCa &&TRAL1 && TR2 && N3 && XOTHER;
- case SBB:
- case ADC: return LITm && SZi && CCb &&TRAL1 && TR2 && N3 && XOTHER;
- case SHL:
- case SHR:
- case SAR: return LITm && SZi && CCa && TRL1 && TR2 && N3 && XOTHER;
- case ROL:
- case ROR: return LITm && SZi && CCc && TRL1 && TR2 && N3 && XOTHER;
- case RCL:
- case RCR: return LITm && SZi && CCd && TRL1 && TR2 && N3 && XOTHER;
- case NOT: return LIT0 && SZi && CC0 && TR1 && N2 && N3 && XOTHER;
- case NEG: return LIT0 && SZi && CCa && TR1 && N2 && N3 && XOTHER;
- case INC:
- case DEC: return LIT0 && SZi && CCe && TR1 && N2 && N3 && XOTHER;
- case CC2VAL: return LIT0 && SZ1 && CCg && TR1 && N2 && N3 && XCONDi;
- case BSWAP: return LIT0 && SZ4 && CC0 && TR1 && N2 && N3 && XOTHER;
- case JIFZ: return LIT1 && SZ4 && CC0 && TR1 && L2 && N3 && XOTHER;
- case FPU_R:
- case FPU_W: return LIT0 && SZf && CC0 && Ls1 && TR2 && N3 && XOTHER;
- case FPU: return LIT0 && SZ0 && CCf && Ls1 && N2 && N3 && XOTHER;
- case LEA1: return /*any*/ SZ4 && CC0 && TR1 && TR2 && N3 && XOTHER;
- case LEA2: return /*any*/ SZ4 && CC0 && TR1 && TR2 && TR3 && XLEA2;
- case INCEIP: return LIT0 && SZ0 && CC0 && Ls1 && N2 && N3 && XOTHER;
- case CCALL: return LIT1 && SZ0 && CC0 &&
- (u->argc > 0 ? TR1 : N1) &&
- (u->argc > 1 ? TR2 : N2) &&
- (u->argc > 2 || u->has_ret_val ? TR3 : N3) &&
- u->regparms_n <= u->argc && XCCALL;
- /* Fields checked: lit32 size flags_r/w tag1 tag2 tag3 (rest) */
- case MMX1:
- case MMX2: return LIT0 && SZ0 && CC0 && Ls1 && N2 && N3 && XOTHER;
- case MMX3: return LIT0 && SZ0 && CC0 && Ls1 && Ls2 && N3 && XOTHER;
- case MMX2_MemRd: return LIT0 && SZ48 && CC0 && Ls1 && TR2 && N3 && XOTHER;
- case MMX2_MemWr: return LIT0 && SZ48 && CC0 && Ls1 && TR2 && N3 && XOTHER;
- case MMX2a1_MemRd: return LIT0 && SZ8 && CC0 && Ls1 && Ls2 && TR3 && XOTHER;
- case MMX2_ERegRd: return LIT0 && SZ4 && CC0 && Ls1 && TR2 && N3 && XOTHER;
- case MMX2_ERegWr: return LIT0 && SZ4 && CC0 && Ls1 && TR2 && N3 && XOTHER;
-
- /* Fields checked: lit32 size flags_r/w tag1 tag2 tag3 (rest) */
- case SSE2a_MemWr: return LIT0 && SZsse2 && CC0 && Ls1 && Ls2 && TR3 && XOTHER;
- case SSE2a_MemRd: return LIT0 && SZsse2 && CCa && Ls1 && Ls2 && TR3 && XOTHER;
- case SSE2a1_MemRd: return LIT0 && SZsse3 && CC0 && Ls1 && Ls2 && TR3 && XOTHER;
- case SSE2g_RegWr: return LIT0 && SZ4 && CC0 && Ls1 && Ls2 && TR3 && XOTHER;
- case SSE2g1_RegWr: return LIT8 && SZ4 && CC0 && Ls1 && Ls2 && TR3 && XOTHER;
- case SSE2e1_RegRd: return LIT8 && SZ2 && CC0 && Ls1 && Ls2 && TR3 && XOTHER;
- case SSE3a_MemWr: return LIT0 && SZsse3 && CC0 && Ls1 && Ls2 && TR3 && XOTHER;
- case SSE3a_MemRd: return LIT0 && SZsse3 && CCa && Ls1 && Ls2 && TR3 && XOTHER;
- case SSE3e_RegRd: return LIT0 && SZ4 && CC0 && Ls1 && Ls2 && TR3 && XOTHER;
- case SSE3e_RegWr: return LIT0 && SZ4 && CC0 && Ls1 && Ls2 && TR3 && XOTHER;
- case SSE3a1_MemRd: return LIT8 && SZ816 && CC0 && Ls1 && Ls2 && TR3 && XOTHER;
- case SSE3g_RegWr: return LIT0 && SZ4 && CC0 && Ls1 && Ls2 && TR3 && XOTHER;
- case SSE3g1_RegWr: return LIT8 && SZ4 && CC0 && Ls1 && Ls2 && TR3 && XOTHER;
- case SSE3e1_RegRd: return LIT8 && SZ2 && CC0 && Ls1 && Ls2 && TR3 && XOTHER;
- case SSE3: return LIT0 && SZ0 && CCa && Ls1 && Ls2 && N3 && XOTHER;
- case SSE4: return LIT0 && SZ0 && CCa && Ls1 && Ls2 && N3 && XOTHER;
- case SSE5: return LIT0 && SZ0 && CC0 && Ls1 && Ls2 && Ls3 && XOTHER;
- case SSE3ag_MemRd_RegWr:
- return SZ48 && CC0 && TR1 && TR2 && N3 && XOTHER;
- default:
- if (VG_(needs).extended_UCode)
- return TL_(sane_XUInstr)(beforeRA, beforeLiveness, u);
- else {
- VG_(printf)("unhandled opcode: %u. Perhaps "
- "VG_(needs).extended_UCode should be set?",
- u->opcode);
- VG_(core_panic)("VG_(saneUInstr): unhandled opcode");
- }
- }
-# undef LIT0
-# undef LIT1
-# undef LIT8
-# undef LITm
-# undef SZ16
-# undef SZ8
-# undef SZ4
-# undef SZ2
-# undef SZ1
-# undef SZ0
-# undef SZ42
-# undef SZ48
-# undef SZ416
-# undef SZ816
-# undef SZsse2
-# undef SZsse3
-# undef SZi
-# undef SZf
-# undef SZ4m
-# undef emptyR
-# undef emptyW
-# undef CC0
-# undef CCr
-# undef CCw
-# undef CCa
-# undef CCb
-# undef CCc
-# undef CCd
-# undef CCe
-# undef CCf
-# undef CCg
-# undef CCj
-# undef TR1
-# undef TR2
-# undef TR3
-# undef A1
-# undef A2
-# undef AS1
-# undef AS2
-# undef AS3
-# undef L1
-# undef L2
-# undef Ls1
-# undef Ls2
-# undef Ls3
-# undef TRL1
-# undef TRAL1
-# undef TRA1
-# undef TRA2
-# undef N1
-# undef N2
-# undef N3
-# undef Se2
-# undef Se1
-# undef COND0
-# undef EXTRA4b0
-# undef EXTRA4b12
-# undef SG_WD0
-# undef JMPKIND0
-# undef CCALL0
-# undef XCONDi
-# undef XLEA2
-# undef XWIDEN
-# undef XJMP
-# undef XCCALL
-# undef XOTHER
-}
-
-void VG_(sanity_check_UInstr)( UInt n, UInstr* u )
-{
- Bool sane = is_sane_UInstr(u);
- if (!sane) {
- VG_(printf)("\nInsane instruction:\n");
- VG_(pp_UInstr)(n, u);
- VG_(up_UInstr)(n, u);
- vg_assert(sane);
- }
-}
-
-static void sanity_check_UCodeBlock ( UCodeBlock* cb )
-{
- Int i;
-
- for (i = 0; i < cb->used; i++) {
- Bool sane = is_sane_UInstr(&cb->instrs[i]);
- if (!sane) {
- VG_(printf)("Instruction failed sanity check:\n");
- VG_(up_UInstr)(i, &cb->instrs[i]);
- }
- vg_assert(sane);
- }
-}
-
-/* Sanity checks to do with CALLMs in UCodeBlocks. */
-static Bool is_sane_UCodeBlockCalls ( UCodeBlock* cb )
-{
- Int callm = 0;
- Int callm_s = 0;
- Int callm_e = 0;
- Int callm_ptr, calls_ptr;
- Int i, j, t;
- Bool incall = False;
-
- /* Ensure the number of CALLM, CALLM_S and CALLM_E are the same. */
-
- for (i = 0; i < cb->used; i++) {
- switch (cb->instrs[i].opcode) {
- case CALLM:
- if (!incall) return False;
- callm++;
- break;
- case CALLM_S:
- if (incall) return False;
- incall = True;
- callm_s++;
- break;
- case CALLM_E:
- if (!incall) return False;
- incall = False;
- callm_e++;
- break;
- case PUSH: case POP: case CLEAR:
- if (!incall) return False;
- break;
- default:
- break;
- }
- }
- if (incall) return False;
- if (callm != callm_s || callm != callm_e) return False;
-
- /* Check the sections between CALLM_S and CALLM's. Ensure that no
- PUSH uinsn pushes any TempReg that any other PUSH in the same
- section pushes. Ie, check that the TempReg args to PUSHes in
- the section are unique. If not, the instrumenter generates
- incorrect code for CALLM insns. */
-
- callm_ptr = 0;
-
- find_next_CALLM:
- /* Search for the next interval, making calls_ptr .. callm_ptr
- bracket it. */
- while (callm_ptr < cb->used
- && cb->instrs[callm_ptr].opcode != CALLM)
- callm_ptr++;
- if (callm_ptr == cb->used)
- return True;
- vg_assert(cb->instrs[callm_ptr].opcode == CALLM);
-
- calls_ptr = callm_ptr - 1;
- while (cb->instrs[calls_ptr].opcode != CALLM_S)
- calls_ptr--;
- vg_assert(cb->instrs[calls_ptr].opcode == CALLM_S);
- vg_assert(calls_ptr >= 0);
-
- /* VG_(printf)("interval from %d to %d\n", calls_ptr, callm_ptr ); */
-
- /* For each PUSH insn in the interval ... */
- for (i = calls_ptr + 1; i < callm_ptr; i++) {
- if (cb->instrs[i].opcode != PUSH) continue;
- t = cb->instrs[i].val1;
- /* Ensure no later PUSH insns up to callm_ptr push the same
- TempReg. Return False if any such are found. */
- for (j = i+1; j < callm_ptr; j++) {
- if (cb->instrs[j].opcode == PUSH &&
- cb->instrs[j].val1 == t)
- return False;
- }
- }
-
- /* This interval is clean. Keep going ... */
- callm_ptr++;
- goto find_next_CALLM;
-}
-
-static void sanity_check_UCodeBlockCalls( UCodeBlock* cb )
-{
- if ( ! is_sane_UCodeBlockCalls( cb ) ) {
- VG_(pp_UCodeBlock)(cb, "block failing calls sanity check");
- VG_(core_panic)("bad block");
- }
-}
-
-/*------------------------------------------------------------*/
-/*--- Printing uinstrs. ---*/
-/*------------------------------------------------------------*/
-
-/* Global that dictates whether to print generated code at all stages */
-Bool VG_(print_codegen);
-
-Char* VG_(name_UCondcode) ( Condcode cond )
-{
- switch (cond) {
- case CondO: return "o";
- case CondNO: return "no";
- case CondB: return "b";
- case CondNB: return "nb";
- case CondZ: return "z";
- case CondNZ: return "nz";
- case CondBE: return "be";
- case CondNBE: return "nbe";
- case CondS: return "s";
- case CondNS: return "ns";
- case CondP: return "p";
- case CondNP: return "np";
- case CondL: return "l";
- case CondNL: return "nl";
- case CondLE: return "le";
- case CondNLE: return "nle";
- case CondAlways: return "MP"; /* hack! */
- default: VG_(core_panic)("name_UCondcode");
- }
-}
-
-
-static void vg_ppFlagSet ( Char* prefix, FlagSet set )
-{
- VG_(printf)("%s", prefix);
- if (set & FlagD) VG_(printf)("D");
- if (set & FlagO) VG_(printf)("O");
- if (set & FlagS) VG_(printf)("S");
- if (set & FlagZ) VG_(printf)("Z");
- if (set & FlagA) VG_(printf)("A");
- if (set & FlagC) VG_(printf)("C");
- if (set & FlagP) VG_(printf)("P");
-}
-
-
-static void ppTempReg ( Int tt )
-{
- if ((tt & 1) == 0)
- VG_(printf)("t%d", tt);
- else
- VG_(printf)("q%d", tt-1);
-}
-
-
-void VG_(pp_UOperand) ( UInstr* u, Int operandNo, Int sz, Bool parens )
-{
- UInt tag, val;
- switch (operandNo) {
- case 1: tag = u->tag1; val = u->val1; break;
- case 2: tag = u->tag2; val = u->val2; break;
- case 3: tag = u->tag3; val = u->val3; break;
- default: VG_(core_panic)("VG_(pp_UOperand)(1)");
- }
- if (tag == Literal) val = u->lit32;
-
- if (parens) VG_(printf)("(");
- switch (tag) {
- case TempReg: ppTempReg(val); break;
- case RealReg: VG_(printf)("%s",nameIReg(sz==0 ? 4 : sz,val)); break;
- case Literal: VG_(printf)("$0x%x", val); break;
- case Lit16: VG_(printf)("$0x%x", val); break;
- case NoValue: VG_(printf)("NoValue"); break;
- case ArchReg: VG_(printf)("%S",nameIReg(sz,val)); break;
- case ArchRegS: VG_(printf)("%S",nameSReg(val)); break;
- case SpillNo: VG_(printf)("spill%d", val); break;
- default: VG_(core_panic)("VG_(ppUOperand)(2)");
- }
- if (parens) VG_(printf)(")");
-}
-
-
-Char* VG_(name_UOpcode) ( Bool upper, Opcode opc )
-{
- switch (opc) {
- case ADD: return (upper ? "ADD" : "add");
- case ADC: return (upper ? "ADC" : "adc");
- case AND: return (upper ? "AND" : "and");
- case OR: return (upper ? "OR" : "or");
- case XOR: return (upper ? "XOR" : "xor");
- case SUB: return (upper ? "SUB" : "sub");
- case SBB: return (upper ? "SBB" : "sbb");
- case SHL: return (upper ? "SHL" : "shl");
- case SHR: return (upper ? "SHR" : "shr");
- case SAR: return (upper ? "SAR" : "sar");
- case ROL: return (upper ? "ROL" : "rol");
- case ROR: return (upper ? "ROR" : "ror");
- case RCL: return (upper ? "RCL" : "rcl");
- case RCR: return (upper ? "RCR" : "rcr");
- case MUL: return (upper ? "MUL" : "mul");
- case NOT: return (upper ? "NOT" : "not");
- case NEG: return (upper ? "NEG" : "neg");
- case INC: return (upper ? "INC" : "inc");
- case DEC: return (upper ? "DEC" : "dec");
- case BSWAP: return (upper ? "BSWAP" : "bswap");
- default: break;
- }
- if (!upper) VG_(core_panic)("vg_name_UOpcode: invalid !upper");
- switch (opc) {
- case CALLM_S: return "CALLM_S";
- case CALLM_E: return "CALLM_E";
- case INCEIP: return "INCEIP";
- case LEA1: return "LEA1";
- case LEA2: return "LEA2";
- case NOP: return "NOP";
- case LOCK: return "LOCK";
- case GET: return "GET";
- case PUT: return "PUT";
- case GETF: return "GETF";
- case PUTF: return "PUTF";
- case GETSEG: return "GETSEG";
- case PUTSEG: return "PUTSEG";
- case USESEG: return "USESEG";
- case LOAD: return "LD" ;
- case STORE: return "ST" ;
- case MOV: return "MOV";
- case CMOV: return "CMOV";
- case WIDEN: return "WIDEN";
- case JMP: return "J" ;
- case JIFZ: return "JIFZ" ;
- case CALLM: return "CALLM";
- case CCALL: return "CCALL";
- case PUSH: return "PUSH" ;
- case POP: return "POP" ;
- case CLEAR: return "CLEAR";
- case CC2VAL: return "CC2VAL";
- case FPU_R: return "FPU_R";
- case FPU_W: return "FPU_W";
- case FPU: return "FPU" ;
- case MMX1: return "MMX1" ;
- case MMX2: return "MMX2" ;
- case MMX3: return "MMX3" ;
- case MMX2_MemRd: return "MMX2_MRd" ;
- case MMX2_MemWr: return "MMX2_MWr" ;
- case MMX2a1_MemRd: return "MMX2a1_MRd" ;
- case MMX2_ERegRd: return "MMX2_eRRd" ;
- case MMX2_ERegWr: return "MMX2_eRWr" ;
- case SSE2a_MemWr: return "SSE2a_MWr";
- case SSE2a_MemRd: return "SSE2a_MRd";
- case SSE2g_RegWr: return "SSE2g_RWr";
- case SSE2a1_MemRd: return "SSE2a1_MRd";
- case SSE2g1_RegWr: return "SSE2g1_RWr";
- case SSE2e1_RegRd: return "SSE2e1_RRd";
- case SSE3e_RegRd: return "SSE3e_RRd";
- case SSE3e_RegWr: return "SSE3e_RWr";
- case SSE3g_RegWr: return "SSE3g_RWr";
- case SSE3a1_MemRd: return "SSE3a1_MRd";
- case SSE3g1_RegWr: return "SSE3g1_RWr";
- case SSE3e1_RegRd: return "SSE3e1_RRd";
- case SSE3: return "SSE3";
- case SSE4: return "SSE4";
- case SSE5: return "SSE5";
- case SSE3a_MemWr: return "SSE3a_MWr";
- case SSE3a_MemRd: return "SSE3a_MRd";
- case SSE3ag_MemRd_RegWr: return "SSE3ag_MemRd_RegWr";
- default:
- if (VG_(needs).extended_UCode)
- return TL_(name_XUOpcode)(opc);
- else {
- VG_(printf)("unhandled opcode: %u. Perhaps "
- "VG_(needs).extended_UCode should be set?",
- opc);
- VG_(core_panic)("name_UOpcode: unhandled opcode");
- }
- }
-}
-
-static
-void pp_realregs_liveness ( UInstr* u )
-{
-# define PRINT_RREG_LIVENESS(realReg,s) \
- VG_(printf)( IS_RREG_LIVE(VG_(realreg_to_rank)(realReg), \
- u->regs_live_after) \
- ? s : "-");
-
- VG_(printf)("[");
- PRINT_RREG_LIVENESS(R_EAX, "a");
- PRINT_RREG_LIVENESS(R_EBX, "b");
- PRINT_RREG_LIVENESS(R_ECX, "c");
- PRINT_RREG_LIVENESS(R_EDX, "d");
- PRINT_RREG_LIVENESS(R_ESI, "S");
- PRINT_RREG_LIVENESS(R_EDI, "D");
- VG_(printf)("]");
-
-# undef PRINT_RREG_LIVENESS
-}
-
-/* Ugly-print UInstr :) */
-void VG_(up_UInstr) ( Int i, UInstr* u )
-{
- VG_(pp_UInstr_regs)(i, u);
-
- VG_(printf)("opcode: %d\n", u->opcode);
- VG_(printf)("lit32: 0x%x\n", u->lit32);
- VG_(printf)("size: %d\n", u->size);
- VG_(printf)("val1,val2,val3: %d, %d, %d\n", u->val1, u->val2, u->val3);
- VG_(printf)("tag1,tag2,tag3: %d, %d, %d\n", u->tag1, u->tag2, u->tag3);
- VG_(printf)("flags_r: 0x%x\n", u->flags_r);
- VG_(printf)("flags_w: 0x%x\n", u->flags_w);
- VG_(printf)("extra4b: 0x%x\n", u->extra4b);
- VG_(printf)("cond: 0x%x\n", u->cond);
- VG_(printf)("signed_widen: %d\n", u->signed_widen);
- VG_(printf)("jmpkind: %d\n", u->jmpkind);
- VG_(printf)("argc,regparms_n: %d, %d\n", u->argc, u->regparms_n);
- VG_(printf)("has_ret_val: %d\n", u->has_ret_val);
- VG_(printf)("regs_live_after: ");
- pp_realregs_liveness(u);
- VG_(printf)("\n");
-}
-
-static
-void pp_UInstrWorker ( Int instrNo, UInstr* u, Bool ppRegsLiveness )
-{
- VG_(printf)("\t%4d: %s", instrNo,
- VG_(name_UOpcode)(True, u->opcode));
- // For JMP, the condition goes before the size
- if (u->opcode == JMP)
- VG_(printf)("%s", VG_(name_UCondcode)(u->cond));
-
- switch (u->size) {
- case 0: VG_(printf)("o"); break;
- case 1: VG_(printf)("B"); break;
- case 2: VG_(printf)("W"); break;
- case 4: VG_(printf)("L"); break;
- case 8: VG_(printf)("Q"); break;
- case 16: VG_(printf)("QQ"); break;
- default: VG_(printf)("%d", (Int)u->size); break;
- }
-
- // For CC2VAL and CMOV, the condition goes after the size
- if (u->opcode == CC2VAL || u->opcode == CMOV)
- VG_(printf)("%s", VG_(name_UCondcode)(u->cond));
-
- // Append extra bits
- switch (u->opcode) {
- case JMP:
- switch (u->jmpkind) {
- case JmpCall: VG_(printf)("-c"); break;
- case JmpRet: VG_(printf)("-r"); break;
- case JmpSyscall: VG_(printf)("-sys"); break;
- case JmpClientReq: VG_(printf)("-cli"); break;
- case JmpYield: VG_(printf)("-yld"); break;
- default: break;
- }
- break;
-
- case WIDEN:
- VG_(printf)("_%c%c", VG_(toupper)(nameISize(u->extra4b)),
- u->signed_widen?'s':'z');
- }
- VG_(printf)(" \t");
-
- switch (u->opcode) {
-
- case CALLM_S: case CALLM_E:
- break;
-
- case INCEIP:
- VG_(printf)("$%d", u->val1);
- break;
-
- case LEA2:
- VG_(printf)("%d(" , u->lit32);
- VG_(pp_UOperand)(u, 1, 4, False);
- VG_(printf)(",");
- VG_(pp_UOperand)(u, 2, 4, False);
- VG_(printf)(",%d), ", (Int)u->extra4b);
- VG_(pp_UOperand)(u, 3, 4, False);
- break;
-
- case LEA1:
- VG_(printf)("%d" , u->lit32);
- VG_(pp_UOperand)(u, 1, 4, True);
- VG_(printf)(", ");
- VG_(pp_UOperand)(u, 2, 4, False);
- break;
-
- case NOP: case LOCK:
- break;
-
- case FPU_W:
- VG_(printf)("0x%x:0x%x, ",
- (u->val1 >> 8) & 0xFF, u->val1 & 0xFF );
- VG_(pp_UOperand)(u, 2, 4, True);
- break;
-
- case FPU_R:
- VG_(printf)("");
- VG_(pp_UOperand)(u, 2, 4, True);
- VG_(printf)(", 0x%x:0x%x",
- (u->val1 >> 8) & 0xFF, u->val1 & 0xFF );
- break;
-
- case FPU:
- VG_(printf)("0x%x:0x%x",
- (u->val1 >> 8) & 0xFF, u->val1 & 0xFF );
- break;
-
- case MMX1:
- VG_(printf)("0x%x",
- u->val1 & 0xFF );
- break;
-
- case MMX2:
- VG_(printf)("0x%x:0x%x",
- (u->val1 >> 8) & 0xFF, u->val1 & 0xFF );
- break;
-
- case MMX3:
- VG_(printf)("0x%x:0x%x:0x%x",
- (u->val1 >> 8) & 0xFF, u->val1 & 0xFF, u->val2 & 0xFF );
- break;
-
- case MMX2_ERegWr:
- case MMX2_ERegRd:
- VG_(printf)("0x%x:0x%x, ",
- (u->val1 >> 8) & 0xFF, u->val1 & 0xFF );
- VG_(pp_UOperand)(u, 2, 4, False);
- break;
-
- case MMX2_MemWr:
- case MMX2_MemRd:
- VG_(printf)("0x%x:0x%x",
- (u->val1 >> 8) & 0xFF, u->val1 & 0xFF );
- VG_(pp_UOperand)(u, 2, 4, True);
- break;
-
- case MMX2a1_MemRd:
- VG_(printf)("0x%x:0x%x:0x%x",
- (u->val1 >> 8) & 0xFF, u->val1 & 0xFF, u->val2 & 0xFF );
- VG_(pp_UOperand)(u, 3, 4, True);
- break;
-
- case SSE2a_MemWr:
- case SSE2a_MemRd:
- case SSE2g_RegWr:
- case SSE2g1_RegWr:
- case SSE2e1_RegRd:
- VG_(printf)("0x%x:0x%x:0x%x",
- (u->val1 >> 8) & 0xFF, u->val1 & 0xFF, u->val2 & 0xFF );
- VG_(pp_UOperand)(u, 3, 4, True);
- break;
-
- case SSE2a1_MemRd:
- case SSE3a_MemWr:
- case SSE3a_MemRd:
- VG_(printf)("0x%x:0x%x:0x%x:0x%x",
- (u->val1 >> 8) & 0xFF, u->val1 & 0xFF,
- (u->val2 >> 8) & 0xFF, u->val2 & 0xFF );
- VG_(pp_UOperand)(u, 3, 4, True);
- break;
-
- case SSE3e_RegWr:
- case SSE3e_RegRd:
- case SSE3g_RegWr:
- VG_(printf)("0x%x:0x%x:0x%x:0x%x",
- (u->val1 >> 8) & 0xFF, u->val1 & 0xFF,
- (u->val2 >> 8) & 0xFF, u->val2 & 0xFF );
- VG_(pp_UOperand)(u, 3, 4, True);
- break;
-
- case SSE3g1_RegWr:
- case SSE3e1_RegRd:
- case SSE3a1_MemRd:
- VG_(printf)("0x%x:0x%x:0x%x:0x%x:0x%x",
- (u->val1 >> 8) & 0xFF, u->val1 & 0xFF,
- (u->val2 >> 8) & 0xFF, u->val2 & 0xFF,
- u->lit32 );
- VG_(pp_UOperand)(u, 3, 4, True);
- break;
-
- case SSE3:
- VG_(printf)("0x%x:0x%x:0x%x",
- (u->val1 >> 8) & 0xFF, u->val1 & 0xFF,
- u->val2 & 0xFF );
- break;
-
- case SSE4:
- VG_(printf)("0x%x:0x%x:0x%x:0x%x",
- (u->val1 >> 8) & 0xFF, u->val1 & 0xFF,
- (u->val2 >> 8) & 0xFF, u->val2 & 0xFF );
- break;
-
- case SSE5:
- VG_(printf)("0x%x:0x%x:0x%x:0x%x:0x%x",
- (u->val1 >> 8) & 0xFF, u->val1 & 0xFF,
- (u->val2 >> 8) & 0xFF, u->val2 & 0xFF,
- u->val3 & 0xFF );
- break;
-
- case SSE3ag_MemRd_RegWr:
- VG_(printf)("0x%x(addr=", u->lit32 );
- VG_(pp_UOperand)(u, 1, 4, False);
- VG_(printf)(", dst=");
- VG_(pp_UOperand)(u, 2, 4, False);
- VG_(printf)(")");
- break;
-
- case GET: case PUT: case MOV: case LOAD: case STORE: case CMOV:
- case GETSEG: case PUTSEG:
- VG_(pp_UOperand)(u, 1, u->size, u->opcode==LOAD);
- VG_(printf)(", ");
- VG_(pp_UOperand)(u, 2, u->size, u->opcode==STORE);
- break;
-
- case JMP:
- VG_(pp_UOperand)(u, 1, u->size, False);
- if (CondAlways == u->cond) {
- /* Print x86 instruction size if filled in */
- if (0 != u->extra4b)
- VG_(printf)(" ($%u)", u->extra4b);
- }
- break;
-
- case GETF: case PUTF:
- case CC2VAL: case PUSH: case POP: case CLEAR: case CALLM:
- case NOT: case NEG: case INC: case DEC: case BSWAP:
- VG_(pp_UOperand)(u, 1, u->size, False);
- break;
-
- /* Print a "(s)" after args passed on stack */
- case CCALL:
- if (u->has_ret_val) {
- VG_(pp_UOperand)(u, 3, 0, False);
- VG_(printf)(" = ");
- }
- VG_(printf)("%p(", u->lit32);
- if (u->argc > 0) {
- VG_(pp_UOperand)(u, 1, 0, False);
- if (u->regparms_n < 1)
- VG_(printf)("(s)");
- }
- if (u->argc > 1) {
- VG_(printf)(", ");
- VG_(pp_UOperand)(u, 2, 0, False);
- if (u->regparms_n < 2)
- VG_(printf)("(s)");
- }
- if (u->argc > 2) {
- VG_(printf)(", ");
- VG_(pp_UOperand)(u, 3, 0, False);
- if (u->regparms_n < 3)
- VG_(printf)("(s)");
- }
- VG_(printf)(") ");
- break;
-
- case USESEG:
- case JIFZ:
- case ADD: case ADC: case AND: case OR:
- case XOR: case SUB: case SBB:
- case SHL: case SHR: case SAR:
- case ROL: case ROR: case RCL: case RCR:
- case MUL:
- VG_(pp_UOperand)(u, 1, u->size, False);
- VG_(printf)(", ");
- VG_(pp_UOperand)(u, 2, u->size, False);
- break;
-
- case WIDEN:
- VG_(pp_UOperand)(u, 1, u->size, False);
- break;
-
- default:
- if (VG_(needs).extended_UCode)
- TL_(pp_XUInstr)(u);
- else {
- VG_(printf)("unhandled opcode: %u. Perhaps "
- "VG_(needs).extended_UCode should be set?",
- u->opcode);
- VG_(core_panic)("pp_UInstr: unhandled opcode");
- }
- }
- if (u->flags_r != FlagsEmpty || u->flags_w != FlagsEmpty) {
- VG_(printf)(" (");
- if (u->flags_r != FlagsEmpty)
- vg_ppFlagSet("-r", u->flags_r);
- if (u->flags_w != FlagsEmpty)
- vg_ppFlagSet("-w", u->flags_w);
- VG_(printf)(")");
- }
-
- if (ppRegsLiveness) {
- VG_(printf)("\t\t");
- pp_realregs_liveness ( u );
- }
-
- VG_(printf)("\n");
-}
-
-void VG_(pp_UInstr) ( Int instrNo, UInstr* u )
-{
- pp_UInstrWorker ( instrNo, u, /*ppRegsLiveness*/False );
-}
-
-void VG_(pp_UInstr_regs) ( Int instrNo, UInstr* u )
-{
- pp_UInstrWorker ( instrNo, u, /*ppRegsLiveness*/True );
-}
-
-void VG_(pp_UCodeBlock) ( UCodeBlock* cb, Char* title )
-{
- Int i;
- VG_(printf)("%s\n", title);
- for (i = 0; i < cb->used; i++)
- if (cb->instrs[i].opcode != NOP)
- VG_(pp_UInstr) ( i, &cb->instrs[i] );
- VG_(printf)("\n");
-}
-
-
-/*------------------------------------------------------------*/
-/*--- uinstr helpers for register allocation ---*/
-/*--- and code improvement. ---*/
-/*------------------------------------------------------------*/
-
-/* Get the temp/reg use of a uinstr, parking them in an array supplied by
- the caller (regs), which is assumed to be big enough. Return the number
- of entries. Written regs are indicated in parallel array isWrites.
- Insns which read _and_ write a register wind up mentioning it twice.
- Entries are placed in the array in program order, so that if a reg is
- read-modified-written, it appears first as a read and then as a write.
- 'tag' indicates whether we are looking at TempRegs or RealRegs.
-*/
-Int VG_(get_reg_usage) ( UInstr* u, Tag tag, Int* regs, Bool* isWrites )
-{
-# define RD(ono) VG_UINSTR_READS_REG(ono, regs, isWrites)
-# define WR(ono) VG_UINSTR_WRITES_REG(ono, regs, isWrites)
-
- Int n = 0;
- switch (u->opcode) {
- case LEA1: RD(1); WR(2); break;
- case LEA2: RD(1); RD(2); WR(3); break;
-
- case SSE3a1_MemRd:
- case SSE2a1_MemRd:
- case SSE2e1_RegRd:
- case SSE3e_RegRd:
- case SSE3a_MemWr:
- case SSE3a_MemRd:
- case SSE2a_MemWr:
- case SSE3e1_RegRd:
- case SSE2a_MemRd: RD(3); break;
-
- case SSE2g_RegWr:
- case SSE2g1_RegWr:
- case SSE3e_RegWr:
- case SSE3g1_RegWr:
- case SSE3g_RegWr: WR(3); break;
-
- case SSE3ag_MemRd_RegWr: RD(1); WR(2); break;
-
- case MMX2a1_MemRd: RD(3); break;
- case MMX2_ERegRd: RD(2); break;
- case MMX2_ERegWr: WR(2); break;
-
- case SSE4: case SSE3: case SSE5:
- case MMX1: case MMX2: case MMX3:
- case NOP: case FPU: case INCEIP: case CALLM_S: case CALLM_E:
- case CLEAR: case CALLM: case LOCK: break;
-
- case CCALL:
- if (u->argc > 0) RD(1);
- if (u->argc > 1) RD(2);
- if (u->argc > 2) RD(3);
- if (u->has_ret_val) WR(3);
- break;
-
- case MMX2_MemRd: case MMX2_MemWr:
- case FPU_R: case FPU_W: RD(2); break;
-
- case GETSEG: WR(2); break;
- case PUTSEG: RD(1); break;
-
- case GETF: WR(1); break;
- case PUTF: RD(1); break;
-
- case GET: WR(2); break;
- case PUT: RD(1); break;
- case LOAD: RD(1); WR(2); break;
- case STORE: RD(1); RD(2); break;
- case MOV: RD(1); WR(2); break;
-
- case JMP: RD(1); break;
-
- case PUSH: RD(1); break;
- case POP: WR(1); break;
-
- case USESEG:
- case CMOV:
- case ADD: case ADC: case AND: case OR:
- case XOR: case SUB: case SBB:
- case MUL:
- RD(1); RD(2); WR(2); break;
-
- case SHL: case SHR: case SAR:
- case ROL: case ROR: case RCL: case RCR:
- RD(1); RD(2); WR(2); break;
-
- case NOT: case NEG: case INC: case DEC: case BSWAP:
- RD(1); WR(1); break;
-
- case WIDEN: RD(1); WR(1); break;
-
- case CC2VAL: WR(1); break;
- case JIFZ: RD(1); break;
-
- default:
- if (VG_(needs).extended_UCode)
- return TL_(get_Xreg_usage)(u, tag, regs, isWrites);
- else {
- VG_(printf)("unhandled opcode: %u. Perhaps "
- "VG_(needs).extended_UCode should be set?",
- u->opcode);
- VG_(core_panic)("VG_(get_reg_usage): unhandled opcode");
- }
- }
- return n;
-
-# undef RD
-# undef WR
-}
-
-
-/* Change temp regs in u into real regs, as directed by the
- * temps[i]-->reals[i] mapping. */
-static
-void patchUInstr ( UInstr* u, Int temps[], UInt reals[], Int n_tmap )
-{
- Int i;
- if (u->tag1 == TempReg) {
- for (i = 0; i < n_tmap; i++)
- if (temps[i] == u->val1) break;
- if (i == n_tmap) VG_(core_panic)("patchUInstr(1)");
- u->tag1 = RealReg;
- u->val1 = reals[i];
- }
- if (u->tag2 == TempReg) {
- for (i = 0; i < n_tmap; i++)
- if (temps[i] == u->val2) break;
- if (i == n_tmap) VG_(core_panic)("patchUInstr(2)");
- u->tag2 = RealReg;
- u->val2 = reals[i];
- }
- if (u->tag3 == TempReg) {
- for (i = 0; i < n_tmap; i++)
- if (temps[i] == u->val3) break;
- if (i == n_tmap) VG_(core_panic)("patchUInstr(3)");
- u->tag3 = RealReg;
- u->val3 = reals[i];
- }
-}
-
-
-/* Tedious x86-specific hack which compensates for the fact that the
- register numbers for %ah .. %dh do not correspond to those for %eax
- .. %edx. It maps a (reg size, reg no) pair to the number of the
- containing 32-bit reg. */
-static __inline__
-Int containingArchRegOf ( Int sz, Int aregno )
-{
- switch (sz) {
- case 4: return aregno;
- case 2: return aregno;
- case 1: return aregno >= 4 ? aregno-4 : aregno;
- default: VG_(core_panic)("containingArchRegOf");
- }
-}
-
-
-/* If u reads an ArchReg, return the number of the containing arch
- reg. Otherwise return -1. Used in redundant-PUT elimination.
- Note that this is not required for tools extending UCode because
- this happens before instrumentation. */
-static
-Int maybe_uinstrReadsArchReg ( UInstr* u )
-{
- switch (u->opcode) {
- case GET:
- case ADD: case ADC: case AND: case OR:
- case XOR: case SUB: case SBB:
- case SHL: case SHR: case SAR: case ROL:
- case ROR: case RCL: case RCR:
- case MUL:
- if (u->tag1 == ArchReg)
- return containingArchRegOf ( u->size, u->val1 );
- else
- return -1;
-
- case GETF: case PUTF:
- case CALLM_S: case CALLM_E:
- case INCEIP:
- case LEA1:
- case LEA2:
- case NOP:
- case LOCK:
- case PUT:
- case LOAD:
- case STORE:
- case MOV:
- case CMOV:
- case JMP:
- case CALLM: case CLEAR: case PUSH: case POP:
- case NOT: case NEG: case INC: case DEC: case BSWAP:
- case CC2VAL:
- case JIFZ:
- case FPU: case FPU_R: case FPU_W:
- case MMX1: case MMX2: case MMX3:
- case MMX2_MemRd: case MMX2_MemWr: case MMX2a1_MemRd:
- case MMX2_ERegRd: case MMX2_ERegWr:
- case SSE2a_MemWr: case SSE2a_MemRd: case SSE2a1_MemRd:
- case SSE2g_RegWr: case SSE2g1_RegWr: case SSE2e1_RegRd:
- case SSE3a_MemWr: case SSE3a_MemRd: case SSE3a1_MemRd:
- case SSE3e_RegRd: case SSE3g_RegWr: case SSE3e_RegWr:
- case SSE3g1_RegWr: case SSE3e1_RegRd:
- case SSE4: case SSE3: case SSE5: case SSE3ag_MemRd_RegWr:
- case WIDEN:
- /* GETSEG and USESEG are to do with ArchRegS, not ArchReg */
- case GETSEG: case PUTSEG:
- case USESEG:
- return -1;
-
- default:
- VG_(pp_UInstr)(0,u);
- VG_(core_panic)("maybe_uinstrReadsArchReg: unhandled opcode");
- }
-}
-
-static __inline__
-Bool uInstrMentionsTempReg ( UInstr* u, Int tempreg )
-{
- Int i, k;
- Int tempUse[VG_MAX_REGS_USED];
- Bool notUsed[VG_MAX_REGS_USED];
-
- k = VG_(get_reg_usage) ( u, TempReg, &tempUse[0], ¬Used[0] );
- for (i = 0; i < k; i++)
- if (tempUse[i] == tempreg)
- return True;
- return False;
-}
-
-
-/*------------------------------------------------------------*/
-/*--- ucode improvement. ---*/
-/*------------------------------------------------------------*/
-
-/* Improve the code in cb by doing
- -- Redundant ArchReg-fetch elimination
- -- Redundant PUT elimination
- -- Redundant cond-code restore/save elimination
- The overall effect of these is to allow target registers to be
- cached in host registers over multiple target insns.
-*/
-static void vg_improve ( UCodeBlock* cb )
-{
- Int i, j, k, m, n, ar, tr, told, actual_areg;
- Int areg_map[N_ARCH_REGS];
- Bool annul_put[N_ARCH_REGS];
- Int tempUse[VG_MAX_REGS_USED];
- Bool isWrites[VG_MAX_REGS_USED];
- UInstr* u;
- Bool wr;
- Int* last_live_before;
- FlagSet future_dead_flags;
-
- if (dis)
- VG_(printf) ("Improvements:\n");
-
- if (cb->nextTemp > 0)
- last_live_before = VG_(arena_malloc) ( VG_AR_JITTER,
- cb->nextTemp * sizeof(Int) );
- else
- last_live_before = NULL;
-
-
- /* PASS 1: redundant GET elimination. (Actually, more general than
- that -- eliminates redundant fetches of ArchRegs). */
-
- /* Find the live-range-ends for all temporaries. Duplicates code
- in the register allocator :-( */
-
- for (i = 0; i < cb->nextTemp; i++) last_live_before[i] = -1;
-
- for (i = cb->used-1; i >= 0; i--) {
- u = &cb->instrs[i];
-
- k = VG_(get_reg_usage)(u, TempReg, &tempUse[0], &isWrites[0]);
-
- /* For each temp usage ... bwds in program order. */
- for (j = k-1; j >= 0; j--) {
- tr = tempUse[j];
- wr = isWrites[j];
- if (last_live_before[tr] == -1) {
- vg_assert(tr >= 0 && tr < cb->nextTemp);
- last_live_before[tr] = wr ? (i+1) : i;
- }
- }
-
- }
-
-# define BIND_ARCH_TO_TEMP(archreg,tempreg)\
- { Int q; \
- /* Invalidate any old binding(s) to tempreg. */ \
- for (q = 0; q < N_ARCH_REGS; q++) \
- if (areg_map[q] == tempreg) areg_map[q] = -1; \
- /* Add the new binding. */ \
- areg_map[archreg] = (tempreg); \
- }
-
- /* Set up the A-reg map. */
- for (i = 0; i < N_ARCH_REGS; i++) areg_map[i] = -1;
-
- /* Scan insns. */
- for (i = 0; i < cb->used; i++) {
- u = &cb->instrs[i];
- if (u->opcode == GET && u->size == 4) {
- /* GET; see if it can be annulled. */
- vg_assert(u->tag1 == ArchReg);
- vg_assert(u->tag2 == TempReg);
- ar = u->val1;
- tr = u->val2;
- told = areg_map[ar];
- if (told != -1 && last_live_before[told] <= i) {
- /* ar already has an old mapping to told, but that runs
- out here. Annul this GET, rename tr to told for the
- rest of the block, and extend told's live range to that
- of tr. */
- VG_(new_NOP)(u);
- n = last_live_before[tr] + 1;
- if (n > cb->used) n = cb->used;
- last_live_before[told] = last_live_before[tr];
- last_live_before[tr] = i-1;
- if (dis)
- VG_(printf)(
- " at %2d: delete GET, rename t%d to t%d in (%d .. %d)\n",
- i, tr, told,i+1, n-1);
- for (m = i+1; m < n; m++) {
- if (cb->instrs[m].tag1 == TempReg
- && cb->instrs[m].val1 == tr)
- cb->instrs[m].val1 = told;
- if (cb->instrs[m].tag2 == TempReg
- && cb->instrs[m].val2 == tr)
- cb->instrs[m].val2 = told;
- if (cb->instrs[m].tag3 == TempReg
- && cb->instrs[m].val3 == tr)
- cb->instrs[m].val3 = told;
- }
- BIND_ARCH_TO_TEMP(ar,told);
- }
- else
- BIND_ARCH_TO_TEMP(ar,tr);
- }
- else if (u->opcode == GET && u->size != 4) {
- /* Invalidate any mapping for this archreg. */
- actual_areg = containingArchRegOf ( u->size, u->val1 );
- areg_map[actual_areg] = -1;
- }
- else if (u->opcode == PUT && u->size == 4) {
- /* PUT; re-establish t -> a binding */
- vg_assert(u->tag1 == TempReg);
- vg_assert(u->tag2 == ArchReg);
- BIND_ARCH_TO_TEMP(u->val2, u->val1);
- }
- else if (u->opcode == PUT && u->size != 4) {
- /* Invalidate any mapping for this archreg. */
- actual_areg = containingArchRegOf ( u->size, u->val2 );
- areg_map[actual_areg] = -1;
- } else {
-
- /* see if insn has an archreg as a read operand; if so try to
- map it. */
- if (u->tag1 == ArchReg && u->size == 4
- && areg_map[u->val1] != -1) {
- switch (u->opcode) {
- case ADD: case SUB: case AND: case OR: case XOR:
- case ADC: case SBB:
- case SHL: case SHR: case SAR: case ROL: case ROR:
- case RCL: case RCR:
- case MUL:
- if (dis)
- VG_(printf)(
- " at %2d: change ArchReg %S to TempReg t%d\n",
- i, nameIReg(4,u->val1), areg_map[u->val1]);
- u->tag1 = TempReg;
- u->val1 = areg_map[u->val1];
- /* Remember to extend the live range of the TempReg,
- if necessary. */
- if (last_live_before[u->val1] < i)
- last_live_before[u->val1] = i;
- break;
- default:
- break;
- }
- }
-
- /* boring insn; invalidate any mappings to temps it writes */
- k = VG_(get_reg_usage)(u, TempReg, &tempUse[0], &isWrites[0]);
-
- for (j = 0; j < k; j++) {
- wr = isWrites[j];
- if (!wr) continue;
- tr = tempUse[j];
- for (m = 0; m < N_ARCH_REGS; m++)
- if (areg_map[m] == tr) areg_map[m] = -1;
- }
- }
-
- }
-
-# undef BIND_ARCH_TO_TEMP
-
- /* PASS 2: redundant PUT elimination. Don't annul (delay) puts of
- %ESP, since the memory check machinery always requires the
- in-memory value of %ESP to be up to date. Although this isn't
- actually required by other analyses (cache simulation), it's
- simplest to be consistent for all end-uses. */
- for (j = 0; j < N_ARCH_REGS; j++)
- annul_put[j] = False;
-
- for (i = cb->used-1; i >= 0; i--) {
- u = &cb->instrs[i];
- if (u->opcode == NOP) continue;
-
- if (u->opcode == PUT && u->size == 4) {
- vg_assert(u->tag2 == ArchReg);
- actual_areg = containingArchRegOf ( 4, u->val2 );
- if (annul_put[actual_areg]) {
- vg_assert(actual_areg != R_ESP);
- VG_(new_NOP)(u);
- if (dis)
- VG_(printf)(" at %2d: delete PUT\n", i );
- } else {
- if (actual_areg != R_ESP)
- annul_put[actual_areg] = True;
- }
- }
- else if (u->opcode == PUT && u->size != 4) {
- actual_areg = containingArchRegOf ( u->size, u->val2 );
- annul_put[actual_areg] = False;
- }
- else if (u->opcode == JMP || u->opcode == JIFZ
- || u->opcode == CALLM) {
- for (j = 0; j < N_ARCH_REGS; j++)
- annul_put[j] = False;
- }
- else {
- /* If an instruction reads an ArchReg, the immediately
- preceding PUT cannot be annulled. */
- actual_areg = maybe_uinstrReadsArchReg ( u );
- if (actual_areg != -1)
- annul_put[actual_areg] = False;
- }
- }
-
- /* PASS 2a: redundant-move elimination. Given MOV t1, t2 and t1 is
- dead after this point, annul the MOV insn and rename t2 to t1.
- Further modifies the last_live_before map. */
-
-# if 0
- VG_(pp_UCodeBlock)(cb, "Before MOV elimination" );
- for (i = 0; i < cb->nextTemp; i++)
- VG_(printf)("llb[t%d]=%d ", i, last_live_before[i]);
- VG_(printf)("\n");
-# endif
-
- for (i = 0; i < cb->used-1; i++) {
- u = &cb->instrs[i];
- if (u->opcode != MOV) continue;
- if (u->tag1 == Literal) continue;
- vg_assert(u->tag1 == TempReg);
- vg_assert(u->tag2 == TempReg);
- if (last_live_before[u->val1] == i) {
- if (dis)
- VG_(printf)(
- " at %2d: delete MOV, rename t%d to t%d in (%d .. %d)\n",
- i, u->val2, u->val1, i+1, last_live_before[u->val2] );
- for (j = i+1; j <= last_live_before[u->val2]; j++) {
- if (cb->instrs[j].tag1 == TempReg
- && cb->instrs[j].val1 == u->val2)
- cb->instrs[j].val1 = u->val1;
- if (cb->instrs[j].tag2 == TempReg
- && cb->instrs[j].val2 == u->val2)
- cb->instrs[j].val2 = u->val1;
- if (cb->instrs[j].tag3 == TempReg
- && cb->instrs[j].val3 == u->val2)
- cb->instrs[j].val3 = u->val1;
- }
- last_live_before[u->val1] = last_live_before[u->val2];
- last_live_before[u->val2] = i-1;
- VG_(new_NOP)(u);
- }
- }
-
- /* PASS 3: redundant condition-code restore/save elimination.
- Scan backwards from the end. future_dead_flags records the set
- of flags which are dead at this point, that is, will be written
- before they are next read. Earlier uinsns which write flags
- already in future_dead_flags can have their writes annulled.
- */
- future_dead_flags = FlagsEmpty;
-
- for (i = cb->used-1; i >= 0; i--) {
- u = &cb->instrs[i];
-
- /* We might never make it to insns beyond this one, so be
- conservative. */
- if (u->opcode == JIFZ || u->opcode == JMP) {
- future_dead_flags = FlagsEmpty;
- continue;
- }
-
- /* PUTF modifies the %EFLAGS in essentially unpredictable ways.
- For example people try to mess with bit 21 to see if CPUID
- works. The setting may or may not actually take hold. So we
- play safe here. */
- if (u->opcode == PUTF) {
- future_dead_flags = FlagsEmpty;
- continue;
- }
-
- /* We can annul the flags written by this insn if it writes a
- subset (or eq) of the set of flags known to be dead after
- this insn. If not, just record the flags also written by
- this insn.*/
- if (u->flags_w != FlagsEmpty
- && VG_IS_FLAG_SUBSET(u->flags_w, future_dead_flags)) {
- if (dis) {
- VG_(printf)(" at %2d: annul flag write ", i);
- vg_ppFlagSet("", u->flags_w);
- VG_(printf)(" due to later ");
- vg_ppFlagSet("", future_dead_flags);
- VG_(printf)("\n");
- }
- u->flags_w = FlagsEmpty;
- } else {
- future_dead_flags
- = VG_UNION_FLAG_SETS ( u->flags_w, future_dead_flags );
- }
-
- /* If this insn also reads flags, empty out future_dead_flags so
- as to force preceding writes not to be annulled. */
- if (u->flags_r != FlagsEmpty)
- future_dead_flags = FlagsEmpty;
- }
-
- if (last_live_before)
- VG_(arena_free) ( VG_AR_JITTER, last_live_before );
-
- if (dis) {
- VG_(printf)("\n");
- VG_(pp_UCodeBlock) ( cb, "Improved UCode:" );
- }
-}
-
-/*------------------------------------------------------------*/
-/*--- %ESP-update pass ---*/
-/*------------------------------------------------------------*/
+/* NOTE: this comment is out of date */
/* For tools that want to know about %ESP changes, this pass adds
in the appropriate hooks. We have to do it after the tool's
the delta-is-unknown case. That case is also used when the delta is not
a nice small amount, or an unknown amount.
*/
-static
-UCodeBlock* vg_ESP_update_pass(UCodeBlock* cb_in)
-{
- UCodeBlock* cb;
- UInstr* u;
- Int delta = 0;
- UInt t_ESP = INVALID_TEMPREG;
- Int i;
-
- cb = VG_(setup_UCodeBlock)(cb_in);
-
- for (i = 0; i < VG_(get_num_instrs)(cb_in); i++) {
- u = VG_(get_instr)(cb_in, i);
-
- if (GET == u->opcode && R_ESP == u->val1) {
- t_ESP = u->val2;
- delta = 0;
-
- } else if (PUT == u->opcode && R_ESP == u->val2 && 4 == u->size) {
-
-# define DO_GENERIC \
- if (VG_(defined_new_mem_stack)() || \
- VG_(defined_die_mem_stack)()) { \
- uInstr1(cb, CCALL, 0, TempReg, u->val1); \
- uCCall(cb, (Addr) VG_(unknown_SP_update), \
- 1, 1, False); \
- }
-
-# define DO(kind, size) \
- if (VG_(defined_##kind##_mem_stack_##size)()) { \
- uInstr1(cb, CCALL, 0, TempReg, u->val1); \
- uCCall(cb, (Addr) VG_(tool_interface).track_##kind##_mem_stack_##size, \
- 1, 1, False); \
- \
- } else \
- DO_GENERIC \
- break
-
- if (u->val1 == t_ESP) {
- /* Known delta, common cases handled specially. */
- switch (delta) {
- case 0: break;
- case 4: DO(die, 4);
- case -4: DO(new, 4);
- case 8: DO(die, 8);
- case -8: DO(new, 8);
- case 12: DO(die, 12);
- case -12: DO(new, 12);
- case 16: DO(die, 16);
- case -16: DO(new, 16);
- case 32: DO(die, 32);
- case -32: DO(new, 32);
- default: DO_GENERIC; break;
- }
- } else {
- /* Unknown delta */
- DO_GENERIC;
-
- /* now we know the temp that points to %ESP */
- t_ESP = u->val1;
- }
- delta = 0;
-
-# undef DO
-# undef DO_GENERIC
-
- } else if (ADD == u->opcode && Literal == u->tag1 && t_ESP == u->val2) {
- delta += u->lit32;
-
- } else if (SUB == u->opcode && Literal == u->tag1 && t_ESP == u->val2) {
- delta -= u->lit32;
-
- } else if (MOV == u->opcode && TempReg == u->tag1 && t_ESP == u->val1 &&
- TempReg == u->tag2) {
- // t_ESP is transferred
- t_ESP = u->val2;
-
- } else {
- // Stop tracking t_ESP if it's clobbered by this instruction.
- Int tempUse [VG_MAX_REGS_USED];
- Bool isWrites[VG_MAX_REGS_USED];
- Int j, n = VG_(get_reg_usage)(u, TempReg, tempUse, isWrites);
-
- for (j = 0; j < n; j++) {
- if (tempUse[j] == t_ESP && isWrites[j])
- t_ESP = INVALID_TEMPREG;
- }
- }
- VG_(copy_UInstr) ( cb, u );
- }
-
- VG_(free_UCodeBlock)(cb_in);
- return cb;
-}
-
-/*------------------------------------------------------------*/
-/*--- The new register allocator. ---*/
-/*------------------------------------------------------------*/
-
-typedef
- struct {
- /* Becomes live for the first time after this insn ... */
- Int live_after;
- /* Becomes dead for the last time before this insn ... */
- Int dead_before;
- /* The "home" spill slot, if needed. Never changes. */
- Int spill_no;
- /* Where is it? VG_NOVALUE==in a spill slot; else in reg. */
- Int real_no;
- }
- TempInfo;
-
-
-/* Take a ucode block and allocate its TempRegs to RealRegs, or put
- them in spill locations, and add spill code, if there are not
- enough real regs. The usual register allocation deal, in short.
-
- Important redundancy of representation:
-
- real_to_temp maps real reg ranks (RRRs) to TempReg nos, or
- to VG_NOVALUE if the real reg has no currently assigned TempReg.
-
- The .real_no field of a TempInfo gives the current RRR for
- this TempReg, or VG_NOVALUE if the TempReg is currently
- in memory, in which case it is in the SpillNo denoted by
- spillno.
-
- These pieces of information (a fwds-bwds mapping, really) must
- be kept consistent!
-
- This allocator uses the so-called Second Chance Bin Packing
- algorithm, as described in "Quality and Speed in Linear-scan
- Register Allocation" (Traub, Holloway and Smith, ACM PLDI98,
- pp142-151). It is simple and fast and remarkably good at
- minimising the amount of spill code introduced.
-*/
static
-UCodeBlock* vg_do_register_allocation ( UCodeBlock* c1 )
-{
- TempInfo* temp_info;
- Int real_to_temp [VG_MAX_REALREGS];
- Bool is_spill_cand[VG_MAX_REALREGS];
- Int ss_busy_until_before[VG_MAX_SPILLSLOTS];
- Int i, j, k, m, r, tno, max_ss_no;
- Bool wr, defer, isRead, spill_reqd;
- UInt realUse [VG_MAX_REGS_USED];
- Int tempUse [VG_MAX_REGS_USED];
- Bool isWrites[VG_MAX_REGS_USED];
- UCodeBlock* c2;
-
- /* Used to denote ... well, "no value" in this fn. */
-# define VG_NOTHING (-2)
-
- /* Initialise the TempReg info. */
- if (c1->nextTemp > 0)
- temp_info = VG_(arena_malloc)(VG_AR_JITTER,
- c1->nextTemp * sizeof(TempInfo) );
- else
- temp_info = NULL;
-
- for (i = 0; i < c1->nextTemp; i++) {
- temp_info[i].live_after = VG_NOTHING;
- temp_info[i].dead_before = VG_NOTHING;
- temp_info[i].spill_no = VG_NOTHING;
- /* temp_info[i].real_no is not yet relevant. */
- }
+IRBB* vg_SP_update_pass ( IRBB* bb_in, VexGuestLayout* layout,
+ IRType hWordTy )
+{
+ Int i, j, minoff_ST, maxoff_ST;
+ IRDirty *dcall, *d;
+ IRStmt* st;
+ IRExpr* e;
+ IRArray* descr;
+
+ /* Set up BB */
+ IRBB* bb = emptyIRBB();
+ bb->tyenv = dopyIRTypeEnv(bb_in->tyenv);
+ bb->next = dopyIRExpr(bb_in->next);
+ bb->jumpkind = bb_in->jumpkind;
+
+ IRTemp curr = IRTemp_INVALID;
+ Long delta = 0;
+
+ Int sizeof_SP = layout->sizeof_SP;
+ Int offset_SP = layout->offset_SP;
+ IRType typeof_SP = sizeof_SP==4 ? Ity_I32 : Ity_I64;
+ vg_assert(sizeof_SP == 4 || sizeof_SP == 8);
+
+# define IS_ADD(op) (sizeof_SP==4 ? ((op)==Iop_Add32) : ((op)==Iop_Add64))
+# define IS_SUB(op) (sizeof_SP==4 ? ((op)==Iop_Sub32) : ((op)==Iop_Sub64))
+
+# define IS_ADD_OR_SUB(op) (IS_ADD(op) || IS_SUB(op))
+
+# define GET_CONST(con) \
+ (sizeof_SP==4 ? (Long)(Int)(con->Ico.U32) \
+ : (Long)(con->Ico.U64))
+
+# define DO(kind, syze) \
+ do { \
+ if (!VG_(defined_##kind##_mem_stack_##syze)()) \
+ goto generic; \
+ \
+ /* I don't know if it's really necessary to say that the */ \
+ /* call reads the stack pointer. But anyway, we do. */ \
+ dcall = unsafeIRDirty_0_N( \
+ 1/*regparms*/, \
+ "track_" #kind "_mem_stack_" #syze, \
+ VG_(tool_interface) \
+ .track_##kind##_mem_stack_##syze, \
+ mkIRExprVec_1(IRExpr_Tmp(curr)) \
+ ); \
+ dcall->nFxState = 1; \
+ dcall->fxState[0].fx = Ifx_Read; \
+ dcall->fxState[0].offset = layout->offset_SP; \
+ dcall->fxState[0].size = layout->sizeof_SP; \
+ \
+ addStmtToIRBB( bb, IRStmt_Dirty(dcall) ); \
+ } while (0)
+
+ for (i = 0; i < bb_in->stmts_used; i++) {
+
+ st = bb_in->stmts[i];
+ if (!st)
+ continue;
- spill_reqd = False;
-
- /* Scan fwds to establish live ranges. */
-
- for (i = 0; i < c1->used; i++) {
- k = VG_(get_reg_usage)(&c1->instrs[i], TempReg, &tempUse[0],
- &isWrites[0]);
- vg_assert(k >= 0 && k <= VG_MAX_REGS_USED);
-
- /* For each temp usage ... fwds in program order */
- for (j = 0; j < k; j++) {
- tno = tempUse[j];
- wr = isWrites[j];
- if (wr) {
- /* Writes hold a reg live until after this insn. */
- if (temp_info[tno].live_after == VG_NOTHING)
- temp_info[tno].live_after = i;
- if (temp_info[tno].dead_before < i + 1)
- temp_info[tno].dead_before = i + 1;
- } else {
- /* First use of a tmp should be a write. */
- if (temp_info[tno].live_after == VG_NOTHING) {
- VG_(printf)("At instr %d...\n", i);
- VG_(core_panic)("First use of tmp not a write,"
- " probably a tool instrumentation error");
- }
- /* Reads only hold it live until before this insn. */
- if (temp_info[tno].dead_before < i)
- temp_info[tno].dead_before = i;
+ /* t = Get(sp): curr = t, delta = 0 */
+ if (st->tag != Ist_Tmp) goto case2;
+ e = st->Ist.Tmp.data;
+ if (e->tag != Iex_Get) goto case2;
+ if (e->Iex.Get.offset != offset_SP) goto case2;
+ if (e->Iex.Get.ty != typeof_SP) goto case2;
+ curr = st->Ist.Tmp.tmp;
+ delta = 0;
+ addStmtToIRBB( bb, st );
+ continue;
+
+ case2:
+ /* t' = curr +/- const: curr = t', delta +=/-= const */
+ if (st->tag != Ist_Tmp) goto case3;
+ e = st->Ist.Tmp.data;
+ if (e->tag != Iex_Binop) goto case3;
+ if (e->Iex.Binop.arg1->tag != Iex_Tmp) goto case3;
+ if (e->Iex.Binop.arg1->Iex.Tmp.tmp != curr) goto case3;
+ if (e->Iex.Binop.arg2->tag != Iex_Const) goto case3;
+ if (!IS_ADD_OR_SUB(e->Iex.Binop.op)) goto case3;
+ curr = st->Ist.Tmp.tmp;
+ if (IS_ADD(e->Iex.Binop.op))
+ delta += GET_CONST(e->Iex.Binop.arg2->Iex.Const.con);
+ else
+ delta -= GET_CONST(e->Iex.Binop.arg2->Iex.Const.con);
+ addStmtToIRBB( bb, st );
+ continue;
+
+ case3:
+ /* t' = curr: curr = t' */
+ if (st->tag != Ist_Tmp) goto case4;
+ e = st->Ist.Tmp.data;
+ if (e->tag != Iex_Tmp) goto case4;
+ if (e->Iex.Tmp.tmp != curr) goto case4;
+ curr = st->Ist.Tmp.tmp;
+ addStmtToIRBB( bb, st );
+ continue;
+
+ case4:
+ /* Put(sp) = curr */
+ if (st->tag != Ist_Put) goto case5;
+ if (st->Ist.Put.offset != offset_SP) goto case5;
+ if (st->Ist.Put.data->tag != Iex_Tmp) goto case5;
+ if (st->Ist.Put.data->Iex.Tmp.tmp == curr) {
+ switch (delta) {
+ case 0: addStmtToIRBB(bb,st); delta = 0; continue;
+ case 4: DO(die, 4); addStmtToIRBB(bb,st); delta = 0; continue;
+ case -4: DO(new, 4); addStmtToIRBB(bb,st); delta = 0; continue;
+ case 8: DO(die, 8); addStmtToIRBB(bb,st); delta = 0; continue;
+ case -8: DO(new, 8); addStmtToIRBB(bb,st); delta = 0; continue;
+ case 12: DO(die, 12); addStmtToIRBB(bb,st); delta = 0; continue;
+ case -12: DO(new, 12); addStmtToIRBB(bb,st); delta = 0; continue;
+ case 16: DO(die, 16); addStmtToIRBB(bb,st); delta = 0; continue;
+ case -16: DO(new, 16); addStmtToIRBB(bb,st); delta = 0; continue;
+ case 32: DO(die, 32); addStmtToIRBB(bb,st); delta = 0; continue;
+ case -32: DO(new, 32); addStmtToIRBB(bb,st); delta = 0; continue;
+ default: goto generic;
}
- }
- }
-
-# if 0
- /* Sanity check on live ranges. Expensive but correct. */
- for (i = 0; i < c1->nextTemp; i++) {
- vg_assert( (temp_info[i].live_after == VG_NOTHING
- && temp_info[i].dead_before == VG_NOTHING)
- || (temp_info[i].live_after != VG_NOTHING
- && temp_info[i].dead_before != VG_NOTHING) );
- }
-# endif
-
- /* Do a rank-based allocation of TempRegs to spill slot numbers.
- We put as few as possible values in spill slots, but
- nevertheless need to have an assignment to them just in case. */
-
- max_ss_no = -1;
-
- for (i = 0; i < VG_MAX_SPILLSLOTS; i++)
- ss_busy_until_before[i] = 0;
-
- for (i = 0; i < c1->nextTemp; i++) {
-
- /* True iff this temp is unused. */
- if (temp_info[i].live_after == VG_NOTHING)
+ } else {
+ generic:
+ /* I don't know if it's really necessary to say that the call
+ reads the stack pointer. But anyway, we do. */
+ dcall = unsafeIRDirty_0_N(
+ 1/*regparms*/,
+ "VG_(unknown_SP_update)", &VG_(unknown_SP_update),
+ mkIRExprVec_1(st->Ist.Put.data)
+ );
+ dcall->nFxState = 1;
+ dcall->fxState[0].fx = Ifx_Read;
+ dcall->fxState[0].offset = layout->offset_SP;
+ dcall->fxState[0].size = layout->sizeof_SP;
+
+ addStmtToIRBB( bb, IRStmt_Dirty(dcall) );
+ addStmtToIRBB(bb,st);
+
+ curr = st->Ist.Put.data->Iex.Tmp.tmp;
+ delta = 0;
continue;
-
- /* Find the lowest-numbered spill slot which is available at the
- start point of this interval, and assign the interval to
- it. */
- for (j = 0; j < VG_MAX_SPILLSLOTS; j++)
- if (ss_busy_until_before[j] <= temp_info[i].live_after)
- break;
- if (j == VG_MAX_SPILLSLOTS) {
- VG_(printf)("VG_MAX_SPILLSLOTS is too low; increase and recompile.\n");
- VG_(core_panic)("register allocation failed -- out of spill slots");
}
- ss_busy_until_before[j] = temp_info[i].dead_before;
- temp_info[i].spill_no = j;
- if (j > max_ss_no)
- max_ss_no = j;
- }
-
- n_total_reg_rank += (max_ss_no+1);
-
- /* Show live ranges and assigned spill slot nos. */
-
- if (dis) {
- VG_(printf)("Live range assignments:\n");
- for (i = 0; i < c1->nextTemp; i++) {
- if (temp_info[i].live_after == VG_NOTHING)
- continue;
- VG_(printf)(
- " LR %d is after %d to before %d\tspillno %d\n",
- i,
- temp_info[i].live_after,
- temp_info[i].dead_before,
- temp_info[i].spill_no
- );
+ case5:
+ /* PutI or Dirty call which overlaps SP: complain. We can't
+ deal with SP changing in weird ways (well, we can, but not at
+ this time of night). */
+ if (st->tag == Ist_PutI) {
+ descr = st->Ist.PutI.descr;
+ minoff_ST = descr->base;
+ maxoff_ST = descr->base + descr->nElems * sizeofIRType(descr->elemTy) - 1;
+ if (!(offset_SP > maxoff_ST || (offset_SP + sizeof_SP - 1) < minoff_ST))
+ goto complain;
}
- VG_(printf)("\n");
- }
-
- /* Now that we've established a spill slot number for each used
- temporary, we can go ahead and do the core of the "Second-chance
- binpacking" allocation algorithm. */
-
- if (dis) VG_(printf)("Register allocated UCode:\n");
-
-
- /* Resulting code goes here. We generate it all in a forwards
- pass. */
- c2 = alloc_UCodeBlock( c1->orig_eip );
-
- /* At the start, no TempRegs are assigned to any real register.
- Correspondingly, all temps claim to be currently resident in
- their spill slots, as computed by the previous two passes. */
- for (i = 0; i < VG_MAX_REALREGS; i++)
- real_to_temp[i] = VG_NOTHING;
- for (i = 0; i < c1->nextTemp; i++)
- temp_info[i].real_no = VG_NOTHING;
-
- /* Process each insn in turn. */
- for (i = 0; i < c1->used; i++) {
-
- if (c1->instrs[i].opcode == NOP) continue;
- n_uinstrs_prealloc++;
-
-# if 0
- /* Check map consistency. Expensive but correct. */
- for (r = 0; r < VG_MAX_REALREGS; r++) {
- if (real_to_temp[r] != VG_NOTHING) {
- tno = real_to_temp[r];
- vg_assert(tno >= 0 && tno < c1->nextTemp);
- vg_assert(temp_info[tno].real_no == r);
- }
- }
- for (tno = 0; tno < c1->nextTemp; tno++) {
- if (temp_info[tno].real_no != VG_NOTHING) {
- r = temp_info[tno].real_no;
- vg_assert(r >= 0 && r < VG_MAX_REALREGS);
- vg_assert(real_to_temp[r] == tno);
+ if (st->tag == Ist_Dirty) {
+ d = st->Ist.Dirty.details;
+ for (j = 0; j < d->nFxState; j++) {
+ minoff_ST = d->fxState[j].offset;
+ maxoff_ST = d->fxState[j].offset + d->fxState[j].size - 1;
+ if (d->fxState[j].fx == Ifx_Read || d->fxState[j].fx == Ifx_None)
+ continue;
+ if (!(offset_SP > maxoff_ST || (offset_SP + sizeof_SP - 1) < minoff_ST))
+ goto complain;
}
}
-# endif
-
- if (dis)
- VG_(pp_UInstr)(i, &c1->instrs[i]);
-
- /* First, free up enough real regs for this insn. This may
- generate spill stores since we may have to evict some TempRegs
- currently in real regs. Also generates spill loads. */
-
- k = VG_(get_reg_usage)(&c1->instrs[i], TempReg, &tempUse[0],
- &isWrites[0]);
- vg_assert(k >= 0 && k <= VG_MAX_REGS_USED);
-
- /* For each ***different*** temp mentioned in the insn .... */
- for (j = 0; j < k; j++) {
-
- /* First check if the temp is mentioned again later; if so,
- ignore this mention. We only want to process each temp
- used by the insn once, even if it is mentioned more than
- once. */
- defer = False;
- tno = tempUse[j];
- for (m = j+1; m < k; m++)
- if (tempUse[m] == tno)
- defer = True;
- if (defer)
- continue;
-
- /* Now we're trying to find a register for tempUse[j].
- First of all, if it already has a register assigned, we
- don't need to do anything more. */
- if (temp_info[tno].real_no != VG_NOTHING)
- continue;
-
- /* No luck. The next thing to do is see if there is a
- currently unassigned register available. If so, bag it. */
- for (r = 0; r < VG_MAX_REALREGS; r++) {
- if (real_to_temp[r] == VG_NOTHING)
- break;
- }
- if (r < VG_MAX_REALREGS) {
- real_to_temp[r] = tno;
- temp_info[tno].real_no = r;
- continue;
- }
- /* Unfortunately, that didn't pan out either. So we'll have
- to eject some other unfortunate TempReg into a spill slot
- in order to free up a register. Of course, we need to be
- careful not to eject some other TempReg needed by this
- insn.
-
- Select r in 0 .. VG_MAX_REALREGS-1 such that
- real_to_temp[r] is not mentioned in
- tempUse[0 .. k-1], since it would be just plain
- wrong to eject some other TempReg which we need to use in
- this insn.
-
- It is here that it is important to make a good choice of
- register to spill. */
-
- /* First, mark those regs which are not spill candidates. */
- for (r = 0; r < VG_MAX_REALREGS; r++) {
- is_spill_cand[r] = True;
- for (m = 0; m < k; m++) {
- if (real_to_temp[r] == tempUse[m]) {
- is_spill_cand[r] = False;
- break;
- }
- }
- }
-
- /* We can choose any r satisfying is_spill_cand[r]. However,
- try to make a good choice. First, try and find r such
- that the associated TempReg is already dead. */
- for (r = 0; r < VG_MAX_REALREGS; r++) {
- if (is_spill_cand[r] &&
- temp_info[real_to_temp[r]].dead_before <= i)
- goto have_spill_cand;
- }
+ /* well, not interesting. Just copy and keep going. */
+ addStmtToIRBB( bb, st );
- /* No spill cand is mapped to a dead TempReg. Now we really
- _do_ have to generate spill code. Choose r so that the
- next use of its associated TempReg is as far ahead as
- possible, in the hope that this will minimise the number of
- consequent reloads required. This is a bit expensive, but
- we don't have to do it very often. */
- {
- Int furthest_r = VG_MAX_REALREGS;
- Int furthest = 0;
- for (r = 0; r < VG_MAX_REALREGS; r++) {
- if (!is_spill_cand[r]) continue;
- for (m = i+1; m < c1->used; m++)
- if (uInstrMentionsTempReg(&c1->instrs[m],
- real_to_temp[r]))
- break;
- if (m > furthest) {
- furthest = m;
- furthest_r = r;
- }
- }
- r = furthest_r;
- goto have_spill_cand;
- }
+ } /* for (i = 0; i < bb_in->stmts_used; i++) */
- have_spill_cand:
- if (r == VG_MAX_REALREGS)
- VG_(core_panic)("new reg alloc: out of registers ?!");
-
- /* Eject r. Important refinement: don't bother if the
- associated TempReg is now dead. */
- vg_assert(real_to_temp[r] != VG_NOTHING);
- vg_assert(real_to_temp[r] != tno);
- temp_info[real_to_temp[r]].real_no = VG_NOTHING;
- if (temp_info[real_to_temp[r]].dead_before > i) {
- uInstr2(c2, PUT, 4,
- RealReg, VG_(rank_to_realreg)(r),
- SpillNo, temp_info[real_to_temp[r]].spill_no);
- n_uinstrs_spill++;
- spill_reqd = True;
- if (dis)
- VG_(pp_UInstr)(c2->used-1, &LAST_UINSTR(c2));
- }
+ return bb;
- /* Decide if tno is read. */
- isRead = False;
- for (m = 0; m < k; m++)
- if (tempUse[m] == tno && !isWrites[m])
- isRead = True;
-
- /* If so, generate a spill load. */
- if (isRead) {
- uInstr2(c2, GET, 4,
- SpillNo, temp_info[tno].spill_no,
- RealReg, VG_(rank_to_realreg)(r) );
- n_uinstrs_spill++;
- spill_reqd = True;
- if (dis)
- VG_(pp_UInstr)(c2->used-1, &LAST_UINSTR(c2));
- }
+ complain:
+ VG_(core_panic)("vg_SP_update_pass: PutI or Dirty which overlaps SP");
- /* Update the forwards and backwards maps. */
- real_to_temp[r] = tno;
- temp_info[tno].real_no = r;
- }
+}
- /* By this point, all TempRegs mentioned by the insn have been
- bought into real regs. We now copy the insn to the output
- and use patchUInstr to convert its rTempRegs into
- realregs. */
- for (j = 0; j < k; j++)
- realUse[j] = VG_(rank_to_realreg)(temp_info[tempUse[j]].real_no);
- VG_(copy_UInstr)(c2, &c1->instrs[i]);
- patchUInstr(&LAST_UINSTR(c2), &tempUse[0], &realUse[0], k);
-
- if (dis) {
- VG_(pp_UInstr)(c2->used-1, &LAST_UINSTR(c2));
- VG_(printf)("\n");
- }
- }
- if (temp_info != NULL)
- VG_(arena_free)(VG_AR_JITTER, temp_info);
- VG_(free_UCodeBlock)(c1);
+#if 0
+ for (i = 0; i < bb_in->stmts_used; i++) {
+ st = bb_in->stmts[i];
+ if (!st)
+ continue;
+ if (st->tag != Ist_Put)
+ goto boring;
+ offP = st->Ist.Put.offset;
+ if (offP != layout->offset_SP)
+ goto boring;
+ szP = sizeofIRType(typeOfIRExpr(bb_in->tyenv, st->Ist.Put.data));
+ if (szP != layout->sizeof_SP)
+ goto boring;
+ vg_assert(isAtom(st->Ist.Put.data));
+
+ /* I don't know if it's really necessary to say that the call reads
+ the stack pointer. But anyway, we do. */
+ dcall = unsafeIRDirty_0_N(
+ mkIRCallee(1, "VG_(unknown_esp_update)",
+ (HWord)&VG_(unknown_esp_update)),
+ mkIRExprVec_1(st->Ist.Put.data)
+ );
+ dcall->nFxState = 1;
+ dcall->fxState[0].fx = Ifx_Read;
+ dcall->fxState[0].offset = layout->offset_SP;
+ dcall->fxState[0].size = layout->sizeof_SP;
+
+ addStmtToIRBB( bb, IRStmt_Dirty(dcall) );
+
+ boring:
+ addStmtToIRBB( bb, st );
+ }
+#endif
- if (spill_reqd)
- n_translations_needing_spill++;
- return c2;
+/*------------------------------------------------------------*/
+/*--- Main entry point for the JITter. ---*/
+/*------------------------------------------------------------*/
-# undef VG_NOTHING
+/* Vex dumps the final code in here. Then we can copy it off
+ wherever we like. */
+#define N_TMPBUF 10000
+static UChar tmpbuf[N_TMPBUF];
+/* Function pointers we must supply to LibVEX in order that it
+ can bomb out and emit messages under Valgrind's control. */
+__attribute__ ((noreturn))
+static
+void failure_exit ( void )
+{
+ LibVEX_ClearTemporary(True);
+ VG_(printf)("VEX did failure_exit. Bye.\n");
+ vg_assert(0); //VG_(exit)(1);
}
-/* Analysis records liveness of all general-use RealRegs in the UCode. */
-static void vg_realreg_liveness_analysis ( UCodeBlock* cb )
-{
- Int i, j, k;
- RRegSet rregs_live;
- Int regUse[VG_MAX_REGS_USED];
- Bool isWrites[VG_MAX_REGS_USED];
- UInstr* u;
-
- /* All regs are dead at the end of the block */
- rregs_live = ALL_RREGS_DEAD;
-
- for (i = cb->used-1; i >= 0; i--) {
- u = &cb->instrs[i];
-
- u->regs_live_after = rregs_live;
-
- k = VG_(get_reg_usage)(u, RealReg, ®Use[0], &isWrites[0]);
-
- /* For each reg usage ... bwds in program order. Variable is live
- before this UInstr if it is read by this UInstr.
- Note that regUse[j] holds the Intel reg number, so we must
- convert it to our rank number. */
- for (j = k-1; j >= 0; j--) {
- SET_RREG_LIVENESS ( VG_(realreg_to_rank)(regUse[j]),
- rregs_live,
- !isWrites[j] );
- }
- }
+static
+void log_bytes ( Char* bytes, Int nbytes )
+{
+ Int i;
+ for (i = 0; i < nbytes-3; i += 4)
+ VG_(printf)("%c%c%c%c", bytes[i], bytes[i+1], bytes[i+2], bytes[i+3]);
+ for (; i < nbytes; i++)
+ VG_(printf)("%c", bytes[i]);
}
-/*------------------------------------------------------------*/
-/*--- Main entry point for the JITter. ---*/
-/*------------------------------------------------------------*/
-
/* Translate the basic block beginning at orig_addr, and add it to
the translation cache & translation table. Unless 'debugging' is true,
in which case the call is being done for debugging purposes, so
'tid' is the identity of the thread needing this block.
*/
+
+/* This stops Vex from chasing into function entry points that we wish
+ to redirect. Chasing across them obviously defeats the redirect
+ mechanism, with bad effects for Memcheck, Addrcheck, and possibly
+ others. */
+static Bool chase_into_ok ( Addr64 addr64 )
+{
+ Addr addr = (Addr)addr64;
+ if (addr != VG_(code_redirect)(addr)) {
+ if (0) VG_(printf)("not chasing into 0x%x\n", addr);
+ return False;
+ } else {
+ return True; /* ok to chase into 'addr' */
+ }
+}
+
Bool VG_(translate) ( ThreadId tid, Addr orig_addr,
Bool debugging_translation )
{
- Addr trans_addr, redir, orig_addr0 = orig_addr;
- UShort jumps[VG_MAX_JUMPS];
- Int i, orig_size, trans_size;
- UCodeBlock* cb;
+ Addr redir, orig_addr0 = orig_addr;
+ Int orig_size, tmpbuf_used;
Bool notrace_until_done;
UInt notrace_until_limit = 0;
+ //UInt FULLTRACE_LIMIT = 1; //21068;
Segment *seg;
- VGP_PUSHCC(VgpTranslate);
+ /* Make sure Vex is initialised right. */
+ TranslateResult tres;
+ static Bool vex_init_done = False;
- beforeRA = True;
- beforeLiveness = True;
+ if (!vex_init_done) {
+ LibVEX_Init ( &failure_exit, &log_bytes,
+ 1, /* debug_paranoia */
+ False, /* valgrind support */
+ &VG_(clo_vex_control) );
+ vex_init_done = True;
+ }
- for (i = 0; i < VG_MAX_JUMPS; i++)
- jumps[i] = (UShort)-1;
+ /* profiling ... */
+ VGP_PUSHCC(VgpTranslate);
/* Look in the code redirect table to see if we should
translate an alternative address for orig_addr. */
redir = VG_(code_redirect)(orig_addr);
if (redir != orig_addr && VG_(clo_verbosity) >= 2) {
+ Char name1[64] = "";
+ Char name2[64] = "";
+ VG_(get_fnname_w_offset)(orig_addr, name1, 64);
+ VG_(get_fnname_w_offset)(redir, name2, 64);
VG_(message)(Vg_UserMsg,
- "TRANSLATE: %p redirected to %p",
- orig_addr,
- redir );
+ "TRANSLATE: %p (%s) redirected to %p (%s)",
+ orig_addr, name1,
+ redir, name2 );
}
orig_addr = redir;
vg_assert(!VG_(is_addressable)(orig_addr, 1));
if (seg != NULL && VG_(seg_contains)(seg, orig_addr, 1)) {
- vg_assert((seg->prot & VKI_PROT_EXEC) == 0);
- VG_(synth_fault_perms)(tid, orig_addr);
+ vg_assert((seg->prot & VKI_PROT_EXEC) == 0);
+ VG_(synth_fault_perms)(tid, orig_addr);
} else
- VG_(synth_fault_mapping)(tid, orig_addr);
+ VG_(synth_fault_mapping)(tid, orig_addr);
return False;
} else
- seg->flags |= SF_CODE; /* contains cached code */
-
- cb = alloc_UCodeBlock( orig_addr );
+ seg->flags |= SF_CODE; /* contains cached code */
/* If doing any code printing, print a basic block start marker */
- if (VG_(clo_trace_codegen) && notrace_until_done) {
+ if (VG_(clo_trace_codegen)) {
Char fnname[64] = "";
- VG_(get_fnname_if_entry)(orig_addr, fnname, 64);
+ VG_(get_fnname_w_offset)(orig_addr, fnname, 64);
VG_(printf)(
- "==== BB %d %s(%p) approx BBs exec'd %llu ====\n\n",
+ "==== BB %d %s(%p) approx BBs exec'd %llu ====\n",
VG_(get_bbs_translated)(), fnname, orig_addr,
VG_(bbs_done));
}
/* True if a debug trans., or if bit N set in VG_(clo_trace_codegen). */
+#if 0
# define DECIDE_IF_PRINTING_CODEGEN_FOR_PHASE(n) \
( debugging_translation \
|| (notrace_until_done \
&& (VG_(clo_trace_codegen) & (1 << (n-1))) ))
+#else
+# define DECIDE_IF_PRINTING_CODEGEN \
+ ( debugging_translation \
+ || (VG_(clo_trace_codegen) > 0 \
+ && VG_(get_bbs_translated)() >= FULLTRACE_LIMIT))
+#endif
- /* Disassemble this basic block into cb. */
- VG_(print_codegen) = DECIDE_IF_PRINTING_CODEGEN_FOR_PHASE(1);
- VGP_PUSHCC(VgpToUCode);
- orig_size = VG_(disBB) ( cb, orig_addr );
- sanity_check_UCodeBlock ( cb );
- // Only sanity-check calls now because tools might remove the
- // CALLM_[ES] pairs.
- sanity_check_UCodeBlockCalls ( cb );
- VGP_POPCC(VgpToUCode);
-
- /* Try and improve the code a bit. */
- if (VG_(clo_optimise)) {
- VG_(print_codegen) = DECIDE_IF_PRINTING_CODEGEN_FOR_PHASE(2);
- VGP_PUSHCC(VgpImprove);
- vg_improve ( cb );
- VGP_POPCC(VgpImprove);
- }
-
- /* Tool's instrumentation (Nb: must set VG_(print_codegen) in case
- TL_(instrument) looks at it. */
- VG_(print_codegen) = DECIDE_IF_PRINTING_CODEGEN_FOR_PHASE(3);
- VGP_PUSHCC(VgpInstrument);
- cb = TL_(instrument) ( cb, orig_addr );
- if (VG_(print_codegen))
- VG_(pp_UCodeBlock) ( cb, "Instrumented UCode:" );
- sanity_check_UCodeBlock( cb );
- VGP_POPCC(VgpInstrument);
-
- /* Add %ESP-update hooks if the tool requires them */
- /* Nb: We don't print out this phase, because it doesn't do much */
- if (VG_(need_to_handle_SP_assignment)()) {
- VGP_PUSHCC(VgpESPUpdate);
- cb = vg_ESP_update_pass ( cb );
- VGP_POPCC(VgpESPUpdate);
- }
-
- /* Allocate registers. */
- VG_(print_codegen) = DECIDE_IF_PRINTING_CODEGEN_FOR_PHASE(4);
- VGP_PUSHCC(VgpRegAlloc);
- cb = vg_do_register_allocation ( cb );
- beforeRA = False;
- VGP_POPCC(VgpRegAlloc);
-
- /* Do post reg-alloc %e[acd]x liveness analysis (too boring to print
- * anything; results can be seen when emitting final code). */
- VGP_PUSHCC(VgpLiveness);
- vg_realreg_liveness_analysis ( cb );
- beforeLiveness = False;
- VGP_POPCC(VgpLiveness);
-
- /* Emit final code */
- VG_(print_codegen) = DECIDE_IF_PRINTING_CODEGEN_FOR_PHASE(5);
- VGP_PUSHCC(VgpFromUcode);
- trans_addr = (Addr)VG_(emit_code)(cb, &trans_size, jumps );
- VGP_POPCC(VgpFromUcode);
- VG_(free_UCodeBlock)(cb);
+ /* Actually do the translation. */
+ tres = LibVEX_Translate (
+ InsnSetX86, InsnSetX86,
+ (Char*)orig_addr, (Addr64)orig_addr,
+ chase_into_ok,
+ &orig_size,
+ tmpbuf, N_TMPBUF, &tmpbuf_used,
+ TL_(instrument),
+ VG_(need_to_handle_SP_assignment)()
+ ? vg_SP_update_pass
+ : NULL,
+ True, /* cleanup after instrumentation */
+ NULL,
+ VG_(clo_trace_codegen)
+ );
+
+ vg_assert(tres == TransOK);
+ vg_assert(tmpbuf_used <= N_TMPBUF);
+ vg_assert(tmpbuf_used > 0);
#undef DECIDE_IF_PRINTING_CODEGEN_FOR_PHASE
/* Copy data at trans_addr into the translation cache. */
/* Since the .orig_size and .trans_size fields are UShort, be paranoid. */
- vg_assert(orig_size > 0 && orig_size < 65536);
- vg_assert(trans_size > 0 && trans_size < 65536);
+ vg_assert(orig_size > 0 && orig_size < 65536);
+ vg_assert(tmpbuf_used > 0 && tmpbuf_used < 65536);
// If debugging, don't do anything with the translated block; we
// only did this for the debugging output produced along the way.
if (!debugging_translation) {
// Note that we use orig_addr0, not orig_addr, which might have been
// changed by the redirection
- VG_(add_to_trans_tab)( orig_addr0, orig_size, trans_addr, trans_size,
- jumps );
+ VG_(add_to_trans_tab)( orig_addr0, orig_size,
+ (Addr)(&tmpbuf[0]), tmpbuf_used );
}
- /* Free the intermediary -- was allocated by VG_(emit_code). */
- VG_(arena_free)( VG_AR_JITTER, (void*)trans_addr );
-
VGP_POPCC(VgpTranslate);
return True;
}
-
/*--------------------------------------------------------------------*/
/*--- end vg_translate.c ---*/
/*--------------------------------------------------------------------*/
/*------------------ T-CHAINING HELPERS ------------------*/
-
+#if 0
static
void for_each_jumpsite(TCEntry *tce, void (*fn)(Addr))
{
for_each_tc(s, unchain_tce_for_sector);
}
-
+#endif
/*------------------ TT HELPERS ------------------*/
Char msg[100];
Int s = find_oldest_sector();
if (s != -1) {
- Int i;
+ //Int i;
vg_assert(s >= 0 && s < VG_TC_N_SECTORS);
VG_(sprintf)(msg, "before discard of sector %d (%d bytes)",
s, vg_tc_used[s]);
- for(i = 0; i < VG_TC_N_SECTORS; i++) {
- if (i != s && vg_tc[i] != NULL)
- unchain_sector(i, (Addr)vg_tc[s], vg_tc_used[s]);
- }
+ //for(i = 0; i < VG_TC_N_SECTORS; i++) {
+ // if (i != s && vg_tc[i] != NULL)
+ // unchain_sector(i, (Addr)vg_tc[s], vg_tc_used[s]);
+ // }
pp_tt_tc_status ( msg );
overall_out_count += vg_tc_stats_count[s];
pointer, which is inserted here.
*/
void VG_(add_to_trans_tab) ( Addr orig_addr, Int orig_size,
- Addr trans_addr, Int trans_size,
- UShort jumps[VG_MAX_JUMPS])
+ Addr trans_addr, Int trans_size )
{
Int i, nBytes, trans_size_aligned;
TCEntry* tce;
tce->orig_addr = orig_addr;
tce->orig_size = (UShort)orig_size; /* what's the point of storing this? */
tce->trans_size = (UShort)trans_size_aligned;
- for (i = 0; i < VG_MAX_JUMPS; i++) {
- tce->jump_sites[i] = jumps[i];
- }
for (i = 0; i < trans_size; i++) {
tce->payload[i] = ((UChar*)trans_addr)[i];
}
- unchain_tce(tce);
+ //unchain_tce(tce);
add_tt_entry(tce);
/* Update stats. */
{
Addr i_start, i_end, o_start, o_end;
UInt out_count, out_osize, out_tsize;
- Int i, j;
+ Int i; //, j;
TCEntry* tce;
# ifdef DEBUG_TRANSTAB
VG_(sanity_check_tt_tc)();
vg_tt[i].orig_addr = VG_TTE_DELETED;
tce->orig_addr = VG_TTE_DELETED;
- if (unchain_blocks) {
- /* make sure no other blocks chain to the one we just discarded */
- for(j = 0; j < VG_TC_N_SECTORS; j++) {
- if (vg_tc[j] != NULL)
- unchain_sector(j, (Addr)tce->payload, tce->trans_size);
- }
- }
+ // if (unchain_blocks) {
+ // /* make sure no other blocks chain to the one we just discarded */
+ // for(j = 0; j < VG_TC_N_SECTORS; j++) {
+ // if (vg_tc[j] != NULL)
+ // unchain_sector(j, (Addr)tce->payload, tce->trans_size);
+ // }
+ // }
overall_out_count ++;
overall_out_osize += tce->orig_size;
------------------------------------------------------------------ */
// Accessors for the arch_thread_t
-#define PLATFORM_SYSCALL_NUM(regs) ((regs).m_eax)
-#define PLATFORM_SYSCALL_RET(regs) ((regs).m_eax)
-#define PLATFORM_SYSCALL_ARG1(regs) ((regs).m_ebx)
-#define PLATFORM_SYSCALL_ARG2(regs) ((regs).m_ecx)
-#define PLATFORM_SYSCALL_ARG3(regs) ((regs).m_edx)
-#define PLATFORM_SYSCALL_ARG4(regs) ((regs).m_esi)
-#define PLATFORM_SYSCALL_ARG5(regs) ((regs).m_edi)
-#define PLATFORM_SYSCALL_ARG6(regs) ((regs).m_ebp)
-
-#define PLATFORM_SET_SYSCALL_RESULT(regs, val) ((regs).m_eax = (val))
+#define PLATFORM_SYSCALL_NUM(regs) ((regs).vex.guest_EAX)
+#define PLATFORM_SYSCALL_RET(regs) ((regs).vex.guest_EAX)
+#define PLATFORM_SYSCALL_ARG1(regs) ((regs).vex.guest_EBX)
+#define PLATFORM_SYSCALL_ARG2(regs) ((regs).vex.guest_ECX)
+#define PLATFORM_SYSCALL_ARG3(regs) ((regs).vex.guest_EDX)
+#define PLATFORM_SYSCALL_ARG4(regs) ((regs).vex.guest_ESI)
+#define PLATFORM_SYSCALL_ARG5(regs) ((regs).vex.guest_EDI)
+#define PLATFORM_SYSCALL_ARG6(regs) ((regs).vex.guest_EBP)
+
+#define PLATFORM_SET_SYSCALL_RESULT(regs, val) \
+ ((regs).vex.guest_EAX = (val))
// Interesting register numbers
#define R_SYSCALL_NUM R_EAX
void VGA_(thread_syscall)(Int syscallno, arch_thread_t *arch,
enum PXState *state , enum PXState poststate)
{
- do_thread_syscall(syscallno, // syscall no.
- arch->m_ebx, // arg 1
- arch->m_ecx, // arg 2
- arch->m_edx, // arg 3
- arch->m_esi, // arg 4
- arch->m_edi, // arg 5
- arch->m_ebp, // arg 6
- &arch->m_eax, // result
+ do_thread_syscall(syscallno, // syscall no.
+ arch->vex.guest_EBX, // arg 1
+ arch->vex.guest_ECX, // arg 2
+ arch->vex.guest_EDX, // arg 3
+ arch->vex.guest_ESI, // arg 4
+ arch->vex.guest_EDI, // arg 5
+ arch->vex.guest_EBP, // arg 6
+ &arch->vex.guest_EAX, // result
state, // state to update
poststate); // state when syscall has finished
}
// Back up to restart a system call.
void VGA_(restart_syscall)(arch_thread_t *arch)
{
- arch->m_eip -= 2; // sizeof(int $0x80)
+ arch->vex.guest_EIP -= 2; // sizeof(int $0x80)
/* Make sure our caller is actually sane, and we're really backing
back over a syscall.
int $0x80 == CD 80
*/
{
- UChar *p = (UChar *)arch->m_eip;
+ UChar *p = (UChar *)arch->vex.guest_EIP;
if (p[0] != 0xcd || p[1] != 0x80)
VG_(message)(Vg_DebugMsg,
"?! restarting over syscall at %p %02x %02x\n",
- arch->m_eip, p[0], p[1]);
+ arch->vex.guest_EIP, p[0], p[1]);
vg_assert(p[0] == 0xcd && p[1] == 0x80);
}
#include "core_arch_asm.h" // arch-specific asm stuff
#include "tool_arch.h" // arch-specific tool stuff
+#include "libvex_guest_x86.h"
+
+
/* ---------------------------------------------------------------------
Interesting registers
------------------------------------------------------------------ */
+/* Generate a pointer into baseBlock via which we can prod the
+ Vex guest state. */
+#define BASEBLOCK_VEX \
+ ((VexGuestX86State*)(&VG_(baseBlock)[VGOFF_(m_vex)]))
+
+/* Ditto the Vex shadow guest state. */
+#define BASEBLOCK_VEX_SHADOW \
+ ((VexGuestX86State*)(&VG_(baseBlock)[VGOFF_(m_vex_shadow)]))
+
// Accessors for the arch_thread_t
-#define ARCH_INSTR_PTR(regs) ((regs).m_eip)
-#define ARCH_STACK_PTR(regs) ((regs).m_esp)
-#define ARCH_FRAME_PTR(regs) ((regs).m_ebp)
+#define ARCH_INSTR_PTR(regs) ((regs).vex.guest_EIP)
+#define ARCH_STACK_PTR(regs) ((regs).vex.guest_ESP)
+#define ARCH_FRAME_PTR(regs) ((regs).vex.guest_EBP)
-#define ARCH_CLREQ_ARGS(regs) ((regs).m_eax)
-#define ARCH_PTHREQ_RET(regs) ((regs).m_edx)
-#define ARCH_CLREQ_RET(regs) ((regs).m_edx)
+#define ARCH_CLREQ_ARGS(regs) ((regs).vex.guest_EAX)
+#define ARCH_PTHREQ_RET(regs) ((regs).vex.guest_EDX)
+#define ARCH_CLREQ_RET(regs) ((regs).vex.guest_EDX)
// Accessors for the baseBlock
+#define R_STACK_PTR R_ESP
+#define R_FRAME_PTR R_EBP
+
#define R_CLREQ_RET R_EDX
#define R_PTHREQ_RET R_EDX
// Stack frame layout and linkage
#define FIRST_STACK_FRAME(ebp) (ebp)
-#define STACK_FRAME_RET(ebp) (((UWord*)ebp)[1])
-#define STACK_FRAME_NEXT(ebp) (((UWord*)ebp)[0])
+#define STACK_FRAME_RET(ebp) (((UInt*)ebp)[1])
+#define STACK_FRAME_NEXT(ebp) (((UInt*)ebp)[0])
-// Offsets of interesting registers
-#define VGOFF_INSTR_PTR VGOFF_(m_eip)
-#define VGOFF_STACK_PTR VGOFF_(m_esp)
-#define VGOFF_FRAME_PTR VGOFF_(m_ebp)
+// Baseblock access to interesting registers
+#define BASEBLOCK_INSTR_PTR BASEBLOCK_VEX->guest_EIP
+#define BASEBLOCK_STACK_PTR BASEBLOCK_VEX->guest_ESP
+#define BASEBLOCK_FRAME_PTR BASEBLOCK_VEX->guest_EBP
// Get stack pointer and frame pointer
#define ARCH_GET_REAL_STACK_PTR(esp) do { \
-------------------------------------------------- */
/* State of the simulated CPU. */
-extern Int VGOFF_(m_eax);
-extern Int VGOFF_(m_ecx);
-extern Int VGOFF_(m_edx);
-extern Int VGOFF_(m_ebx);
-extern Int VGOFF_(m_esp);
-extern Int VGOFF_(m_ebp);
-extern Int VGOFF_(m_esi);
-extern Int VGOFF_(m_edi);
-extern Int VGOFF_(m_eflags);
-extern Int VGOFF_(m_ssestate);
-extern Int VGOFF_(m_eip);
-
-extern Int VGOFF_(m_dflag); /* D flag is handled specially */
-
-extern Int VGOFF_(m_cs);
-extern Int VGOFF_(m_ss);
-extern Int VGOFF_(m_ds);
-extern Int VGOFF_(m_es);
-extern Int VGOFF_(m_fs);
-extern Int VGOFF_(m_gs);
+extern Int VGOFF_(m_vex);
+extern Int VGOFF_(m_vex_shadow);
/* Reg-alloc spill area (VG_MAX_SPILLSLOTS words long). */
extern Int VGOFF_(spillslots);
-/* Records the valid bits for the 8 integer regs & flags reg. */
-extern Int VGOFF_(sh_eax);
-extern Int VGOFF_(sh_ecx);
-extern Int VGOFF_(sh_edx);
-extern Int VGOFF_(sh_ebx);
-extern Int VGOFF_(sh_esp);
-extern Int VGOFF_(sh_ebp);
-extern Int VGOFF_(sh_esi);
-extern Int VGOFF_(sh_edi);
-extern Int VGOFF_(sh_eflags);
/* -----------------------------------------------------
Read-only parts of baseBlock.
#define VG_ELF_CLASS ELFCLASS32
-/* ---------------------------------------------------------------------
- Exports of vg_helpers.S
- ------------------------------------------------------------------ */
-
-/* Mul, div, etc, -- we don't codegen these directly. */
-extern void VG_(helper_idiv_64_32);
-extern void VG_(helper_div_64_32);
-extern void VG_(helper_idiv_32_16);
-extern void VG_(helper_div_32_16);
-extern void VG_(helper_idiv_16_8);
-extern void VG_(helper_div_16_8);
-
-extern void VG_(helper_imul_32_64);
-extern void VG_(helper_mul_32_64);
-extern void VG_(helper_imul_16_32);
-extern void VG_(helper_mul_16_32);
-extern void VG_(helper_imul_8_16);
-extern void VG_(helper_mul_8_16);
-
-extern void VG_(helper_CLD);
-extern void VG_(helper_STD);
-extern void VG_(helper_get_dirflag);
-
-extern void VG_(helper_CLC);
-extern void VG_(helper_STC);
-extern void VG_(helper_CMC);
-
-extern void VG_(helper_shldl);
-extern void VG_(helper_shldw);
-extern void VG_(helper_shrdl);
-extern void VG_(helper_shrdw);
-
-extern void VG_(helper_IN);
-extern void VG_(helper_OUT);
-
-extern void VG_(helper_RDTSC);
-extern void VG_(helper_CPUID);
-
-extern void VG_(helper_bsfw);
-extern void VG_(helper_bsfl);
-extern void VG_(helper_bsrw);
-extern void VG_(helper_bsrl);
-
-extern void VG_(helper_fstsw_AX);
-extern void VG_(helper_SAHF);
-extern void VG_(helper_LAHF);
-extern void VG_(helper_DAS);
-extern void VG_(helper_DAA);
-extern void VG_(helper_AAS);
-extern void VG_(helper_AAA);
-extern void VG_(helper_AAD);
-extern void VG_(helper_AAM);
-
-extern void VG_(helper_cmpxchg8b);
-
/* ---------------------------------------------------------------------
LDT type
------------------------------------------------------------------ */
which need to go here to avoid ugly circularities.
------------------------------------------------------------------ */
-/* How big is the saved SSE/SSE2 state? Note that this subsumes the
- FPU state. On machines without SSE, we just save/restore the FPU
- state into the first part of this area. */
-/* A general comment about SSE save/restore: It appears that the 7th
- word (which is the MXCSR) has to be &ed with 0x0000FFBF in order
- that restoring from it later does not cause a GP fault (which is
- delivered as a segfault). I guess this will have to be done
- any time we do fxsave :-( 7th word means word offset 6 or byte
- offset 24 from the start address of the save area.
- */
-#define VG_SIZE_OF_SSESTATE 512
-/* ... and in words ... */
-#define VG_SIZE_OF_SSESTATE_W ((VG_SIZE_OF_SSESTATE+3)/4)
-
-
// Architecture-specific part of a ThreadState
// XXX: eventually this should be made abstract, ie. the fields not visible
// to the core... then VgLdtEntry can be made non-visible to the core
deallocate this at thread exit. */
VgLdtEntry* ldt;
-
/* TLS table. This consists of a small number (currently 3) of
entries from the Global Descriptor Table. */
VgLdtEntry tls[VKI_GDT_ENTRY_TLS_ENTRIES];
- /* Saved machine context. Note the FPU state, %EIP and segment
- registers are not shadowed.
-
- Although the segment registers are 16 bits long, storage
- management here and in VG_(baseBlock) is
- simplified if we pretend they are 32 bits. */
- UInt m_cs;
- UInt m_ss;
- UInt m_ds;
- UInt m_es;
- UInt m_fs;
- UInt m_gs;
-
- UInt m_eax;
- UInt m_ebx;
- UInt m_ecx;
- UInt m_edx;
- UInt m_esi;
- UInt m_edi;
- UInt m_ebp;
- UInt m_esp;
- UInt m_eflags;
- UInt m_eip;
-
- /* The SSE/FPU state. This array does not (necessarily) have the
- required 16-byte alignment required to get stuff in/out by
- fxsave/fxrestore. So we have to do it "by hand".
- */
- UInt m_sse[VG_SIZE_OF_SSESTATE_W];
-
- UInt sh_eax;
- UInt sh_ebx;
- UInt sh_ecx;
- UInt sh_edx;
- UInt sh_esi;
- UInt sh_edi;
- UInt sh_ebp;
- UInt sh_esp;
- UInt sh_eflags;
+ /* Saved machine context. */
+ VexGuestX86State vex;
+
+ /* Saved shadow context. */
+ VexGuestX86State vex_shadow;
}
arch_thread_t;
------------------------------------------------------------------ */
// Total number of spill slots available for register allocation.
-#define VG_MAX_SPILLSLOTS 24
+#define VG_MAX_SPILLSLOTS 100
// Valgrind's signal stack size, in words.
#define VG_SIGSTACK_SIZE_W 10000
The GNU General Public License is contained in the file COPYING.
*/
+#if 0
+
#include "core_asm.h"
/*
/* Let the linker know we don't need an executable stack */
.section .note.GNU-stack,"",@progbits
+#endif /* 0 */
+
##--------------------------------------------------------------------##
##--- end ---##
##--------------------------------------------------------------------##
##--------------------------------------------------------------------##
##--- The core dispatch loop, for jumping to a code address. ---##
-##--- x86/dispatch.S ---##
+##--- vg_dispatch.S ---##
##--------------------------------------------------------------------##
/*
movl VGOFF_(m_eip), %esi
movl (%ebp, %esi, 4), %eax
-dispatch_main:
- /* Jump here to do a new dispatch.
- %eax holds destination (original) address.
- %ebp indicates further details of the control transfer
- requested to the address in %eax.
-
- If ebp == & VG_(baseBlock), just jump next to %eax.
-
- If ebp == VG_EBP_JMP_SYSCALL, do a system call before
- continuing at eax.
-
- If ebp == VG_EBP_JMP_CLIENTREQ, do a client request before
- continuing at eax.
-
- If %ebp has any other value, we panic.
- */
- /*cmpl $VG_(baseBlock), %ebp*/
- /*jnz dispatch_exceptional*/
/* fall into main loop */
-
dispatch_boring:
/* save the jump address at VG_(baseBlock)[VGOFF_(m_eip)] */
movl VGOFF_(m_eip), %esi
movl %eax, (%ebp, %esi, 4)
/* Are we out of timeslice? If yes, defer to scheduler. */
- cmpl $0, VG_(dispatch_ctr)
+ subl $1, VG_(dispatch_ctr)
+
jz counter_is_zero
/* try a fast lookup in the translation cache */
TT_LOOKUP(%ebx, fast_lookup_failed)
/* Found a match. Call the tce.payload field (+VG_CODE_OFFSET) */
addl $VG_CODE_OFFSET, %ebx
- incl VG_(unchained_jumps_done) /* update stats */
call *%ebx
+ /*
+ %eax holds destination (original) address.
+ %ebp indicates further details of the control transfer
+ requested to the address in %eax.
+
+ If ebp == & VG_(baseBlock), just jump next to %eax.
+
+ If ebp == VG_EBP_JMP_SYSCALL, do a system call before
+ continuing at eax.
+
+ If ebp == VG_EBP_JMP_CLIENTREQ, do a client request before
+ continuing at eax.
+
+ If %ebp has any other value, we panic.
+ */
+
cmpl $VG_(baseBlock), %ebp
jz dispatch_boring
fast_lookup_failed:
/* %EIP is up to date here since dispatch_boring dominates */
+ addl $1, VG_(dispatch_ctr)
movl $VG_TRC_INNER_FASTMISS, %eax
jmp run_innerloop_exit
counter_is_zero:
/* %EIP is up to date here since dispatch_boring dominates */
+ addl $1, VG_(dispatch_ctr)
movl $VG_TRC_INNER_COUNTERZERO, %eax
jmp run_innerloop_exit
movl %ebp, %eax
jmp run_innerloop_exit
-
-/*
- This is the translation chainer, our run-time linker, if you like.
-
- VG_(patch_me) patches the call instruction in the jump site
- with a jump to the generated code for the branch target. %eax
- contains the original program's EIP - if we get a hit in
- tt_fast, then the call is patched into a jump; otherwise it
- simply drops back into the dispatch loop for normal
- processing.
-
- The callsite is expected to look like:
- call VG_(patch_me)
- it will be transformed into
- jmp $TARGETADDR
-
- The environment we're expecting on entry is:
- %eax = branch target address (original code EIP)
- *(%esp) = just after call
-*/
-.globl VG_(patch_me)
-VG_(patch_me):
- /* try a fast lookup in the translation cache */
- TT_LOOKUP(%ebx, 1f)
-
- /* Patch call instruction at callsite into a chained jmp */
- popl %eax /* eax = just after (VG_PATCHME_CALLSZ byte) call */
- addl $VG_CODE_OFFSET, %ebx /* ebx = target eip */
- subl %eax, %ebx /* ebx = delta */
- movb $0xE9, -(VG_PATCHME_CALLSZ-0)(%eax) /* 0xe9 = jmp */
- movl %ebx, -(VG_PATCHME_CALLSZ-1)(%eax) /* store delta */
- addl %eax, %ebx
- incl VG_(bb_enchain_count) /* update stats */
- jmp *%ebx /* jmp to dest */
-
- /* tt_fast miss: return into main dispatch loop */
-1: addl $4, %esp /* remove our call address */
- ret /* return into main dispatch loop above */
.data
panic_msg_ebp:
.section .note.GNU-stack,"",@progbits
##--------------------------------------------------------------------##
-##--- end ---##
+##--- end vg_dispatch.S ---##
##--------------------------------------------------------------------##
.long syscall_start - VG_(trampoline_code_start)
.text
-
-/* ------------------ REAL CPU HELPERS ------------------ */
-/* The rest of this lot run on the real CPU. */
-
-/* Various helper routines, for instructions which are just too
- darn tedious for the JITter to output code in-line:
-
- * integer division
- * integer multiplication
- * setting and getting obscure eflags
- * double-length shifts
- * eight byte compare and exchange
-
- All routines use a standard calling convention designed for
- calling from translations, in which the incoming args are
- underneath the return address, the callee saves _all_ registers,
- and the incoming parameters can be modified, to return results.
-*/
-
-/* Fetch the time-stamp-ctr reg.
- On entry:
- dummy, replaced by %EAX value
- dummy, replaced by %EDX value
- RA <- %esp
-*/
-.global VG_(helper_RDTSC)
-VG_(helper_RDTSC):
- pushl %eax
- pushl %edx
- rdtsc
- movl %edx, 12(%esp)
- movl %eax, 16(%esp)
- popl %edx
- popl %eax
- ret
-
-/*
- Fetch a byte/word/dword from given port
- On entry:
- size 1, 2 or 4
- port, replaced by result
- RA
-*/
-.global VG_(helper_IN)
-VG_(helper_IN):
- pushl %eax
- pushl %edx
- movl 16(%esp), %eax
- movl 12(%esp), %edx
-
- pushfl
- cmpl $4, %eax
- je in_dword
- cmpl $2, %eax
- je in_word
-in_byte:
- inb (%dx), %al
- jmp in_done
-in_word:
- in (%dx), %ax
- jmp in_done
-in_dword:
- inl (%dx),%eax
-in_done:
- popfl
- movl %eax,12(%esp)
- popl %edx
- popl %eax
- ret
-
-/*
- Write a byte/word/dword to given port
- On entry:
- size 1, 2 or 4
- port
- value
- RA
-*/
-.global VG_(helper_OUT)
-VG_(helper_OUT):
- pushl %eax
- pushl %edx
- movl 16(%esp), %edx
- movl 12(%esp), %eax
-
- pushfl
- cmpl $4, 20(%esp)
- je out_dword
- cmpl $2, 20(%esp)
- je out_word
-out_byte:
- outb %al,(%dx)
- jmp out_done
-out_word:
- out %ax,(%dx)
- jmp out_done
-out_dword:
- outl %eax,(%dx)
-out_done:
- popfl
- popl %edx
- popl %eax
- ret
-
-
-/* Do the CPUID instruction.
- On entry:
- dummy, replaced by %EAX value
- dummy, replaced by %EBX value
- dummy, replaced by %ECX value
- dummy, replaced by %EDX value
- RA <- %esp
-
- We save registers and package up the args so we can call a C helper
- for all this.
-*/
-.global VG_(helper_CPUID)
-VG_(helper_CPUID):
- pushl %ebp
- movl %esp,%ebp
- pushl %eax
- pushl %ebx
- pushl %ecx
- pushl %edx
- pushl %esi
- pushl %edi
- pushf
-
- lea 2*4(%ebp),%eax /* &edx */
- pushl %eax
- addl $4,%eax /* &ecx */
- pushl %eax
- addl $4,%eax /* &ebx */
- pushl %eax
- addl $4,%eax /* &eax */
- pushl %eax
- pushl (%eax) /* eax */
-
- call VG_(helperc_CPUID)
- addl $20,%esp
-
- popf
- popl %edi
- popl %esi
- popl %edx
- popl %ecx
- popl %ebx
- popl %eax
- popl %ebp
- ret
-
-/* Fetch the FPU status register.
- On entry:
- dummy, replaced by result
- RA <- %esp
-*/
-.global VG_(helper_fstsw_AX)
-VG_(helper_fstsw_AX):
- pushl %eax
- pushl %esi
- movl VGOFF_(m_ssestate), %esi
-
- pushfl
- cmpb $0, VG_(have_ssestate)
- jz aa1nosse
- fxrstor (%ebp, %esi, 4)
- jmp aa1merge
-aa1nosse:
- frstor (%ebp, %esi, 4)
-aa1merge:
- popfl
-
- fstsw %ax
- popl %esi
- movw %ax, 8(%esp)
- popl %eax
- ret
-
-
-/* Copy %ah into %eflags.
- On entry:
- value of %eax
- RA <- %esp
-*/
-.global VG_(helper_SAHF)
-VG_(helper_SAHF):
- pushl %eax
- movl 8(%esp), %eax
- sahf
- popl %eax
- ret
-
-/* Copy %eflags into %ah.
- On entry:
- value of %eax
- RA <- %esp
-*/
-.global VG_(helper_LAHF)
-VG_(helper_LAHF):
- pushl %eax
- movl 8(%esp), %eax
- lahf
- movl %eax, 8(%esp)
- popl %eax
- ret
-
-
-/* Do %al = DAS(%al). Note that the passed param has %AL as the least
- significant 8 bits, since it was generated with GETB %AL,
- some-temp. Fortunately %al is the least significant 8 bits of
- %eax anyway, which is why it's safe to work with %eax as a
- whole.
-
- On entry:
- value of %eax
- RA <- %esp
-*/
-.global VG_(helper_DAS)
-VG_(helper_DAS):
- pushl %eax
- movl 8(%esp), %eax
- das
- movl %eax, 8(%esp)
- popl %eax
- ret
-
-
-/* Similarly, do %al = DAA(%al). */
-.global VG_(helper_DAA)
-VG_(helper_DAA):
- pushl %eax
- movl 8(%esp), %eax
- daa
- movl %eax, 8(%esp)
- popl %eax
- ret
-
-
-/* Similarly, do %ax = AAS(%ax). */
-.global VG_(helper_AAS)
-VG_(helper_AAS):
- pushl %eax
- movl 8(%esp), %eax
- aas
- movl %eax, 8(%esp)
- popl %eax
- ret
-
-
-/* Similarly, do %ax = AAA(%ax). */
-.global VG_(helper_AAA)
-VG_(helper_AAA):
- pushl %eax
- movl 8(%esp), %eax
- aaa
- movl %eax, 8(%esp)
- popl %eax
- ret
-
-
-/* Similarly, do %ax = AAD(%ax). */
-.global VG_(helper_AAD)
-VG_(helper_AAD):
- pushl %eax
- movl 8(%esp), %eax
- aad
- movl %eax, 8(%esp)
- popl %eax
- ret
-
-
-/* Similarly, do %ax = AAM(%ax). */
-.global VG_(helper_AAM)
-VG_(helper_AAM):
- pushl %eax
- movl 8(%esp), %eax
- aam
- movl %eax, 8(%esp)
- popl %eax
- ret
-
-
-/* Bit scan forwards/reverse. Sets flags (??).
- On entry:
- value, replaced by result
- RA <- %esp
-*/
-.global VG_(helper_bsrw)
-VG_(helper_bsrw):
- pushl %eax
- movw 12(%esp), %ax
- bsrw 8(%esp), %ax
- movw %ax, 12(%esp)
- popl %eax
- ret
-
-.global VG_(helper_bsrl)
-VG_(helper_bsrl):
- pushl %eax
- movl 12(%esp), %eax
- bsrl 8(%esp), %eax
- movl %eax, 12(%esp)
- popl %eax
- ret
-
-.global VG_(helper_bsfw)
-VG_(helper_bsfw):
- pushl %eax
- movw 12(%esp), %ax
- bsfw 8(%esp), %ax
- movw %ax, 12(%esp)
- popl %eax
- ret
-
-.global VG_(helper_bsfl)
-VG_(helper_bsfl):
- pushl %eax
- movl 12(%esp), %eax
- bsfl 8(%esp), %eax
- movl %eax, 12(%esp)
- popl %eax
- ret
-
-
-/* 32-bit double-length shift left/right.
- On entry:
- amount
- src
- dst
- RA <- %esp
-*/
-.global VG_(helper_shldl)
-VG_(helper_shldl):
- pushl %eax
- pushl %ebx
- pushl %ecx
-
- movb 24(%esp), %cl
- movl 20(%esp), %ebx
- movl 16(%esp), %eax
- shldl %cl, %ebx, %eax
- movl %eax, 16(%esp)
-
- popl %ecx
- popl %ebx
- popl %eax
- ret
-
-.global VG_(helper_shldw)
-VG_(helper_shldw):
- pushl %eax
- pushl %ebx
- pushl %ecx
-
- movb 24(%esp), %cl
- movw 20(%esp), %bx
- movw 16(%esp), %ax
- shldw %cl, %bx, %ax
- movw %ax, 16(%esp)
-
- popl %ecx
- popl %ebx
- popl %eax
- ret
-
-.global VG_(helper_shrdl)
-VG_(helper_shrdl):
- pushl %eax
- pushl %ebx
- pushl %ecx
-
- movb 24(%esp), %cl
- movl 20(%esp), %ebx
- movl 16(%esp), %eax
- shrdl %cl, %ebx, %eax
- movl %eax, 16(%esp)
-
- popl %ecx
- popl %ebx
- popl %eax
- ret
-
-.global VG_(helper_shrdw)
-VG_(helper_shrdw):
- pushl %eax
- pushl %ebx
- pushl %ecx
-
- movb 24(%esp), %cl
- movw 20(%esp), %bx
- movw 16(%esp), %ax
- shrdw %cl, %bx, %ax
- movw %ax, 16(%esp)
-
- popl %ecx
- popl %ebx
- popl %eax
- ret
-
-
-/* Get the direction flag, and return either 1 or -1. */
-.global VG_(helper_get_dirflag)
-VG_(helper_get_dirflag):
- pushl %eax
-
- movl VGOFF_(m_dflag), %eax
- movl (%ebp, %eax, 4), %eax
- movl %eax, 8(%esp)
-
- popl %eax
- ret
-
-/* Clear/set the direction flag. */
-.global VG_(helper_CLD)
-VG_(helper_CLD):
- pushl %eax
-
- movl VGOFF_(m_dflag), %eax
- movl $1, (%ebp, %eax, 4)
-
- popl %eax
- ret
-
-.global VG_(helper_STD)
-VG_(helper_STD):
- pushl %eax
-
- movl VGOFF_(m_dflag), %eax
- movl $-1, (%ebp, %eax, 4)
-
- popl %eax
- ret
-
-/* Clear/set/complement the carry flag. */
-.global VG_(helper_CLC)
-VG_(helper_CLC):
- clc
- ret
-
-.global VG_(helper_STC)
-VG_(helper_STC):
- stc
- ret
-
-.global VG_(helper_CMC)
-VG_(helper_CMC):
- cmc
- ret
-
-/* Signed 32-to-64 multiply. */
-.globl VG_(helper_imul_32_64)
-VG_(helper_imul_32_64):
- pushl %eax
- pushl %edx
- movl 16(%esp), %eax
- imull 12(%esp)
- movl %eax, 16(%esp)
- movl %edx, 12(%esp)
- popl %edx
- popl %eax
- ret
-
-/* Signed 16-to-32 multiply. */
-.globl VG_(helper_imul_16_32)
-VG_(helper_imul_16_32):
- pushl %eax
- pushl %edx
- movw 16(%esp), %ax
- imulw 12(%esp)
- movw %ax, 16(%esp)
- movw %dx, 12(%esp)
- popl %edx
- popl %eax
- ret
-
-/* Signed 8-to-16 multiply. */
-.globl VG_(helper_imul_8_16)
-VG_(helper_imul_8_16):
- pushl %eax
- pushl %edx
- movb 16(%esp), %al
- imulb 12(%esp)
- movw %ax, 16(%esp)
- popl %edx
- popl %eax
- ret
-
-
-
-
-
-
-/* Unsigned 32-to-64 multiply. */
-.globl VG_(helper_mul_32_64)
-VG_(helper_mul_32_64):
- pushl %eax
- pushl %edx
- movl 16(%esp), %eax
- mull 12(%esp)
- movl %eax, 16(%esp)
- movl %edx, 12(%esp)
- popl %edx
- popl %eax
- ret
-
-/* Unsigned 16-to-32 multiply. */
-.globl VG_(helper_mul_16_32)
-VG_(helper_mul_16_32):
- pushl %eax
- pushl %edx
- movw 16(%esp), %ax
- mulw 12(%esp)
- movw %ax, 16(%esp)
- movw %dx, 12(%esp)
- popl %edx
- popl %eax
- ret
-
-/* Unsigned 8-to-16 multiply. */
-.globl VG_(helper_mul_8_16)
-VG_(helper_mul_8_16):
- pushl %eax
- pushl %edx
- movb 16(%esp), %al
- mulb 12(%esp)
- movw %ax, 16(%esp)
- popl %edx
- popl %eax
- ret
-
-
-
-
-/* Unsigned 64-into-32 divide. */
-.globl VG_(helper_div_64_32)
-VG_(helper_div_64_32):
- pushl %eax
- pushl %edx
- movl 16(%esp),%eax
- movl 12(%esp),%edx
- divl 20(%esp)
- movl %eax,16(%esp)
- movl %edx,12(%esp)
- popl %edx
- popl %eax
- ret
-
-/* Signed 64-into-32 divide. */
-.globl VG_(helper_idiv_64_32)
-VG_(helper_idiv_64_32):
- pushl %eax
- pushl %edx
- movl 16(%esp),%eax
- movl 12(%esp),%edx
- idivl 20(%esp)
- movl %eax,16(%esp)
- movl %edx,12(%esp)
- popl %edx
- popl %eax
- ret
-
-/* Unsigned 32-into-16 divide. */
-.globl VG_(helper_div_32_16)
-VG_(helper_div_32_16):
- pushl %eax
- pushl %edx
- movw 16(%esp),%ax
- movw 12(%esp),%dx
- divw 20(%esp)
- movw %ax,16(%esp)
- movw %dx,12(%esp)
- popl %edx
- popl %eax
- ret
-
-/* Signed 32-into-16 divide. */
-.globl VG_(helper_idiv_32_16)
-VG_(helper_idiv_32_16):
- pushl %eax
- pushl %edx
- movw 16(%esp),%ax
- movw 12(%esp),%dx
- idivw 20(%esp)
- movw %ax,16(%esp)
- movw %dx,12(%esp)
- popl %edx
- popl %eax
- ret
-
-/* Unsigned 16-into-8 divide. */
-.globl VG_(helper_div_16_8)
-VG_(helper_div_16_8):
- pushl %eax
- movw 12(%esp),%ax
- divb 16(%esp)
- movb %ah,12(%esp)
- movb %al,8(%esp)
- popl %eax
- ret
-
-/* Signed 16-into-8 divide. */
-.globl VG_(helper_idiv_16_8)
-VG_(helper_idiv_16_8):
- pushl %eax
- movw 12(%esp),%ax
- idivb 16(%esp)
- movb %ah,12(%esp)
- movb %al,8(%esp)
- popl %eax
- ret
-
-/* Eight byte compare and exchange. */
-.globl VG_(helper_cmpxchg8b)
-VG_(helper_cmpxchg8b):
- pushl %eax
- pushl %ebx
- pushl %ecx
- pushl %edx
- movl 20(%esp), %eax
- movl 24(%esp), %edx
- movl 28(%esp), %ebx
- movl 32(%esp), %ecx
- cmpxchg8b 36(%esp)
- movl %eax, 20(%esp)
- movl %edx, 24(%esp)
- movl %ebx, 28(%esp)
- movl %ecx, 32(%esp)
- popl %edx
- popl %ecx
- popl %ebx
- popl %eax
- ret
/* Undefined instruction (generates SIGILL) */
#include "core.h"
+#include "libvex_guest_x86.h"
+
/*------------------------------------------------------------*/
/*--- Signal frame ---*/
/*------------------------------------------------------------*/
/* Safely-saved version of sigNo, as described above. */
Int sigNo_private;
+
/* Saved processor state. */
- UInt m_sse[VG_SIZE_OF_SSESTATE_W];
-
- UInt m_eax;
- UInt m_ecx;
- UInt m_edx;
- UInt m_ebx;
- UInt m_ebp;
- UInt m_esp;
- UInt m_esi;
- UInt m_edi;
- UInt m_eflags;
- Addr m_eip;
-
- UInt sh_eax;
- UInt sh_ebx;
- UInt sh_ecx;
- UInt sh_edx;
- UInt sh_esi;
- UInt sh_edi;
- UInt sh_ebp;
- UInt sh_esp;
- UInt sh_eflags;
+ VexGuestX86State vex;
+ VexGuestX86State vex_shadow;
/* saved signal mask to be restored when handler returns */
vki_sigset_t mask;
uc->uc_sigmask = *set;
uc->uc_stack = tst->altstack;
-#define SC(reg) sc->reg = tst->arch.m_##reg
- SC(gs);
- SC(fs);
- SC(es);
- SC(ds);
-
- SC(edi);
- SC(esi);
- SC(ebp);
- SC(esp);
- SC(ebx);
- SC(edx);
- SC(ecx);
- SC(eax);
-
- SC(eip);
- SC(cs);
- SC(eflags);
- SC(ss);
+#define SC2(reg,REG) sc->reg = tst->arch.vex.guest_##REG
+ SC2(gs,GS);
+ SC2(fs,FS);
+ SC2(es,ES);
+ SC2(ds,DS);
+
+ SC2(edi,EDI);
+ SC2(esi,ESI);
+ SC2(ebp,EBP);
+ SC2(esp,ESP);
+ SC2(ebx,EBX);
+ SC2(edx,EDX);
+ SC2(ecx,ECX);
+ SC2(eax,EAX);
+
+ SC2(eip,EIP);
+ SC2(cs,CS);
+ sc->eflags = LibVEX_GuestX86_get_eflags(&tst->arch.vex);
+ SC2(ss,SS);
/* XXX esp_at_signal */
/* XXX trapno */
/* XXX err */
-#undef SC
+#undef SC2
sc->cr2 = (UInt)si->_sifields._sigfault._addr;
}
{
Addr esp;
ThreadState* tst;
- Int i;
VgSigFrame* frame;
Int sigNo = siginfo->si_signo;
frame->magicPI = 0x31415927;
- for (i = 0; i < VG_SIZE_OF_SSESTATE_W; i++)
- frame->m_sse[i] = tst->arch.m_sse[i];
-
- frame->m_eax = tst->arch.m_eax;
- frame->m_ecx = tst->arch.m_ecx;
- frame->m_edx = tst->arch.m_edx;
- frame->m_ebx = tst->arch.m_ebx;
- frame->m_ebp = tst->arch.m_ebp;
- frame->m_esp = tst->arch.m_esp;
- frame->m_esi = tst->arch.m_esi;
- frame->m_edi = tst->arch.m_edi;
- frame->m_eflags = tst->arch.m_eflags;
- frame->m_eip = tst->arch.m_eip;
-
- if (VG_(needs).shadow_regs) {
- frame->sh_eax = tst->arch.sh_eax;
- frame->sh_ecx = tst->arch.sh_ecx;
- frame->sh_edx = tst->arch.sh_edx;
- frame->sh_ebx = tst->arch.sh_ebx;
- frame->sh_ebp = tst->arch.sh_ebp;
- frame->sh_esp = tst->arch.sh_esp;
- frame->sh_esi = tst->arch.sh_esi;
- frame->sh_edi = tst->arch.sh_edi;
- frame->sh_eflags = tst->arch.sh_eflags;
- }
+ frame->vex = tst->arch.vex;
+ if (VG_(needs).shadow_regs)
+ frame->vex_shadow = tst->arch.vex_shadow;
frame->mask = tst->sig_mask;
/* tst->m_esp = esp; */
SET_SIGNAL_ESP(tid, esp);
- tst->arch.m_eip = (Addr) handler;
+ tst->arch.vex.guest_EIP = (Addr) handler;
/* This thread needs to be marked runnable, but we leave that the
caller to do. */
if (0)
VG_(printf)("pushed signal frame; %%ESP now = %p, next %%EBP = %p, status=%d\n",
- esp, tst->arch.m_eip, tst->status);
+ esp, tst->arch.vex.guest_EIP, tst->status);
}
Int VGA_(pop_signal_frame)(ThreadId tid)
{
Addr esp;
- Int i;
VgSigFrame* frame;
ThreadState* tst;
tst = & VG_(threads)[tid];
/* Correctly reestablish the frame base address. */
- esp = tst->arch.m_esp;
+ esp = tst->arch.vex.guest_ESP;
frame = (VgSigFrame*)
(esp -4 /* because the handler's RET pops the RA */
+20 /* because signalreturn_bogusRA pushes 5 words */);
vg_assert(frame->magicE == 0x27182818);
if (VG_(clo_trace_signals))
VG_(message)(Vg_DebugMsg,
- "vg_pop_signal_frame (thread %d): valid magic; EIP=%p", tid, frame->m_eip);
+ "vg_pop_signal_frame (thread %d): valid magic; EIP=%p", tid, frame->vex.guest_EIP);
/* Mark the frame structure as nonaccessible. */
VG_TRACK( die_mem_stack_signal, (Addr)frame, sizeof(VgSigFrame) );
/* restore machine state */
- for (i = 0; i < VG_SIZE_OF_SSESTATE_W; i++)
- tst->arch.m_sse[i] = frame->m_sse[i];
-
- tst->arch.m_eax = frame->m_eax;
- tst->arch.m_ecx = frame->m_ecx;
- tst->arch.m_edx = frame->m_edx;
- tst->arch.m_ebx = frame->m_ebx;
- tst->arch.m_ebp = frame->m_ebp;
- tst->arch.m_esp = frame->m_esp;
- tst->arch.m_esi = frame->m_esi;
- tst->arch.m_edi = frame->m_edi;
- tst->arch.m_eflags = frame->m_eflags;
- tst->arch.m_eip = frame->m_eip;
-
- if (VG_(needs).shadow_regs) {
- tst->arch.sh_eax = frame->sh_eax;
- tst->arch.sh_ecx = frame->sh_ecx;
- tst->arch.sh_edx = frame->sh_edx;
- tst->arch.sh_ebx = frame->sh_ebx;
- tst->arch.sh_ebp = frame->sh_ebp;
- tst->arch.sh_esp = frame->sh_esp;
- tst->arch.sh_esi = frame->sh_esi;
- tst->arch.sh_edi = frame->sh_edi;
- tst->arch.sh_eflags = frame->sh_eflags;
- }
+ tst->arch.vex = frame->vex;
+ if (VG_(needs).shadow_regs)
+ tst->arch.vex_shadow = frame->vex_shadow;
/* And restore the thread's status to what it was before the signal
was delivered. */
void VGA_(fill_elfregs_from_BB)(struct vki_user_regs_struct* regs)
{
- regs->eflags = VG_(baseBlock)[VGOFF_(m_eflags)];
- regs->esp = VG_(baseBlock)[VGOFF_(m_esp)];
- regs->eip = VG_(baseBlock)[VGOFF_(m_eip)];
-
- regs->ebx = VG_(baseBlock)[VGOFF_(m_ebx)];
- regs->ecx = VG_(baseBlock)[VGOFF_(m_ecx)];
- regs->edx = VG_(baseBlock)[VGOFF_(m_edx)];
- regs->esi = VG_(baseBlock)[VGOFF_(m_esi)];
- regs->edi = VG_(baseBlock)[VGOFF_(m_edi)];
- regs->ebp = VG_(baseBlock)[VGOFF_(m_ebp)];
- regs->eax = VG_(baseBlock)[VGOFF_(m_eax)];
-
- regs->cs = VG_(baseBlock)[VGOFF_(m_cs)];
- regs->ds = VG_(baseBlock)[VGOFF_(m_ds)];
- regs->ss = VG_(baseBlock)[VGOFF_(m_ss)];
- regs->es = VG_(baseBlock)[VGOFF_(m_es)];
- regs->fs = VG_(baseBlock)[VGOFF_(m_fs)];
- regs->gs = VG_(baseBlock)[VGOFF_(m_gs)];
+ regs->eflags = LibVEX_GuestX86_get_eflags(BASEBLOCK_VEX);
+ regs->esp = BASEBLOCK_VEX->guest_ESP;
+ regs->eip = BASEBLOCK_VEX->guest_EIP;
+
+ regs->ebx = BASEBLOCK_VEX->guest_EBX;
+ regs->ecx = BASEBLOCK_VEX->guest_ECX;
+ regs->edx = BASEBLOCK_VEX->guest_EDX;
+ regs->esi = BASEBLOCK_VEX->guest_ESI;
+ regs->edi = BASEBLOCK_VEX->guest_EDI;
+ regs->ebp = BASEBLOCK_VEX->guest_EBP;
+ regs->eax = BASEBLOCK_VEX->guest_EAX;
+
+ regs->cs = BASEBLOCK_VEX->guest_CS;
+ regs->ds = BASEBLOCK_VEX->guest_DS;
+ regs->ss = BASEBLOCK_VEX->guest_SS;
+ regs->es = BASEBLOCK_VEX->guest_ES;
+ regs->fs = BASEBLOCK_VEX->guest_FS;
+ regs->gs = BASEBLOCK_VEX->guest_GS;
}
void VGA_(fill_elfregs_from_tst)(struct vki_user_regs_struct* regs,
- const arch_thread_t* arch)
+ arch_thread_t* arch)
{
- regs->eflags = arch->m_eflags;
- regs->esp = arch->m_esp;
- regs->eip = arch->m_eip;
-
- regs->ebx = arch->m_ebx;
- regs->ecx = arch->m_ecx;
- regs->edx = arch->m_edx;
- regs->esi = arch->m_esi;
- regs->edi = arch->m_edi;
- regs->ebp = arch->m_ebp;
- regs->eax = arch->m_eax;
-
- regs->cs = arch->m_cs;
- regs->ds = arch->m_ds;
- regs->ss = arch->m_ss;
- regs->es = arch->m_es;
- regs->fs = arch->m_fs;
- regs->gs = arch->m_gs;
+ regs->eflags = LibVEX_GuestX86_get_eflags(&arch->vex);
+ regs->esp = arch->vex.guest_ESP;
+ regs->eip = arch->vex.guest_EIP;
+
+ regs->ebx = arch->vex.guest_EBX;
+ regs->ecx = arch->vex.guest_ECX;
+ regs->edx = arch->vex.guest_EDX;
+ regs->esi = arch->vex.guest_ESI;
+ regs->edi = arch->vex.guest_EDI;
+ regs->ebp = arch->vex.guest_EBP;
+ regs->eax = arch->vex.guest_EAX;
+
+ regs->cs = arch->vex.guest_CS;
+ regs->ds = arch->vex.guest_DS;
+ regs->ss = arch->vex.guest_SS;
+ regs->es = arch->vex.guest_ES;
+ regs->fs = arch->vex.guest_FS;
+ regs->gs = arch->vex.guest_GS;
}
+#if 0
static void fill_fpu(vki_elf_fpregset_t *fpu, const Char *from)
{
if (VG_(have_ssestate)) {
} else
VG_(memcpy)(fpu, from, sizeof(*fpu));
}
+#endif
void VGA_(fill_elffpregs_from_BB)( vki_elf_fpregset_t* fpu )
{
- fill_fpu(fpu, (const Char *)&VG_(baseBlock)[VGOFF_(m_ssestate)]);
+ //fill_fpu(fpu, (const Char *)&VG_(baseBlock)[VGOFF_(m_ssestate)]);
}
void VGA_(fill_elffpregs_from_tst)( vki_elf_fpregset_t* fpu,
const arch_thread_t* arch)
{
- fill_fpu(fpu, (const Char *)&arch->m_sse);
+ //fill_fpu(fpu, (const Char *)&arch->m_sse);
}
void VGA_(fill_elffpxregs_from_BB) ( vki_elf_fpxregset_t* xfpu )
{
- VG_(memcpy)(xfpu, &VG_(baseBlock)[VGOFF_(m_ssestate)], sizeof(*xfpu));
+ //VG_(memcpy)(xfpu, &VG_(baseBlock)[VGOFF_(m_ssestate)], sizeof(*xfpu));
}
void VGA_(fill_elffpxregs_from_tst) ( vki_elf_fpxregset_t* xfpu,
const arch_thread_t* arch )
{
- VG_(memcpy)(xfpu, arch->m_sse, sizeof(*xfpu));
+ //VG_(memcpy)(xfpu, arch->m_sse, sizeof(*xfpu));
}
/*--------------------------------------------------------------------*/
#include "x86_private.h"
#include <sys/ptrace.h>
+#include "libvex_guest_x86.h"
+
/*------------------------------------------------------------*/
/*--- baseBlock setup and operations ---*/
/*------------------------------------------------------------*/
/* The variables storing offsets. */
+Int VGOFF_(m_vex) = INVALID_OFFSET;
+Int VGOFF_(m_vex_shadow) = INVALID_OFFSET;
-Int VGOFF_(m_eax) = INVALID_OFFSET;
-Int VGOFF_(m_ecx) = INVALID_OFFSET;
-Int VGOFF_(m_edx) = INVALID_OFFSET;
-Int VGOFF_(m_ebx) = INVALID_OFFSET;
-Int VGOFF_(m_esp) = INVALID_OFFSET;
-Int VGOFF_(m_ebp) = INVALID_OFFSET;
-Int VGOFF_(m_esi) = INVALID_OFFSET;
-Int VGOFF_(m_edi) = INVALID_OFFSET;
-Int VGOFF_(m_eflags) = INVALID_OFFSET;
-Int VGOFF_(m_dflag) = INVALID_OFFSET;
-Int VGOFF_(m_ssestate) = INVALID_OFFSET;
Int VGOFF_(ldt) = INVALID_OFFSET;
Int VGOFF_(tls_ptr) = INVALID_OFFSET;
-Int VGOFF_(m_cs) = INVALID_OFFSET;
-Int VGOFF_(m_ss) = INVALID_OFFSET;
-Int VGOFF_(m_ds) = INVALID_OFFSET;
-Int VGOFF_(m_es) = INVALID_OFFSET;
-Int VGOFF_(m_fs) = INVALID_OFFSET;
-Int VGOFF_(m_gs) = INVALID_OFFSET;
Int VGOFF_(m_eip) = INVALID_OFFSET;
+
Int VGOFF_(spillslots) = INVALID_OFFSET;
-Int VGOFF_(sh_eax) = INVALID_OFFSET;
-Int VGOFF_(sh_ecx) = INVALID_OFFSET;
-Int VGOFF_(sh_edx) = INVALID_OFFSET;
-Int VGOFF_(sh_ebx) = INVALID_OFFSET;
-Int VGOFF_(sh_esp) = INVALID_OFFSET;
-Int VGOFF_(sh_ebp) = INVALID_OFFSET;
-Int VGOFF_(sh_esi) = INVALID_OFFSET;
-Int VGOFF_(sh_edi) = INVALID_OFFSET;
-Int VGOFF_(sh_eflags) = INVALID_OFFSET;
-
-Int VGOFF_(helper_idiv_64_32) = INVALID_OFFSET;
-Int VGOFF_(helper_div_64_32) = INVALID_OFFSET;
-Int VGOFF_(helper_idiv_32_16) = INVALID_OFFSET;
-Int VGOFF_(helper_div_32_16) = INVALID_OFFSET;
-Int VGOFF_(helper_idiv_16_8) = INVALID_OFFSET;
-Int VGOFF_(helper_div_16_8) = INVALID_OFFSET;
-Int VGOFF_(helper_imul_32_64) = INVALID_OFFSET;
-Int VGOFF_(helper_mul_32_64) = INVALID_OFFSET;
-Int VGOFF_(helper_imul_16_32) = INVALID_OFFSET;
-Int VGOFF_(helper_mul_16_32) = INVALID_OFFSET;
-Int VGOFF_(helper_imul_8_16) = INVALID_OFFSET;
-Int VGOFF_(helper_mul_8_16) = INVALID_OFFSET;
-Int VGOFF_(helper_CLD) = INVALID_OFFSET;
-Int VGOFF_(helper_STD) = INVALID_OFFSET;
-Int VGOFF_(helper_get_dirflag) = INVALID_OFFSET;
-Int VGOFF_(helper_CLC) = INVALID_OFFSET;
-Int VGOFF_(helper_STC) = INVALID_OFFSET;
-Int VGOFF_(helper_CMC) = INVALID_OFFSET;
-Int VGOFF_(helper_shldl) = INVALID_OFFSET;
-Int VGOFF_(helper_shldw) = INVALID_OFFSET;
-Int VGOFF_(helper_shrdl) = INVALID_OFFSET;
-Int VGOFF_(helper_shrdw) = INVALID_OFFSET;
-Int VGOFF_(helper_IN) = INVALID_OFFSET;
-Int VGOFF_(helper_OUT) = INVALID_OFFSET;
-Int VGOFF_(helper_RDTSC) = INVALID_OFFSET;
-Int VGOFF_(helper_CPUID) = INVALID_OFFSET;
-Int VGOFF_(helper_BSWAP) = INVALID_OFFSET;
-Int VGOFF_(helper_bsfw) = INVALID_OFFSET;
-Int VGOFF_(helper_bsfl) = INVALID_OFFSET;
-Int VGOFF_(helper_bsrw) = INVALID_OFFSET;
-Int VGOFF_(helper_bsrl) = INVALID_OFFSET;
-Int VGOFF_(helper_fstsw_AX) = INVALID_OFFSET;
-Int VGOFF_(helper_SAHF) = INVALID_OFFSET;
-Int VGOFF_(helper_LAHF) = INVALID_OFFSET;
-Int VGOFF_(helper_DAS) = INVALID_OFFSET;
-Int VGOFF_(helper_DAA) = INVALID_OFFSET;
-Int VGOFF_(helper_AAS) = INVALID_OFFSET;
-Int VGOFF_(helper_AAA) = INVALID_OFFSET;
-Int VGOFF_(helper_AAD) = INVALID_OFFSET;
-Int VGOFF_(helper_AAM) = INVALID_OFFSET;
-Int VGOFF_(helper_cmpxchg8b) = INVALID_OFFSET;
-
-static Int extractDflag(UInt eflags)
-{
- return ( eflags & EFlagD ? -1 : 1 );
-}
-static UInt insertDflag(UInt eflags, Int d)
-{
- vg_assert(d == 1 || d == -1);
- eflags &= ~EFlagD;
- if (d < 0) eflags |= EFlagD;
- return eflags;
-}
+
/* Here we assign actual offsets. It's important on x86 to get the most
popular referents within 128 bytes of the start, so we can take
size of translations. */
void VGA_(init_low_baseBlock) ( Addr client_eip, Addr esp_at_startup )
{
- /* Those with offsets under 128 are carefully chosen. */
-
- /* WORD offsets in this column */
- /* 0 */ VGOFF_(m_eax) = VG_(alloc_BaB_1_set)(0);
- /* 1 */ VGOFF_(m_ecx) = VG_(alloc_BaB_1_set)(0);
- /* 2 */ VGOFF_(m_edx) = VG_(alloc_BaB_1_set)(0);
- /* 3 */ VGOFF_(m_ebx) = VG_(alloc_BaB_1_set)(0);
- /* 4 */ VGOFF_(m_esp) = VG_(alloc_BaB_1_set)(esp_at_startup);
- /* 5 */ VGOFF_(m_ebp) = VG_(alloc_BaB_1_set)(0);
- /* 6 */ VGOFF_(m_esi) = VG_(alloc_BaB_1_set)(0);
- /* 7 */ VGOFF_(m_edi) = VG_(alloc_BaB_1_set)(0);
- /* 8 */ VGOFF_(m_eflags) = VG_(alloc_BaB_1_set)(0);
+ vg_assert(0 == sizeof(VexGuestX86State) % 8);
- if (VG_(needs).shadow_regs) {
- /* 9 */ VGOFF_(sh_eax) = VG_(alloc_BaB_1_set)(0);
- /* 10 */ VGOFF_(sh_ecx) = VG_(alloc_BaB_1_set)(0);
- /* 11 */ VGOFF_(sh_edx) = VG_(alloc_BaB_1_set)(0);
- /* 12 */ VGOFF_(sh_ebx) = VG_(alloc_BaB_1_set)(0);
- /* 13 */ VGOFF_(sh_esp) = VG_(alloc_BaB_1_set)(0);
- /* 14 */ VGOFF_(sh_ebp) = VG_(alloc_BaB_1_set)(0);
- /* 15 */ VGOFF_(sh_esi) = VG_(alloc_BaB_1_set)(0);
- /* 16 */ VGOFF_(sh_edi) = VG_(alloc_BaB_1_set)(0);
- /* 17 */ VGOFF_(sh_eflags) = VG_(alloc_BaB_1_set)(0);
- VG_TRACK( post_regs_write_init );
- }
+ /* First the guest state. */
+ VGOFF_(m_vex) = VG_(alloc_BaB)( sizeof(VexGuestX86State) / 4 );
+
+ /* Then equal sized shadow state. */
+ VGOFF_(m_vex_shadow) = VG_(alloc_BaB)( sizeof(VexGuestX86State) / 4 );
- /* 9,10,11 or 18,19,20... depends on number whether shadow regs are used
- * and on compact helpers registered */
+ /* Finally the spill area. */
+ VGOFF_(spillslots) = VG_(alloc_BaB)( LibVEX_N_SPILL_BYTES/4 );
+ if (0) VG_(printf)("SPILL SLOTS start at %d\n", VGOFF_(spillslots));
- /* Make these most-frequently-called specialised ones compact, if they
- are used. */
- if (VG_(defined_new_mem_stack_4)())
- VG_(register_compact_helper)( (Addr) VG_(tool_interface).track_new_mem_stack_4);
+ /* Zero out the initial state, and set up the simulated FPU in a
+ sane way. */
+ LibVEX_GuestX86_initialise(BASEBLOCK_VEX);
- if (VG_(defined_die_mem_stack_4)())
- VG_(register_compact_helper)( (Addr) VG_(tool_interface).track_die_mem_stack_4);
+ /* Zero out the shadow area. */
+ VG_(memset)(BASEBLOCK_VEX_SHADOW, 0, sizeof(VexGuestX86State));
+ /* Put essential stuff into the new state. */
+ BASEBLOCK_VEX->guest_ESP = esp_at_startup;
+ BASEBLOCK_VEX->guest_EIP = client_eip;
+
+ /* The dispatch loop needs to be able to find %EIP. */
+ VGOFF_(m_eip)
+ = VGOFF_(m_vex) + offsetof(VexGuestX86State,guest_EIP)/4;
+
+ if (VG_(needs).shadow_regs) {
+ VG_TRACK( post_regs_write_init );
+ }
}
void VGA_(init_high_baseBlock)( Addr client_eip, Addr esp_at_startup )
{
- /* (9/10 or 18/19) + n_compact_helpers */
- VGOFF_(m_eip) = VG_(alloc_BaB_1_set)(client_eip);
-
/* There are currently 24 spill slots */
/* (11+/20+ .. 32+/43+) + n_compact_helpers. This can overlap the magic
* boundary at >= 32 words, but most spills are to low numbered spill
* slots, so the ones above the boundary don't see much action. */
- VGOFF_(spillslots) = VG_(alloc_BaB)(VG_MAX_SPILLSLOTS);
/* I gave up counting at this point. Since they're above the
short-amode-boundary, there's no point. */
- VGOFF_(m_dflag) = VG_(alloc_BaB_1_set)(1); // 1 == forward D-flag
-
- /* The FPU/SSE state. This _must_ be 16-byte aligned. Initial
- state doesn't matter much, as long as it's not totally borked. */
- VG_(align_BaB)(16);
- VGOFF_(m_ssestate) = VG_(alloc_BaB)(VG_SIZE_OF_SSESTATE_W);
- vg_assert(
- 0 == ( ((UInt)(& VG_(baseBlock)[VGOFF_(m_ssestate)])) % 16 )
- );
-
/* I assume that if we have SSE2 we also have SSE */
- VG_(have_ssestate) =
- VG_(cpu_has_feature)(VG_X86_FEAT_FXSR) &&
- VG_(cpu_has_feature)(VG_X86_FEAT_SSE);
-
- /* set up an initial FPU state (doesn't really matter what it is,
- so long as it's somewhat valid) */
- if (!VG_(have_ssestate))
- asm volatile("fwait; fnsave %0; fwait; frstor %0; fwait"
- :
- : "m" (VG_(baseBlock)[VGOFF_(m_ssestate)])
- : "cc", "memory");
- else
- asm volatile("fwait; fxsave %0; fwait; andl $0xffbf, %1;"
- "fxrstor %0; fwait"
- :
- : "m" (VG_(baseBlock)[VGOFF_(m_ssestate)]),
- "m" (VG_(baseBlock)[VGOFF_(m_ssestate)+(24/4)])
- : "cc", "memory");
+ VG_(have_ssestate) = False;
+ // VG_(cpu_has_feature)(VG_X86_FEAT_FXSR) &&
+ // VG_(cpu_has_feature)(VG_X86_FEAT_SSE);
if (0) {
if (VG_(have_ssestate))
/* TLS pointer: pretend the root thread has no TLS array for now. */
VGOFF_(tls_ptr) = VG_(alloc_BaB_1_set)((UInt)NULL);
- /* segment registers */
- VGOFF_(m_cs) = VG_(alloc_BaB_1_set)(0);
- VGOFF_(m_ss) = VG_(alloc_BaB_1_set)(0);
- VGOFF_(m_ds) = VG_(alloc_BaB_1_set)(0);
- VGOFF_(m_es) = VG_(alloc_BaB_1_set)(0);
- VGOFF_(m_fs) = VG_(alloc_BaB_1_set)(0);
- VGOFF_(m_gs) = VG_(alloc_BaB_1_set)(0);
-
/* initialise %cs, %ds and %ss to point at the operating systems
default code, data and stack segments */
asm volatile("movw %%cs, %0"
:
- : "m" (VG_(baseBlock)[VGOFF_(m_cs)]));
+ : "m" (BASEBLOCK_VEX->guest_CS));
asm volatile("movw %%ds, %0"
:
- : "m" (VG_(baseBlock)[VGOFF_(m_ds)]));
+ : "m" (BASEBLOCK_VEX->guest_DS));
asm volatile("movw %%ss, %0"
:
- : "m" (VG_(baseBlock)[VGOFF_(m_ss)]));
-
- VG_(register_noncompact_helper)( (Addr) & VG_(do_useseg) );
-
-# define HELPER(name) \
- VGOFF_(helper_##name) = VG_(alloc_BaB_1_set)( (Addr) & VG_(helper_##name))
-
- /* Helper functions. */
- HELPER(idiv_64_32); HELPER(div_64_32);
- HELPER(idiv_32_16); HELPER(div_32_16);
- HELPER(idiv_16_8); HELPER(div_16_8);
-
- HELPER(imul_32_64); HELPER(mul_32_64);
- HELPER(imul_16_32); HELPER(mul_16_32);
- HELPER(imul_8_16); HELPER(mul_8_16);
-
- HELPER(CLD); HELPER(STD);
- HELPER(get_dirflag);
-
- HELPER(CLC); HELPER(STC);
- HELPER(CMC);
-
- HELPER(shldl); HELPER(shldw);
- HELPER(shrdl); HELPER(shrdw);
-
- HELPER(RDTSC); HELPER(CPUID);
-
- HELPER(bsfw); HELPER(bsfl);
- HELPER(bsrw); HELPER(bsrl);
-
- HELPER(fstsw_AX);
- HELPER(SAHF); HELPER(LAHF);
- HELPER(DAS); HELPER(DAA);
- HELPER(AAS); HELPER(AAA);
- HELPER(AAD); HELPER(AAM);
- HELPER(IN); HELPER(OUT);
- HELPER(cmpxchg8b);
-
- HELPER(undefined_instruction);
-
-# undef HELPER
+ : "m" (BASEBLOCK_VEX->guest_SS));
}
/* Junk to fill up a thread's shadow regs with when shadow regs aren't
void VGA_(load_state) ( arch_thread_t* arch, ThreadId tid )
{
- Int i;
-
VG_(baseBlock)[VGOFF_(ldt)] = (UInt)arch->ldt;
VG_(baseBlock)[VGOFF_(tls_ptr)] = (UInt)arch->tls;
- VG_(baseBlock)[VGOFF_(m_cs)] = arch->m_cs;
- VG_(baseBlock)[VGOFF_(m_ss)] = arch->m_ss;
- VG_(baseBlock)[VGOFF_(m_ds)] = arch->m_ds;
- VG_(baseBlock)[VGOFF_(m_es)] = arch->m_es;
- VG_(baseBlock)[VGOFF_(m_fs)] = arch->m_fs;
- VG_(baseBlock)[VGOFF_(m_gs)] = arch->m_gs;
-
- VG_(baseBlock)[VGOFF_(m_eax)] = arch->m_eax;
- VG_(baseBlock)[VGOFF_(m_ebx)] = arch->m_ebx;
- VG_(baseBlock)[VGOFF_(m_ecx)] = arch->m_ecx;
- VG_(baseBlock)[VGOFF_(m_edx)] = arch->m_edx;
- VG_(baseBlock)[VGOFF_(m_esi)] = arch->m_esi;
- VG_(baseBlock)[VGOFF_(m_edi)] = arch->m_edi;
- VG_(baseBlock)[VGOFF_(m_ebp)] = arch->m_ebp;
- VG_(baseBlock)[VGOFF_(m_esp)] = arch->m_esp;
- VG_(baseBlock)[VGOFF_(m_eflags)] = arch->m_eflags & ~EFlagD;
- VG_(baseBlock)[VGOFF_(m_dflag)] = extractDflag(arch->m_eflags);
- VG_(baseBlock)[VGOFF_(m_eip)] = arch->m_eip;
-
- for (i = 0; i < VG_SIZE_OF_SSESTATE_W; i++)
- VG_(baseBlock)[VGOFF_(m_ssestate) + i] = arch->m_sse[i];
+
+ *BASEBLOCK_VEX = arch->vex;
if (VG_(needs).shadow_regs) {
- VG_(baseBlock)[VGOFF_(sh_eax)] = arch->sh_eax;
- VG_(baseBlock)[VGOFF_(sh_ebx)] = arch->sh_ebx;
- VG_(baseBlock)[VGOFF_(sh_ecx)] = arch->sh_ecx;
- VG_(baseBlock)[VGOFF_(sh_edx)] = arch->sh_edx;
- VG_(baseBlock)[VGOFF_(sh_esi)] = arch->sh_esi;
- VG_(baseBlock)[VGOFF_(sh_edi)] = arch->sh_edi;
- VG_(baseBlock)[VGOFF_(sh_ebp)] = arch->sh_ebp;
- VG_(baseBlock)[VGOFF_(sh_esp)] = arch->sh_esp;
- VG_(baseBlock)[VGOFF_(sh_eflags)] = arch->sh_eflags;
+ *BASEBLOCK_VEX_SHADOW = arch->vex_shadow;
} else {
/* Fields shouldn't be used -- check their values haven't changed. */
+ /* ummm ...
vg_assert(
VG_UNUSED_SHADOW_REG_VALUE == arch->sh_eax &&
VG_UNUSED_SHADOW_REG_VALUE == arch->sh_ebx &&
VG_UNUSED_SHADOW_REG_VALUE == arch->sh_ebp &&
VG_UNUSED_SHADOW_REG_VALUE == arch->sh_esp &&
VG_UNUSED_SHADOW_REG_VALUE == arch->sh_eflags);
+ */
}
}
assertion fails. */
if ((void*)arch->ldt != (void*)VG_(baseBlock)[VGOFF_(ldt)])
VG_(printf)("VG_(threads)[%d].ldt=%p VG_(baseBlock)[VGOFF_(ldt)]=%p\n",
- tid, (void*)arch->ldt,
+ tid, (void*)arch->ldt,
(void*)VG_(baseBlock)[VGOFF_(ldt)]);
vg_assert((void*)arch->ldt == (void*)VG_(baseBlock)[VGOFF_(ldt)]);
if ((void*)arch->tls != (void*)VG_(baseBlock)[VGOFF_(tls_ptr)])
VG_(printf)("VG_(threads)[%d].tls=%p VG_(baseBlock)[VGOFF_(tls_ptr)]=%p\
n",
- tid, (void*)arch->tls,
+ tid, (void*)arch->tls,
(void*)VG_(baseBlock)[VGOFF_(tls_ptr)]);
- vg_assert((void*)arch->tls
+ vg_assert((void*)arch->tls
== (void*)VG_(baseBlock)[VGOFF_(tls_ptr)]);
- arch->m_cs = VG_(baseBlock)[VGOFF_(m_cs)];
- arch->m_ss = VG_(baseBlock)[VGOFF_(m_ss)];
- arch->m_ds = VG_(baseBlock)[VGOFF_(m_ds)];
- arch->m_es = VG_(baseBlock)[VGOFF_(m_es)];
- arch->m_fs = VG_(baseBlock)[VGOFF_(m_fs)];
- arch->m_gs = VG_(baseBlock)[VGOFF_(m_gs)];
-
- arch->m_eax = VG_(baseBlock)[VGOFF_(m_eax)];
- arch->m_ebx = VG_(baseBlock)[VGOFF_(m_ebx)];
- arch->m_ecx = VG_(baseBlock)[VGOFF_(m_ecx)];
- arch->m_edx = VG_(baseBlock)[VGOFF_(m_edx)];
- arch->m_esi = VG_(baseBlock)[VGOFF_(m_esi)];
- arch->m_edi = VG_(baseBlock)[VGOFF_(m_edi)];
- arch->m_ebp = VG_(baseBlock)[VGOFF_(m_ebp)];
- arch->m_esp = VG_(baseBlock)[VGOFF_(m_esp)];
- arch->m_eflags
- = insertDflag(VG_(baseBlock)[VGOFF_(m_eflags)],
- VG_(baseBlock)[VGOFF_(m_dflag)]);
- arch->m_eip = VG_(baseBlock)[VGOFF_(m_eip)];
-
- for (i = 0; i < VG_SIZE_OF_SSESTATE_W; i++)
- arch->m_sse[i]
- = VG_(baseBlock)[VGOFF_(m_ssestate) + i];
+ arch->vex = *BASEBLOCK_VEX;
if (VG_(needs).shadow_regs) {
- arch->sh_eax = VG_(baseBlock)[VGOFF_(sh_eax)];
- arch->sh_ebx = VG_(baseBlock)[VGOFF_(sh_ebx)];
- arch->sh_ecx = VG_(baseBlock)[VGOFF_(sh_ecx)];
- arch->sh_edx = VG_(baseBlock)[VGOFF_(sh_edx)];
- arch->sh_esi = VG_(baseBlock)[VGOFF_(sh_esi)];
- arch->sh_edi = VG_(baseBlock)[VGOFF_(sh_edi)];
- arch->sh_ebp = VG_(baseBlock)[VGOFF_(sh_ebp)];
- arch->sh_esp = VG_(baseBlock)[VGOFF_(sh_esp)];
- arch->sh_eflags = VG_(baseBlock)[VGOFF_(sh_eflags)];
+ arch->vex_shadow = *BASEBLOCK_VEX_SHADOW;
} else {
/* Fill with recognisable junk */
+ /* can't easily do this ...
arch->sh_eax =
arch->sh_ebx =
arch->sh_ecx =
arch->sh_esi =
arch->sh_edi =
arch->sh_ebp =
- arch->sh_esp =
+ arch->sh_esp =
arch->sh_eflags = VG_UNUSED_SHADOW_REG_VALUE;
+ */
}
/* Fill it up with junk. */
VG_(baseBlock)[VGOFF_(ldt)] = junk;
VG_(baseBlock)[VGOFF_(tls_ptr)] = junk;
- VG_(baseBlock)[VGOFF_(m_cs)] = junk;
- VG_(baseBlock)[VGOFF_(m_ss)] = junk;
- VG_(baseBlock)[VGOFF_(m_ds)] = junk;
- VG_(baseBlock)[VGOFF_(m_es)] = junk;
- VG_(baseBlock)[VGOFF_(m_fs)] = junk;
- VG_(baseBlock)[VGOFF_(m_gs)] = junk;
-
- VG_(baseBlock)[VGOFF_(m_eax)] = junk;
- VG_(baseBlock)[VGOFF_(m_ebx)] = junk;
- VG_(baseBlock)[VGOFF_(m_ecx)] = junk;
- VG_(baseBlock)[VGOFF_(m_edx)] = junk;
- VG_(baseBlock)[VGOFF_(m_esi)] = junk;
- VG_(baseBlock)[VGOFF_(m_edi)] = junk;
- VG_(baseBlock)[VGOFF_(m_ebp)] = junk;
- VG_(baseBlock)[VGOFF_(m_esp)] = junk;
- VG_(baseBlock)[VGOFF_(m_eflags)] = junk;
- VG_(baseBlock)[VGOFF_(m_eip)] = junk;
-
- for (i = 0; i < VG_SIZE_OF_SSESTATE_W; i++)
- VG_(baseBlock)[VGOFF_(m_ssestate) + i] = junk;
+
+ for (i = 0; i < (3 + sizeof(VexGuestX86State)) / 4; i++)
+ VG_(baseBlock)[VGOFF_(m_vex) + i] = junk;
+}
+
+/*------------------------------------------------------------*/
+/*--- Register access stuff ---*/
+/*------------------------------------------------------------*/
+
+void VGA_(set_thread_shadow_archreg) ( ThreadId tid, UInt archreg, UInt val )
+{
+ ThreadState* tst;
+
+ vg_assert(VG_(is_valid_tid)(tid));
+ tst = & VG_(threads)[tid];
+ if (0)
+ VG_(printf)("set_thread_shadow_archreg(%d, %d, 0x%x)\n",
+ tid, archreg, val);
+ switch (archreg) {
+ case R_EAX: tst->arch.vex_shadow.guest_EAX = val; break;
+ case R_ECX: tst->arch.vex_shadow.guest_ECX = val; break;
+ case R_EDX: tst->arch.vex_shadow.guest_EDX = val; break;
+ case R_EBX: tst->arch.vex_shadow.guest_EBX = val; break;
+ case R_ESP: tst->arch.vex_shadow.guest_ESP = val; break;
+ case R_EBP: tst->arch.vex_shadow.guest_EBP = val; break;
+ case R_ESI: tst->arch.vex_shadow.guest_ESI = val; break;
+ case R_EDI: tst->arch.vex_shadow.guest_EDI = val; break;
+ default: VG_(core_panic)( "set_thread_shadow_archreg");
+ }
+}
+
+UInt VGA_(get_thread_shadow_archreg) ( ThreadId tid, UInt archreg )
+{
+ ThreadState* tst;
+
+ vg_assert(VG_(is_valid_tid)(tid));
+ tst = & VG_(threads)[tid];
+
+ VG_(printf)("get_thread_shadow_archreg(%d, %d)\n",
+ tid, archreg);
+
+ switch (archreg) {
+ case R_EAX: return tst->arch.vex_shadow.guest_EAX;
+ case R_ECX: return tst->arch.vex_shadow.guest_ECX;
+ case R_EDX: return tst->arch.vex_shadow.guest_EDX;
+ case R_EBX: return tst->arch.vex_shadow.guest_EBX;
+ case R_ESP: return tst->arch.vex_shadow.guest_ESP;
+ case R_EBP: return tst->arch.vex_shadow.guest_EBP;
+ case R_ESI: return tst->arch.vex_shadow.guest_ESI;
+ case R_EDI: return tst->arch.vex_shadow.guest_EDI;
+ default: VG_(core_panic)( "get_thread_shadow_archreg");
+ }
+}
+
+/* Return the baseBlock index for the specified shadow register */
+static Int shadow_reg_index ( Int arch )
+{
+ VG_(printf)("shadow_reg_index(%d)\n",
+ arch);
+ switch (arch) {
+ case R_EAX: return VGOFF_(m_vex_shadow) + offsetof(VexGuestX86State,guest_EAX)/4;
+ case R_ECX: return VGOFF_(m_vex_shadow) + offsetof(VexGuestX86State,guest_ECX)/4;
+ case R_EDX: return VGOFF_(m_vex_shadow) + offsetof(VexGuestX86State,guest_EDX)/4;
+ case R_EBX: return VGOFF_(m_vex_shadow) + offsetof(VexGuestX86State,guest_EBX)/4;
+ case R_ESP: return VGOFF_(m_vex_shadow) + offsetof(VexGuestX86State,guest_ESP)/4;
+ case R_EBP: return VGOFF_(m_vex_shadow) + offsetof(VexGuestX86State,guest_EBP)/4;
+ case R_ESI: return VGOFF_(m_vex_shadow) + offsetof(VexGuestX86State,guest_ESI)/4;
+ case R_EDI: return VGOFF_(m_vex_shadow) + offsetof(VexGuestX86State,guest_EDI)/4;
+ default: VG_(core_panic)( "shadow_reg_index");
+ }
}
+/* Accessing shadow arch. registers */
+UInt VGA_(get_shadow_archreg) ( UInt archreg )
+{
+ return VG_(baseBlock)[ shadow_reg_index(archreg) ];
+}
+
+
/*------------------------------------------------------------*/
/*--- Thread stuff ---*/
/*------------------------------------------------------------*/
void VGA_(set_arg_and_bogus_ret)( ThreadId tid, UWord arg, Addr ret )
{
/* Push the arg, and mark it as readable. */
- SET_PTHREQ_ESP(tid, VG_(threads)[tid].arch.m_esp - sizeof(UWord));
- * (UInt*)(VG_(threads)[tid].arch.m_esp) = arg;
- VG_TRACK( post_mem_write, VG_(threads)[tid].arch.m_esp, sizeof(void*) );
+ SET_PTHREQ_ESP(tid, VG_(threads)[tid].arch.vex.guest_ESP - sizeof(UWord));
+ * (UInt*)(VG_(threads)[tid].arch.vex.guest_ESP) = arg;
+ VG_TRACK( post_mem_write, VG_(threads)[tid].arch.vex.guest_ESP, sizeof(void*) );
/* Don't mark the pushed return address as readable; any attempt to read
this is an internal valgrind bug since thread_exit_wrapper() should not
return. */
- SET_PTHREQ_ESP(tid, VG_(threads)[tid].arch.m_esp - sizeof(UWord));
- * (UInt*)(VG_(threads)[tid].arch.m_esp) = ret;
+ SET_PTHREQ_ESP(tid, VG_(threads)[tid].arch.vex.guest_ESP - sizeof(UWord));
+ * (UInt*)(VG_(threads)[tid].arch.vex.guest_ESP) = ret;
}
void VGA_(thread_initial_stack)(ThreadId tid, UWord arg, Addr ret)
UInt *VGA_(reg_addr_from_BB)(Int regno)
{
- Int r;
switch (regno) {
- case R_EAX: r = VGOFF_(m_eax); break;
- case R_ECX: r = VGOFF_(m_ecx); break;
- case R_EDX: r = VGOFF_(m_edx); break;
- case R_EBX: r = VGOFF_(m_ebx); break;
- case R_ESP: r = VGOFF_(m_esp); break;
- case R_EBP: r = VGOFF_(m_ebp); break;
- case R_ESI: r = VGOFF_(m_esi); break;
- case R_EDI: r = VGOFF_(m_edi); break;
- default:
- return NULL;
+ case R_EAX: return &(BASEBLOCK_VEX->guest_EAX);
+ case R_ECX: return &(BASEBLOCK_VEX->guest_ECX);
+ case R_EDX: return &(BASEBLOCK_VEX->guest_EDX);
+ case R_EBX: return &(BASEBLOCK_VEX->guest_EBX);
+ case R_ESP: return &(BASEBLOCK_VEX->guest_ESP);
+ case R_EBP: return &(BASEBLOCK_VEX->guest_EBP);
+ case R_ESI: return &(BASEBLOCK_VEX->guest_ESI);
+ case R_EDI: return &(BASEBLOCK_VEX->guest_EDI);
+ default: return NULL;
}
- return &VG_(baseBlock)[r];
}
UInt *VGA_(reg_addr_from_tst)(Int regno, arch_thread_t *arch)
{
switch (regno) {
- case R_EAX: return &arch->m_eax;
- case R_ECX: return &arch->m_ecx;
- case R_EDX: return &arch->m_edx;
- case R_EBX: return &arch->m_ebx;
- case R_ESP: return &arch->m_esp;
- case R_EBP: return &arch->m_ebp;
- case R_ESI: return &arch->m_esi;
- case R_EDI: return &arch->m_edi;
+ case R_EAX: return &arch->vex.guest_EAX;
+ case R_ECX: return &arch->vex.guest_ECX;
+ case R_EDX: return &arch->vex.guest_EDX;
+ case R_EBX: return &arch->vex.guest_EBX;
+ case R_ESP: return &arch->vex.guest_ESP;
+ case R_EBP: return &arch->vex.guest_EBP;
+ case R_ESI: return &arch->vex.guest_ESI;
+ case R_EDI: return &arch->vex.guest_EDI;
default: return NULL;
}
}
{
struct vki_user_regs_struct regs;
- regs.cs = VG_(baseBlock)[VGOFF_(m_cs)];
- regs.ss = VG_(baseBlock)[VGOFF_(m_ss)];
- regs.ds = VG_(baseBlock)[VGOFF_(m_ds)];
- regs.es = VG_(baseBlock)[VGOFF_(m_es)];
- regs.fs = VG_(baseBlock)[VGOFF_(m_fs)];
- regs.gs = VG_(baseBlock)[VGOFF_(m_gs)];
- regs.eax = VG_(baseBlock)[VGOFF_(m_eax)];
- regs.ebx = VG_(baseBlock)[VGOFF_(m_ebx)];
- regs.ecx = VG_(baseBlock)[VGOFF_(m_ecx)];
- regs.edx = VG_(baseBlock)[VGOFF_(m_edx)];
- regs.esi = VG_(baseBlock)[VGOFF_(m_esi)];
- regs.edi = VG_(baseBlock)[VGOFF_(m_edi)];
- regs.ebp = VG_(baseBlock)[VGOFF_(m_ebp)];
- regs.esp = VG_(baseBlock)[VGOFF_(m_esp)];
- regs.eflags = VG_(baseBlock)[VGOFF_(m_eflags)];
- regs.eip = VG_(baseBlock)[VGOFF_(m_eip)];
+ regs.cs = BASEBLOCK_VEX->guest_CS;
+ regs.ss = BASEBLOCK_VEX->guest_SS;
+ regs.ds = BASEBLOCK_VEX->guest_DS;
+ regs.es = BASEBLOCK_VEX->guest_ES;
+ regs.fs = BASEBLOCK_VEX->guest_FS;
+ regs.gs = BASEBLOCK_VEX->guest_GS;
+ regs.eax = BASEBLOCK_VEX->guest_EAX;
+ regs.ebx = BASEBLOCK_VEX->guest_EBX;
+ regs.ecx = BASEBLOCK_VEX->guest_ECX;
+ regs.edx = BASEBLOCK_VEX->guest_EDX;
+ regs.esi = BASEBLOCK_VEX->guest_ESI;
+ regs.edi = BASEBLOCK_VEX->guest_EDI;
+ regs.ebp = BASEBLOCK_VEX->guest_EBP;
+ regs.esp = BASEBLOCK_VEX->guest_ESP;
+ regs.eflags = LibVEX_GuestX86_get_eflags(BASEBLOCK_VEX);
+ regs.eip = BASEBLOCK_VEX->guest_EIP;
return ptrace(PTRACE_SETREGS, pid, NULL, ®s);
}
{
struct vki_user_regs_struct regs;
- regs.cs = arch->m_cs;
- regs.ss = arch->m_ss;
- regs.ds = arch->m_ds;
- regs.es = arch->m_es;
- regs.fs = arch->m_fs;
- regs.gs = arch->m_gs;
- regs.eax = arch->m_eax;
- regs.ebx = arch->m_ebx;
- regs.ecx = arch->m_ecx;
- regs.edx = arch->m_edx;
- regs.esi = arch->m_esi;
- regs.edi = arch->m_edi;
- regs.ebp = arch->m_ebp;
- regs.esp = arch->m_esp;
- regs.eflags = arch->m_eflags;
- regs.eip = arch->m_eip;
+ regs.cs = arch->vex.guest_CS;
+ regs.ss = arch->vex.guest_SS;
+ regs.ds = arch->vex.guest_DS;
+ regs.es = arch->vex.guest_ES;
+ regs.fs = arch->vex.guest_FS;
+ regs.gs = arch->vex.guest_GS;
+ regs.eax = arch->vex.guest_EAX;
+ regs.ebx = arch->vex.guest_EBX;
+ regs.ecx = arch->vex.guest_ECX;
+ regs.edx = arch->vex.guest_EDX;
+ regs.esi = arch->vex.guest_ESI;
+ regs.edi = arch->vex.guest_EDI;
+ regs.ebp = arch->vex.guest_EBP;
+ regs.esp = arch->vex.guest_ESP;
+ regs.eflags = LibVEX_GuestX86_get_eflags(&arch->vex);
+ regs.eip = arch->vex.guest_EIP;
return ptrace(PTRACE_SETREGS, pid, NULL, ®s);
}
Basic types
------------------------------------------------------------------ */
+#include "libvex_basictypes.h"
+
+/* VEX defines Char, UChar, Short, UShort, Int, UInt, Long, ULong,
+ Addr32, Addr64, HWord, HChar, Bool, False and True. */
+
// By choosing the right types, we can get these right for 32-bit and 64-bit
// platforms without having to do any conditional compilation or anything.
//
// Size in bits on: 32-bit archs 64-bit archs
// ------------ ------------
-typedef unsigned char UChar; // 8 8
-typedef unsigned short UShort; // 16 16
-typedef unsigned int UInt; // 32 32
typedef unsigned long UWord; // 32 64
-typedef unsigned long long ULong; // 64 64
-typedef signed char Char; // 8 8
-typedef signed short Short; // 16 16
-typedef signed int Int; // 32 32
typedef signed long Word; // 32 64
-typedef signed long long Long; // 64 64
typedef UWord Addr; // 32 64
typedef Word OffT; // 32 64
-typedef UChar Bool; // 8 8
-#define False ((Bool)0)
-#define True ((Bool)1)
/* ---------------------------------------------------------------------
Where to send bug reports to.
#include "tool_arch.h" // arch-specific tool stuff
#include "vki.h"
+#include "libvex.h"
+#include "libvex_ir.h"
+
/*====================================================================*/
/*=== Build options and table sizes. ===*/
/*====================================================================*/
UInt *eax_ret, UInt *ebx_ret,
UInt *ecx_ret, UInt *edx_ret );
-/*====================================================================*/
-/*=== UCode definition ===*/
-/*====================================================================*/
-
-/* Tags which describe what operands are. Must fit into 4 bits, which
- they clearly do. */
-typedef
-enum { TempReg =0, /* virtual temp-reg */
- ArchReg =1, /* simulated integer reg */
- ArchRegS =2, /* simulated segment reg */
- RealReg =3, /* real machine's real reg */
- SpillNo =4, /* spill slot location */
- Literal =5, /* literal; .lit32 field has actual value */
- Lit16 =6, /* literal; .val[123] field has actual value */
- NoValue =7 /* operand not in use */
- }
- Tag;
-
-/* Invalid register numbers (can't be negative) */
-#define INVALID_TEMPREG 999999999
-#define INVALID_REALREG 999999999
-
-/* Microinstruction opcodes. */
-typedef
- enum {
- NOP, /* Null op */
-
- LOCK, /* Indicate the existence of a LOCK prefix (functionally NOP) */
-
- /* Moving values around */
- GET, PUT, /* simulated register <--> TempReg */
- GETF, PUTF, /* simulated %eflags <--> TempReg */
- LOAD, STORE, /* memory <--> TempReg */
- MOV, /* TempReg <--> TempReg */
- CMOV, /* Used for cmpxchg and cmov */
-
- /* Arithmetic/logical ops */
- MUL, UMUL, /* Multiply */
- ADD, ADC, SUB, SBB, /* Add/subtract (w/wo carry) */
- AND, OR, XOR, NOT, /* Boolean ops */
- SHL, SHR, SAR, ROL, ROR, RCL, RCR, /* Shift/rotate (w/wo carry) */
- NEG, /* Negate */
- INC, DEC, /* Increment/decrement */
- BSWAP, /* Big-endian <--> little-endian */
- CC2VAL, /* Condition code --> 0 or 1 */
- WIDEN, /* Signed or unsigned widening */
-
- /* Conditional or unconditional jump */
- JMP,
-
- /* FPU ops */
- FPU, /* Doesn't touch memory */
- FPU_R, FPU_W, /* Reads/writes memory */
-
- /* ------------ MMX ops ------------ */
- /* In this and the SSE encoding, bytes at higher addresses are
- held in bits [7:0] in these 16-bit words. I guess this means
- it is a big-endian encoding. */
-
- /* 1 byte, no memrefs, no iregdefs, copy exactly to the
- output. Held in val1[7:0]. */
- MMX1,
-
- /* 2 bytes, no memrefs, no iregdefs, copy exactly to the
- output. Held in val1[15:0]. */
- MMX2,
-
- /* 3 bytes, no memrefs, no iregdefs, copy exactly to the
- output. Held in val1[15:0] and val2[7:0]. */
- MMX3,
-
- /* 2 bytes, reads/writes mem. Insns of the form
- bbbbbbbb:mod mmxreg r/m.
- Held in val1[15:0], and mod and rm are to be replaced
- at codegen time by a reference to the Temp/RealReg holding
- the address. Arg2 holds this Temp/Real Reg.
- Transfer is always at size 8.
- */
- MMX2_MemRd,
- MMX2_MemWr,
-
- /* 3 bytes, reads/writes mem. Insns of the form
- bbbbbbbb:mod mmxreg r/m:bbbbbbbb
- Held in val1[15:0] and val2[7:0], and mod and rm are to be
- replaced at codegen time by a reference to the Temp/RealReg
- holding the address. Arg2 holds this Temp/Real Reg.
- Transfer is always at size 8.
- */
- MMX2a1_MemRd,
-
- /* 2 bytes, reads/writes an integer ("E") register. Insns of the form
- bbbbbbbb:11 mmxreg ireg.
- Held in val1[15:0], and ireg is to be replaced
- at codegen time by a reference to the relevant RealReg.
- Transfer is always at size 4. Arg2 holds this Temp/Real Reg.
- */
- MMX2_ERegRd,
- MMX2_ERegWr,
-
- /* ------------ SSE/SSE2 ops ------------ */
- /* In the following:
-
- a digit N indicates the next N bytes are to be copied exactly
- to the output.
-
- 'a' indicates a mod-xmmreg-rm byte, where the mod-rm part is
- to be replaced at codegen time to a Temp/RealReg holding the
- address.
-
- 'e' indicates a byte of the form '11 xmmreg ireg', where ireg
- is read or written, and is to be replaced at codegen time by
- a reference to the relevant RealReg. 'e' because it's the E
- reg in Intel encoding parlance.
-
- 'g' indicates a byte of the form '11 ireg xmmreg', where ireg
- is read or written, and is to be replaced at codegen time by
- a reference to the relevant RealReg. 'g' because it's called
- G in Intel parlance. */
-
- /* 3 bytes, no memrefs, no iregdefs, copy exactly to the
- output. Held in val1[15:0] and val2[7:0]. */
- SSE3,
-
- /* 3 bytes, reads/writes mem. Insns of the form
- bbbbbbbb:bbbbbbbb:mod mmxreg r/m.
- Held in val1[15:0] and val2[7:0], and mod and rm are to be
- replaced at codegen time by a reference to the Temp/RealReg
- holding the address. Arg3 holds this Temp/Real Reg.
- Transfer is usually, but not always, at size 16. */
- SSE2a_MemRd,
- SSE2a_MemWr,
-
- /* 4 bytes, writes an integer register. Insns of the form
- bbbbbbbb:bbbbbbbb:11 ireg bbb.
- Held in val1[15:0] and val2[7:0], and ireg is to be replaced
- at codegen time by a reference to the relevant RealReg.
- Transfer is always at size 4. Arg3 holds this Temp/Real Reg.
- */
- SSE2g_RegWr,
-
- /* 5 bytes, writes an integer register. Insns of the form
- bbbbbbbb:bbbbbbbb:11 ireg bbb :bbbbbbbb. Held in
- val1[15:0] and val2[7:0] and lit32[7:0], and ireg is to be
- replaced at codegen time by a reference to the relevant
- RealReg. Transfer is always at size 4. Arg3 holds this
- Temp/Real Reg.
- */
- SSE2g1_RegWr,
-
- /* 5 bytes, reads an integer register. Insns of the form
- bbbbbbbb:bbbbbbbb:11 bbb ireg :bbbbbbbb. Held in
- val1[15:0] and val2[7:0] and lit32[7:0], and ireg is to be
- replaced at codegen time by a reference to the relevant
- RealReg. Transfer is always at size 4. Arg3 holds this
- Temp/Real Reg.
- */
- SSE2e1_RegRd,
-
- /* 4 bytes, no memrefs, no iregdefs, copy exactly to the
- output. Held in val1[15:0] and val2[15:0]. */
- SSE4,
-
- /* 4 bytes, reads/writes mem. Insns of the form
- bbbbbbbb:bbbbbbbb:bbbbbbbb:mod mmxreg r/m.
- Held in val1[15:0] and val2[15:0], and mod and rm are to be
- replaced at codegen time by a reference to the Temp/RealReg
- holding the address. Arg3 holds this Temp/Real Reg.
- Transfer is at stated size. */
- SSE3a_MemRd,
- SSE3a_MemWr,
-
- /* 4 bytes, reads/writes mem. Insns of the form
- bbbbbbbb:bbbbbbbb:mod mmxreg r/m:bbbbbbbb
- Held in val1[15:0] and val2[15:0], and mod and rm are to be
- replaced at codegen time by a reference to the Temp/RealReg
- holding the address. Arg3 holds this Temp/Real Reg.
- Transfer is at stated size. */
- SSE2a1_MemRd,
-
- /* 4 bytes, writes an integer register. Insns of the form
- bbbbbbbb:bbbbbbbb:bbbbbbbb:11 ireg bbb.
- Held in val1[15:0] and val2[15:0], and ireg is to be replaced
- at codegen time by a reference to the relevant RealReg.
- Transfer is always at size 4. Arg3 holds this Temp/Real Reg.
- */
- SSE3g_RegWr,
-
- /* 5 bytes, writes an integer register. Insns of the form
- bbbbbbbb:bbbbbbbb:bbbbbbbb: 11 ireg bbb :bbbbbbbb. Held in
- val1[15:0] and val2[15:0] and lit32[7:0], and ireg is to be
- replaced at codegen time by a reference to the relevant
- RealReg. Transfer is always at size 4. Arg3 holds this
- Temp/Real Reg.
- */
- SSE3g1_RegWr,
-
- /* 4 bytes, reads an integer register. Insns of the form
- bbbbbbbb:bbbbbbbb:bbbbbbbb:11 bbb ireg.
- Held in val1[15:0] and val2[15:0], and ireg is to be replaced
- at codegen time by a reference to the relevant RealReg.
- Transfer is always at size 4. Arg3 holds this Temp/Real Reg.
- */
- SSE3e_RegRd,
- SSE3e_RegWr, /* variant that writes Ereg, not reads it */
-
- /* 5 bytes, reads an integer register. Insns of the form
- bbbbbbbb:bbbbbbbb:bbbbbbbb: 11 bbb ireg :bbbbbbbb. Held in
- val1[15:0] and val2[15:0] and lit32[7:0], and ireg is to be
- replaced at codegen time by a reference to the relevant
- RealReg. Transfer is always at size 4. Arg3 holds this
- Temp/Real Reg.
- */
- SSE3e1_RegRd,
-
- /* 4 bytes, reads memory, writes an integer register, but is
- nevertheless an SSE insn. The insn is of the form
- bbbbbbbb:bbbbbbbb:bbbbbbbb:mod ireg rm where mod indicates
- memory (ie is not 11b) and ireg is the int reg written. The
- first 4 bytes are held in lit32[31:0] since there is
- insufficient space elsewhere. mod and rm are to be replaced
- at codegen time by a reference to the Temp/RealReg holding
- the address. Arg1 holds this Temp/RealReg. ireg is to be
- replaced at codegen time by a reference to the relevant
- RealReg in which the answer is to be written. Arg2 holds
- this Temp/RealReg. Transfer to the destination reg is always
- at size 4. However the memory read can be at sizes 4 or 8
- and so this is what the sz field holds. Note that the 4th
- byte of the instruction (the modrm byte) is redundant, but we
- store it anyway so as to be consistent with all other SSE
- uinstrs.
- */
- SSE3ag_MemRd_RegWr,
-
- /* 5 bytes, no memrefs, no iregdefs, copy exactly to the
- output. Held in val1[15:0], val2[15:0] and val3[7:0]. */
- SSE5,
-
- /* 5 bytes, reads/writes mem. Insns of the form
- bbbbbbbb:bbbbbbbb:bbbbbbbb:mod mmxreg r/m:bbbbbbbb
- Held in val1[15:0], val2[15:0], lit32[7:0].
- mod and rm are to be replaced at codegen time by a reference
- to the Temp/RealReg holding the address. Arg3 holds this
- Temp/Real Reg. Transfer is always at size 16. */
- SSE3a1_MemRd,
-
- /* ------------------------ */
-
- /* Not strictly needed, but improve address calculation translations. */
- LEA1, /* reg2 := const + reg1 */
- LEA2, /* reg3 := const + reg1 + reg2 * 1,2,4 or 8 */
-
- /* Hack for x86 REP insns. Jump to literal if TempReg/RealReg
- is zero. */
- JIFZ,
-
- /* Advance the simulated %eip by some small (< 128) number. */
- INCEIP,
-
- /* Dealing with segment registers */
- GETSEG, PUTSEG, /* simulated segment register <--> TempReg */
- USESEG, /* (LDT/GDT index, virtual addr) --> linear addr */
-
- /* Not for translating x86 calls -- only to call helpers */
- CALLM_S, CALLM_E, /* Mark start/end of CALLM push/pop sequence */
- PUSH, POP, CLEAR, /* Add/remove/zap args for helpers */
- CALLM, /* Call assembly-code helper */
-
- /* Not for translating x86 calls -- only to call C helper functions of
- up to three arguments (or two if the functions has a return value).
- Arguments and return value must be word-sized. More arguments can
- be faked with global variables (eg. use VG_(lit_to_globvar)()).
-
- Seven possibilities: 'arg[123]' show where args go, 'ret' shows
- where return value goes (if present).
-
- CCALL(-, -, - ) void f(void)
- CCALL(arg1, -, - ) void f(UInt arg1)
- CCALL(arg1, arg2, - ) void f(UInt arg1, UInt arg2)
- CCALL(arg1, arg2, arg3) void f(UInt arg1, UInt arg2, UInt arg3)
- CCALL(-, -, ret ) UInt f(UInt)
- CCALL(arg1, -, ret ) UInt f(UInt arg1)
- CCALL(arg1, arg2, ret ) UInt f(UInt arg1, UInt arg2) */
- CCALL,
-
- /* This opcode makes it easy for tools that extend UCode to do this to
- avoid opcode overlap:
-
- enum { EU_OP1 = DUMMY_FINAL_UOPCODE + 1, ... }
-
- WARNING: Do not add new opcodes after this one! They can be added
- before, though. */
- DUMMY_FINAL_UOPCODE
- }
- Opcode;
-
-
-/* Condition codes, using the Intel encoding. CondAlways is an extra. */
-typedef
- enum {
- CondO = 0, /* overflow */
- CondNO = 1, /* no overflow */
- CondB = 2, /* below */
- CondNB = 3, /* not below */
- CondZ = 4, /* zero */
- CondNZ = 5, /* not zero */
- CondBE = 6, /* below or equal */
- CondNBE = 7, /* not below or equal */
- CondS = 8, /* negative */
- CondNS = 9, /* not negative */
- CondP = 10, /* parity even */
- CondNP = 11, /* not parity even */
- CondL = 12, /* jump less */
- CondNL = 13, /* not less */
- CondLE = 14, /* less or equal */
- CondNLE = 15, /* not less or equal */
- CondAlways = 16 /* Jump always */
- }
- Condcode;
-
-
-/* Descriptions of additional properties of *unconditional* jumps. */
-typedef
- enum {
- JmpBoring=0, /* boring unconditional jump */
- JmpCall=1, /* jump due to an x86 call insn */
- JmpRet=2, /* jump due to an x86 ret insn */
- JmpSyscall=3, /* do a system call, then jump */
- JmpClientReq=4,/* do a client request, then jump */
- JmpYield=5 /* do a yield, then jump */
- }
- JmpKind;
-
-
-/* Flags. User-level code can only read/write O(verflow), S(ign),
- Z(ero), A(ux-carry), C(arry), P(arity), and may also write
- D(irection). That's a total of 7 flags. A FlagSet is a bitset,
- thusly:
- 76543210
- DOSZACP
- and bit 7 must always be zero since it is unused.
-
- Note: these Flag? values are **not** the positions in the actual
- %eflags register. */
-
-typedef UChar FlagSet;
-
-#define FlagD (1<<6)
-#define FlagO (1<<5)
-#define FlagS (1<<4)
-#define FlagZ (1<<3)
-#define FlagA (1<<2)
-#define FlagC (1<<1)
-#define FlagP (1<<0)
-
-#define FlagsOSZACP (FlagO | FlagS | FlagZ | FlagA | FlagC | FlagP)
-#define FlagsOSZAP (FlagO | FlagS | FlagZ | FlagA | FlagP)
-#define FlagsOSZCP (FlagO | FlagS | FlagZ | FlagC | FlagP)
-#define FlagsOSACP (FlagO | FlagS | FlagA | FlagC | FlagP)
-#define FlagsSZACP ( FlagS | FlagZ | FlagA | FlagC | FlagP)
-#define FlagsSZAP ( FlagS | FlagZ | FlagA | FlagP)
-#define FlagsSZP ( FlagS | FlagZ | FlagP)
-#define FlagsZCP ( FlagZ | FlagC | FlagP)
-#define FlagsOC (FlagO | FlagC )
-#define FlagsAC ( FlagA | FlagC )
-
-#define FlagsALL (FlagsOSZACP | FlagD)
-#define FlagsEmpty (FlagSet)0
-
-
-/* flag positions in eflags */
-#define EFlagC (1 << 0) /* carry */
-#define EFlagP (1 << 2) /* parity */
-#define EFlagA (1 << 4) /* aux carry */
-#define EFlagZ (1 << 6) /* zero */
-#define EFlagS (1 << 7) /* sign */
-#define EFlagD (1 << 10) /* direction */
-#define EFlagO (1 << 11) /* overflow */
-#define EFlagID (1 << 21) /* changable if CPUID exists */
-
-/* Liveness of general purpose registers, useful for code generation.
- Reg rank order 0..N-1 corresponds to bits 0..N-1, ie. first
- reg's liveness in bit 0, last reg's in bit N-1. Note that
- these rankings don't match the Intel register ordering. */
-typedef UInt RRegSet;
-
-#define ALL_RREGS_DEAD 0 /* 0000...00b */
-#define ALL_RREGS_LIVE ((1 << VG_MAX_REALREGS)-1) /* 0011...11b */
-#define UNIT_RREGSET(rank) (1 << (rank))
-
-#define IS_RREG_LIVE(rank,rregs_live) (rregs_live & UNIT_RREGSET(rank))
-#define SET_RREG_LIVENESS(rank,rregs_live,b) \
- do { RRegSet unit = UNIT_RREGSET(rank); \
- if (b) rregs_live |= unit; \
- else rregs_live &= ~unit; \
- } while(0)
-
-
-/* A Micro (u)-instruction. */
-typedef
- struct {
- /* word 1 */
- UInt lit32; /* 32-bit literal */
-
- /* word 2 */
- UShort val1; /* first operand */
- UShort val2; /* second operand */
-
- /* word 3 */
- UShort val3; /* third operand */
- UChar opcode; /* opcode */
- UShort size; /* data transfer size */
-
- /* word 4 */
- FlagSet flags_r; /* :: FlagSet */
- FlagSet flags_w; /* :: FlagSet */
- UChar tag1:4; /* first operand tag */
- UChar tag2:4; /* second operand tag */
- UChar tag3:4; /* third operand tag */
- UChar extra4b:4; /* Spare field, used by WIDEN for src
- -size, and by LEA2 for scale (1,2,4 or 8),
- and by JMPs for original x86 instr size */
-
- /* word 5 */
- UChar cond; /* condition, for jumps */
- Bool signed_widen:1; /* signed or unsigned WIDEN ? */
- JmpKind jmpkind:3; /* additional properties of unconditional JMP */
-
- /* Additional properties for UInstrs that call C functions:
- - CCALL
- - PUT (when %ESP is the target)
- - possibly tool-specific UInstrs
- */
- UChar argc:2; /* Number of args, max 3 */
- UChar regparms_n:2; /* Number of args passed in registers */
- Bool has_ret_val:1; /* Function has return value? */
-
- /* RealReg liveness; only sensical after reg alloc and liveness
- analysis done. This info is a little bit arch-specific --
- VG_MAX_REALREGS can vary on different architectures. Note that
- to use this information requires converting between register ranks
- and the Intel register numbers, using VG_(realreg_to_rank)()
- and/or VG_(rank_to_realreg)() */
- RRegSet regs_live_after:VG_MAX_REALREGS;
- }
- UInstr;
-
-
-typedef
- struct _UCodeBlock
- UCodeBlock;
-
-extern Int VG_(get_num_instrs) (UCodeBlock* cb);
-extern Int VG_(get_num_temps) (UCodeBlock* cb);
-
-extern UInstr* VG_(get_instr) (UCodeBlock* cb, Int i);
-extern UInstr* VG_(get_last_instr) (UCodeBlock* cb);
-
-
-/*====================================================================*/
-/*=== Instrumenting UCode ===*/
-/*====================================================================*/
-
-/* Maximum number of registers read or written by a single UInstruction. */
-#define VG_MAX_REGS_USED 3
-
-/* Find what this instruction does to its regs, useful for
- analysis/optimisation passes. `tag' indicates whether we're considering
- TempRegs (pre-reg-alloc) or RealRegs (post-reg-alloc). `regs' is filled
- with the affected register numbers, `isWrites' parallels it and indicates
- if the reg is read or written. If a reg is read and written, it will
- appear twice in `regs'. `regs' and `isWrites' must be able to fit
- VG_MAX_REGS_USED elements. */
-extern Int VG_(get_reg_usage) ( UInstr* u, Tag tag, Int* regs, Bool* isWrites );
-
-
-/* Used to register helper functions to be called from generated code. A
- limited number of compact helpers can be registered; the code generated
- to call them is slightly shorter -- so register the mostly frequently
- called helpers as compact. */
-extern void VG_(register_compact_helper) ( Addr a );
-extern void VG_(register_noncompact_helper) ( Addr a );
-
-
-/* ------------------------------------------------------------------ */
-/* Virtual register allocation */
-
-/* Get a new virtual register */
-extern Int VG_(get_new_temp) ( UCodeBlock* cb );
-
-/* Get a new virtual shadow register */
-extern Int VG_(get_new_shadow) ( UCodeBlock* cb );
-
-/* Get a virtual register's corresponding virtual shadow register */
-#define SHADOW(tempreg) ((tempreg)+1)
-
-
-/* ------------------------------------------------------------------ */
-/* Low-level UInstr builders */
-extern void VG_(new_NOP) ( UInstr* u );
-extern void VG_(new_UInstr0) ( UCodeBlock* cb, Opcode opcode, Int sz );
-extern void VG_(new_UInstr1) ( UCodeBlock* cb, Opcode opcode, Int sz,
- Tag tag1, UInt val1 );
-extern void VG_(new_UInstr2) ( UCodeBlock* cb, Opcode opcode, Int sz,
- Tag tag1, UInt val1,
- Tag tag2, UInt val2 );
-extern void VG_(new_UInstr3) ( UCodeBlock* cb, Opcode opcode, Int sz,
- Tag tag1, UInt val1,
- Tag tag2, UInt val2,
- Tag tag3, UInt val3 );
-
-/* Set read/write/undefined flags. Undefined flags are treaten as written,
- but it's worth keeping them logically distinct. */
-extern void VG_(set_flag_fields) ( UCodeBlock* cb, FlagSet fr, FlagSet fw,
- FlagSet fu);
-extern void VG_(set_lit_field) ( UCodeBlock* cb, UInt lit32 );
-extern void VG_(set_ccall_fields) ( UCodeBlock* cb, Addr fn, UChar argc,
- UChar regparms_n, Bool has_ret_val );
-extern void VG_(set_cond_field) ( UCodeBlock* cb, Condcode code );
-extern void VG_(set_widen_fields) ( UCodeBlock* cb, UInt szs, Bool is_signed );
-
-extern void VG_(copy_UInstr) ( UCodeBlock* cb, UInstr* instr );
-
-extern Bool VG_(any_flag_use)( UInstr* u );
-
-/* Macro versions of the above; just shorter to type. */
-#define uInstr0 VG_(new_UInstr0)
-#define uInstr1 VG_(new_UInstr1)
-#define uInstr2 VG_(new_UInstr2)
-#define uInstr3 VG_(new_UInstr3)
-#define uLiteral VG_(set_lit_field)
-#define uCCall VG_(set_ccall_fields)
-#define uCond VG_(set_cond_field)
-#define uWiden VG_(set_widen_fields)
-#define uFlagsRWU VG_(set_flag_fields)
-#define newTemp VG_(get_new_temp)
-#define newShadow VG_(get_new_shadow)
-
-/* Refer to `the last instruction stuffed in' (can be lvalue). */
-#define LAST_UINSTR(cb) (cb)->instrs[(cb)->used-1]
-
-
-/* ------------------------------------------------------------------ */
-/* Higher-level UInstr sequence builders */
-
-extern void VG_(lit_to_reg) ( UCodeBlock* cb, UInt lit, UInt t );
-extern UInt VG_(lit_to_newreg) ( UCodeBlock* cb, UInt lit );
-
-#define CB_F UCodeBlock* cb, Addr f
-#define EV extern void
-#define RPn UInt regparms_n
-
-/* Various CCALL builders, of the form "ccall_<args>_<retval>". 'R'
- represents a TempReg, 'L' represents a literal, '0' represents nothing
- (ie. no args, or no return value). */
-
-EV VG_(ccall_0_0) ( CB_F );
-
-EV VG_(ccall_R_0) ( CB_F, UInt R1, RPn );
-EV VG_(ccall_L_0) ( CB_F, UInt L1, RPn );
-EV VG_(ccall_R_R) ( CB_F, UInt R1, UInt R_ret, RPn );
-EV VG_(ccall_L_R) ( CB_F, UInt L1, UInt R_ret, RPn );
-
-EV VG_(ccall_RR_0) ( CB_F, UInt R1, UInt R2, RPn );
-EV VG_(ccall_RL_0) ( CB_F, UInt R1, UInt RL, RPn );
-EV VG_(ccall_LR_0) ( CB_F, UInt L1, UInt R2, RPn );
-EV VG_(ccall_LL_0) ( CB_F, UInt L1, UInt L2, RPn );
-EV VG_(ccall_RR_R) ( CB_F, UInt R1, UInt R2, UInt R_ret, RPn );
-EV VG_(ccall_RL_R) ( CB_F, UInt R1, UInt L2, UInt R_ret, RPn );
-EV VG_(ccall_LR_R) ( CB_F, UInt L1, UInt R2, UInt R_ret, RPn );
-EV VG_(ccall_LL_R) ( CB_F, UInt L1, UInt L2, UInt R_ret, RPn );
-
-EV VG_(ccall_RRR_0) ( CB_F, UInt R1, UInt R2, UInt R3, RPn );
-EV VG_(ccall_RLL_0) ( CB_F, UInt R1, UInt L2, UInt L3, RPn );
-EV VG_(ccall_LRR_0) ( CB_F, UInt L1, UInt R2, UInt R3, RPn );
-EV VG_(ccall_LLR_0) ( CB_F, UInt L1, UInt L2, UInt R3, RPn );
-EV VG_(ccall_LLL_0) ( CB_F, UInt L1, UInt L2, UInt L3, RPn );
-
-#undef CB_F
-#undef EV
-#undef RPn
-
-/* One way around the 3-arg C function limit is to pass args via global
- * variables... ugly, but it works. */
-void VG_(reg_to_globvar)(UCodeBlock* cb, UInt t, UInt* globvar_ptr);
-void VG_(lit_to_globvar)(UCodeBlock* cb, UInt lit, UInt* globvar_ptr);
-
-
-/* Old, deprecated versions of some of the helpers (DO NOT USE) */
-extern void VG_(call_helper_0_0) ( UCodeBlock* cb, Addr f);
-extern void VG_(call_helper_1_0) ( UCodeBlock* cb, Addr f, UInt arg1,
- UInt regparms_n);
-extern void VG_(call_helper_2_0) ( UCodeBlock* cb, Addr f, UInt arg1, UInt arg2,
- UInt regparms_n);
-extern void VG_(set_global_var) ( UCodeBlock* cb, Addr globvar_ptr, UInt val);
-extern void VG_(set_global_var_tempreg) ( UCodeBlock* cb, Addr globvar_ptr,
- UInt t_val);
-
-/* ------------------------------------------------------------------ */
-/* Allocating/freeing basic blocks of UCode */
-extern UCodeBlock* VG_(setup_UCodeBlock) ( UCodeBlock* cb );
-extern void VG_(free_UCodeBlock) ( UCodeBlock* cb );
-
-/* ------------------------------------------------------------------ */
-/* UCode pretty/ugly printing. Probably only useful to call from a tool
- if VG_(needs).extended_UCode == True. */
-
-/* When True, all generated code is/should be printed. */
-extern Bool VG_(print_codegen);
-
-/* Pretty/ugly printing functions */
-extern void VG_(pp_UCodeBlock) ( UCodeBlock* cb, Char* title );
-extern void VG_(pp_UInstr) ( Int instrNo, UInstr* u );
-extern void VG_(pp_UInstr_regs) ( Int instrNo, UInstr* u );
-extern void VG_(up_UInstr) ( Int instrNo, UInstr* u );
-extern Char* VG_(name_UOpcode) ( Bool upper, Opcode opc );
-extern Char* VG_(name_UCondcode) ( Condcode cond );
-extern void VG_(pp_UOperand) ( UInstr* u, Int operandNo,
- Int sz, Bool parens );
/* ------------------------------------------------------------------ */
/* Accessing archregs and their shadows */
+/* ToDo: is this still needed ? */
extern UInt VG_(get_archreg) ( UInt archreg );
extern UInt VG_(get_thread_archreg) ( ThreadId tid, UInt archreg );
extern void VG_(set_thread_shadow_archreg) ( ThreadId tid, UInt archreg,
UInt val );
-/*====================================================================*/
-/*=== Generating x86 code from UCode ===*/
-/*====================================================================*/
-
-/* All this only necessary for tools with VG_(needs).extends_UCode == True. */
-
+/* ToDo: FIX */
/* This is the Intel register encoding -- integer regs. */
#define R_EAX 0
#define R_ECX 1
#define R_ESI 6
#define R_EDI 7
-#define R_AL (0+R_EAX)
-#define R_CL (0+R_ECX)
-#define R_DL (0+R_EDX)
-#define R_BL (0+R_EBX)
-#define R_AH (4+R_EAX)
-#define R_CH (4+R_ECX)
-#define R_DH (4+R_EDX)
-#define R_BH (4+R_EBX)
-
-/* This is the Intel register encoding -- segment regs. */
-#define R_ES 0
-#define R_CS 1
-#define R_SS 2
-#define R_DS 3
-#define R_FS 4
-#define R_GS 5
-
-/* For pretty printing x86 code */
-extern const Char* VG_(name_of_mmx_gran) ( UChar gran );
-extern const Char* VG_(name_of_mmx_reg) ( Int mmxreg );
-extern const Char* VG_(name_of_seg_reg) ( Int sreg );
-extern const Char* VG_(name_of_int_reg) ( Int size, Int reg );
-extern const Char VG_(name_of_int_size) ( Int size );
-
-/* Shorter macros for convenience */
-#define nameIReg VG_(name_of_int_reg)
-#define nameISize VG_(name_of_int_size)
-#define nameSReg VG_(name_of_seg_reg)
-#define nameMMXReg VG_(name_of_mmx_reg)
-#define nameMMXGran VG_(name_of_mmx_gran)
-#define nameXMMReg VG_(name_of_xmm_reg)
-
-/* Randomly useful things */
-extern UInt VG_(extend_s_8to32) ( UInt x );
-
-/* Code emitters */
-extern void VG_(emitB) ( UInt b );
-extern void VG_(emitW) ( UInt w );
-extern void VG_(emitL) ( UInt l );
-extern void VG_(new_emit) ( Bool upd_cc, FlagSet uses_flags, FlagSet sets_flags );
-
-/* Finding offsets */
-extern Int VG_(helper_offset) ( Addr a );
-extern Int VG_(shadow_reg_offset) ( Int arch );
-extern Int VG_(shadow_flags_offset) ( void );
-
-/* Convert reg ranks <-> Intel register ordering, for using register
- liveness information. */
-extern Int VG_(realreg_to_rank) ( Int realreg );
-extern Int VG_(rank_to_realreg) ( Int rank );
-
-/* Call a subroutine. Does no argument passing, stack manipulations, etc. */
-extern void VG_(synth_call) ( Bool ensure_shortform, Int word_offset,
- Bool upd_cc, FlagSet use_flags, FlagSet set_flags );
-
-/* For calling C functions -- saves caller save regs, pushes args, calls,
- clears the stack, restores caller save regs. `fn' must be registered in
- the baseBlock first. Acceptable tags are RealReg and Literal. Optimises
- things, eg. by not preserving non-live caller-save registers.
-
- WARNING: a UInstr should *not* be translated with synth_ccall() followed
- by some other x86 assembly code; this will invalidate the results of
- vg_realreg_liveness_analysis() and everything will fall over. */
-extern void VG_(synth_ccall) ( Addr fn, Int argc, Int regparms_n, UInt argv[],
- Tag tagv[], Int ret_reg,
- RRegSet regs_live_before,
- RRegSet regs_live_after );
-
-/* Addressing modes */
-extern void VG_(emit_amode_offregmem_reg)( Int off, Int regmem, Int reg );
-extern void VG_(emit_amode_ereg_greg) ( Int e_reg, Int g_reg );
-
-/* v-size (4, or 2 with OSO) insn emitters */
-extern void VG_(emit_movv_offregmem_reg) ( Int sz, Int off, Int areg, Int reg );
-extern void VG_(emit_movv_reg_offregmem) ( Int sz, Int reg, Int off, Int areg );
-extern void VG_(emit_movv_reg_reg) ( Int sz, Int reg1, Int reg2 );
-extern void VG_(emit_nonshiftopv_lit_reg)( Bool upd_cc, Int sz, Opcode opc, UInt lit,
- Int reg );
-extern void VG_(emit_shiftopv_lit_reg) ( Bool upd_cc, Int sz, Opcode opc, UInt lit,
- Int reg );
-extern void VG_(emit_nonshiftopv_reg_reg)( Bool upd_cc, Int sz, Opcode opc,
- Int reg1, Int reg2 );
-extern void VG_(emit_movv_lit_reg) ( Int sz, UInt lit, Int reg );
-extern void VG_(emit_unaryopv_reg) ( Bool upd_cc, Int sz, Opcode opc, Int reg );
-extern void VG_(emit_pushv_reg) ( Int sz, Int reg );
-extern void VG_(emit_popv_reg) ( Int sz, Int reg );
-
-extern void VG_(emit_pushl_lit32) ( UInt int32 );
-extern void VG_(emit_pushl_lit8) ( Int lit8 );
-extern void VG_(emit_cmpl_zero_reg) ( Bool upd_cc, Int reg );
-extern void VG_(emit_swapl_reg_EAX) ( Int reg );
-extern void VG_(emit_movv_lit_offregmem) ( Int sz, UInt lit, Int off,
- Int memreg );
-
-/* b-size (1 byte) instruction emitters */
-extern void VG_(emit_movb_lit_offregmem) ( UInt lit, Int off, Int memreg );
-extern void VG_(emit_movb_reg_offregmem) ( Int reg, Int off, Int areg );
-extern void VG_(emit_unaryopb_reg) ( Bool upd_cc, Opcode opc, Int reg );
-extern void VG_(emit_testb_lit_reg) ( Bool upd_cc, UInt lit, Int reg );
-
-/* zero-extended load emitters */
-extern void VG_(emit_movzbl_offregmem_reg) ( Bool bounds, Int off, Int regmem, Int reg );
-extern void VG_(emit_movzwl_offregmem_reg) ( Bool bounds, Int off, Int areg, Int reg );
-extern void VG_(emit_movzwl_regmem_reg) ( Bool bounds, Int reg1, Int reg2 );
-
-/* misc instruction emitters */
-extern void VG_(emit_call_reg) ( Int reg );
-extern void VG_(emit_add_lit_to_esp) ( Int lit );
-extern void VG_(emit_pushal) ( void );
-extern void VG_(emit_popal) ( void );
-extern void VG_(emit_AMD_prefetch_reg) ( Int reg );
-
-/* jump emitters */
-extern void VG_(init_target) ( Int *tgt );
-
-extern void VG_(target_back) ( Int *tgt );
-extern void VG_(target_forward) ( Int *tgt );
-extern void VG_(emit_target_delta) ( Int *tgt );
-
-typedef enum {
- JP_NONE, /* no prediction */
- JP_TAKEN, /* predict taken */
- JP_NOT_TAKEN, /* predict not taken */
-} JumpPred;
-
-extern void VG_(emit_jcondshort_delta) ( Bool simd_cc, Condcode cond, Int delta, JumpPred );
-extern void VG_(emit_jcondshort_target)( Bool simd_cc, Condcode cond, Int *tgt, JumpPred );
/*====================================================================*/
#define REGPARM(n) __attribute__((regparm(n)))
-// Accessors for the baseBlock
-#define R_STACK_PTR R_ESP
-#define R_FRAME_PTR R_EBP
-
-#define FIRST_ARCH_REG R_EAX
-#define LAST_ARCH_REG R_EDI
-
-#define N_ARCH_REGS 8
-
#define MIN_INSTR_SIZE 1
#define MAX_INSTR_SIZE 16
-/* Total number of integer registers available for allocation -- all of
- them except %esp (points to Valgrind's stack) and %ebp (permanently
- points at the baseBlock).
-
- If you increase this you'll have to also change at least these:
- - VG_(rank_to_realreg)()
- - VG_(realreg_to_rank)()
- - ppRegsLiveness()
- - the RegsLive type (maybe -- RegsLive type must have more than
- VG_MAX_REALREGS bits)
-
- You can decrease it, and performance will drop because more spills will
- occur. If you decrease it too much, everything will fall over.
-
- Do not change this unless you really know what you are doing! */
-#define VG_MAX_REALREGS 6
-
-
-/*====================================================================*/
-/*=== Instrumenting UCode ===*/
-/*====================================================================*/
-
-/* ------------------------------------------------------------------ */
-/* Offsets of addresses of helper functions. A "helper" function is one
- which is called from generated code via CALLM. */
-
-// XXX: eventually these should be private to the x86 part, not visible to
-// tools, and the IR should provide a better way than this to see what the
-// original instruction was.
-
-extern Int VGOFF_(helper_idiv_64_32);
-extern Int VGOFF_(helper_div_64_32);
-extern Int VGOFF_(helper_idiv_32_16);
-extern Int VGOFF_(helper_div_32_16);
-extern Int VGOFF_(helper_idiv_16_8);
-extern Int VGOFF_(helper_div_16_8);
-
-extern Int VGOFF_(helper_imul_32_64);
-extern Int VGOFF_(helper_mul_32_64);
-extern Int VGOFF_(helper_imul_16_32);
-extern Int VGOFF_(helper_mul_16_32);
-extern Int VGOFF_(helper_imul_8_16);
-extern Int VGOFF_(helper_mul_8_16);
-
-extern Int VGOFF_(helper_CLD);
-extern Int VGOFF_(helper_STD);
-extern Int VGOFF_(helper_get_dirflag);
-
-extern Int VGOFF_(helper_CLC);
-extern Int VGOFF_(helper_STC);
-extern Int VGOFF_(helper_CMC);
-
-extern Int VGOFF_(helper_shldl);
-extern Int VGOFF_(helper_shldw);
-extern Int VGOFF_(helper_shrdl);
-extern Int VGOFF_(helper_shrdw);
-
-extern Int VGOFF_(helper_RDTSC);
-extern Int VGOFF_(helper_CPUID);
-
-extern Int VGOFF_(helper_IN);
-extern Int VGOFF_(helper_OUT);
-
-extern Int VGOFF_(helper_bsfw);
-extern Int VGOFF_(helper_bsfl);
-extern Int VGOFF_(helper_bsrw);
-extern Int VGOFF_(helper_bsrl);
-
-extern Int VGOFF_(helper_fstsw_AX);
-extern Int VGOFF_(helper_SAHF);
-extern Int VGOFF_(helper_LAHF);
-extern Int VGOFF_(helper_DAS);
-extern Int VGOFF_(helper_DAA);
-extern Int VGOFF_(helper_AAS);
-extern Int VGOFF_(helper_AAA);
-extern Int VGOFF_(helper_AAD);
-extern Int VGOFF_(helper_AAM);
-
-extern Int VGOFF_(helper_cmpxchg8b);
-
#endif // __X86_TOOL_ARCH_H
projects / thirdparty / valgrind.git / commitdiff
