soc: qcom: geni-se: Cleanup register defines and update copyright

Refactor register macros for consistency and clarity and remove redundant
definitions and update naming for better alignment.
Update copyright to include Qualcomm Technologies, Inc.

Signed-off-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250911043256.3523057-3-viken.dadhaniya@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c
index 3c3b796333a61e2664d54c2fc85d6894a128655d..e8ab2833815eb9ca038a3078f73be97271fe80ff 100644 (file)
--- a/drivers/soc/qcom/qcom-geni-se.c
+++ b/drivers/soc/qcom/qcom-geni-se.c
@@ -1,5 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0
-// Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
+/*
+ *  Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
+ *  Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
 
 /* Disable MMIO tracing to prevent excessive logging of unwanted MMIO traces */
 #define __DISABLE_TRACE_MMIO__
@@ -110,22 +113,20 @@ struct geni_se_desc {
 static const char * const icc_path_names[] = {"qup-core", "qup-config",
                                                "qup-memory"};
 
-#define QUP_HW_VER_REG                 0x4
+/* Common QUPV3 registers */
+#define QUPV3_HW_VER_REG               0x4
 
 /* Common SE registers */
-#define GENI_INIT_CFG_REVISION         0x0
-#define GENI_S_INIT_CFG_REVISION       0x4
-#define GENI_OUTPUT_CTRL               0x24
-#define GENI_CGC_CTRL                  0x28
-#define GENI_CLK_CTRL_RO               0x60
-#define GENI_FW_S_REVISION_RO          0x6c
+#define SE_GENI_INIT_CFG_REVISION      0x0
+#define SE_GENI_S_INIT_CFG_REVISION    0x4
+#define SE_GENI_CGC_CTRL               0x28
+#define SE_GENI_CLK_CTRL_RO            0x60
+#define SE_GENI_FW_S_REVISION_RO       0x6c
 #define SE_GENI_BYTE_GRAN              0x254
 #define SE_GENI_TX_PACKING_CFG0                0x260
 #define SE_GENI_TX_PACKING_CFG1                0x264
 #define SE_GENI_RX_PACKING_CFG0                0x284
 #define SE_GENI_RX_PACKING_CFG1                0x288
-#define SE_GENI_M_GP_LENGTH            0x910
-#define SE_GENI_S_GP_LENGTH            0x914
 #define SE_DMA_TX_PTR_L                        0xc30
 #define SE_DMA_TX_PTR_H                        0xc34
 #define SE_DMA_TX_ATTR                 0xc38
@@ -142,7 +143,6 @@ static const char * const icc_path_names[] = {"qup-core", "qup-config",
 #define SE_DMA_RX_IRQ_EN               0xd48
 #define SE_DMA_RX_IRQ_EN_SET           0xd4c
 #define SE_DMA_RX_IRQ_EN_CLR           0xd50
-#define SE_DMA_RX_LEN_IN               0xd54
 #define SE_DMA_RX_MAX_BURST            0xd5c
 #define SE_DMA_RX_FLUSH                        0xd60
 #define SE_GSI_EVENT_EN                        0xe18
@@ -179,7 +179,7 @@ static const char * const icc_path_names[] = {"qup-core", "qup-config",
 /* SE_DMA_GENERAL_CFG */
 #define DMA_RX_CLK_CGC_ON              BIT(0)
 #define DMA_TX_CLK_CGC_ON              BIT(1)
-#define DMA_AHB_SLV_CFG_ON             BIT(2)
+#define DMA_AHB_SLV_CLK_CGC_ON         BIT(2)
 #define AHB_SEC_SLV_CLK_CGC_ON         BIT(3)
 #define DUMMY_RX_NON_BUFFERABLE                BIT(4)
 #define RX_DMA_ZERO_PADDING_EN         BIT(5)
@@ -196,7 +196,7 @@ u32 geni_se_get_qup_hw_version(struct geni_se *se)
 {
        struct geni_wrapper *wrapper = se->wrapper;
 
-       return readl_relaxed(wrapper->base + QUP_HW_VER_REG);
+       return readl_relaxed(wrapper->base + QUPV3_HW_VER_REG);
 }
 EXPORT_SYMBOL_GPL(geni_se_get_qup_hw_version);
 
@@ -220,12 +220,12 @@ static void geni_se_io_init(void __iomem *base)
 {
        u32 val;
 
-       val = readl_relaxed(base + GENI_CGC_CTRL);
+       val = readl_relaxed(base + SE_GENI_CGC_CTRL);
        val |= DEFAULT_CGC_EN;
-       writel_relaxed(val, base + GENI_CGC_CTRL);
+       writel_relaxed(val, base + SE_GENI_CGC_CTRL);
 
        val = readl_relaxed(base + SE_DMA_GENERAL_CFG);
-       val |= AHB_SEC_SLV_CLK_CGC_ON | DMA_AHB_SLV_CFG_ON;
+       val |= AHB_SEC_SLV_CLK_CGC_ON | DMA_AHB_SLV_CLK_CGC_ON;
        val |= DMA_TX_CLK_CGC_ON | DMA_RX_CLK_CGC_ON;
        writel_relaxed(val, base + SE_DMA_GENERAL_CFG);