x86/vmscape: Warn when STIBP is disabled with SMT

commit b7cc9887231526ca4fa89f3fa4119e47c2dc7b1e upstream.

Cross-thread attacks are generally harder as they require the victim to be
co-located on a core. However, with VMSCAPE the adversary targets belong to
the same guest execution, that are more likely to get co-located. In
particular, a thread that is currently executing userspace hypervisor
(after the IBPB) may still be targeted by a guest execution from a sibling
thread.

Issue a warning about the potential risk, except when:

- SMT is disabled
- STIBP is enabled system-wide
- Intel eIBRS is enabled (which implies STIBP protection)

Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Signed-off-by: Amit Shah <amit.shah@amd.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index 56102a870cd5cea683581469bbaf215056555c20..8794e3f4974b36c2b8b2295ce77542a246074ddb 100644 (file)
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -2751,6 +2751,7 @@ static void __init vmscape_select_mitigation(void)
 #define MDS_MSG_SMT "MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more details.\n"
 #define TAA_MSG_SMT "TAA CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/tsx_async_abort.html for more details.\n"
 #define MMIO_MSG_SMT "MMIO Stale Data CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/processor_mmio_stale_data.html for more details.\n"
+#define VMSCAPE_MSG_SMT "VMSCAPE: SMT on, STIBP is required for full protection. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/vmscape.html for more details.\n"
 
 void cpu_bugs_smt_update(void)
 {
@@ -2823,6 +2824,28 @@ void cpu_bugs_smt_update(void)
                break;
        }
 
+       switch (vmscape_mitigation) {
+       case VMSCAPE_MITIGATION_NONE:
+       case VMSCAPE_MITIGATION_AUTO:
+               break;
+       case VMSCAPE_MITIGATION_IBPB_ON_VMEXIT:
+       case VMSCAPE_MITIGATION_IBPB_EXIT_TO_USER:
+               /*
+                * Hypervisors can be attacked across-threads, warn for SMT when
+                * STIBP is not already enabled system-wide.
+                *
+                * Intel eIBRS (!AUTOIBRS) implies STIBP on.
+                */
+               if (!sched_smt_active() ||
+                   spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT ||
+                   spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED ||
+                   (spectre_v2_in_eibrs_mode(spectre_v2_enabled) &&
+                    !boot_cpu_has(X86_FEATURE_AUTOIBRS)))
+                       break;
+               pr_warn_once(VMSCAPE_MSG_SMT);
+               break;
+       }
+
        mutex_unlock(&spec_ctrl_mutex);
 }