drm/msm: adreno: a6xx: enable GMU bandwidth voting for x1e80100 GPU

The Adreno GPU Management Unit (GMU) can also scale DDR Bandwidth along
the Frequency and Power Domain level, but by default we leave the
OPP core scale the interconnect ddr path.

Declare the Bus Control Modules (BCMs) and the corresponding parameters
in the GPU info struct to allow the GMU to vote for the bandwidth.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/665778/
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
index 00e1afd46b81546eec03e22cda9e9a604f6f3b60..892f98b1f2ae582268adebd758437ff60456cdd5 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
@@ -1440,6 +1440,17 @@ static const struct adreno_info a7xx_gpus[] = {
                        .pwrup_reglist = &a7xx_pwrup_reglist,
                        .gmu_chipid = 0x7050001,
                        .gmu_cgc_mode = 0x00020202,
+                       .bcms = (const struct a6xx_bcm[]) {
+                               { .name = "SH0", .buswidth = 16 },
+                               { .name = "MC0", .buswidth = 4 },
+                               {
+                                       .name = "ACV",
+                                       .fixed = true,
+                                       .perfmode = BIT(3),
+                                       .perfmode_bw = 16500000,
+                               },
+                               { /* sentinel */ },
+                       },
                },
                .preempt_record_size = 4192 * SZ_1K,
                .speedbins = ADRENO_SPEEDBINS(