net: stmmac: mdio: use same test for MDC clock divisor lookups

Use the same frequency test for all clk_csr value lookups (clock
rate > table rate). This has the side effect that the standard rate
table results in the divider being used for the maximum frequency
for the divider rather than the next higher divider. This still
allows MDC to meet the IEE 802.3 specification, but at a rate closer
to 2.5MHz for these frequencies.

Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Tested-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Link: https://patch.msgid.link/E1vy6A4-0000000Btwj-0ATB@rmk-PC.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h
index 42a48f655849668cbff8fe7f8b94d0252612258c..e4ce1167ebabe7268595ce8330cd489820dd28c7 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/common.h
+++ b/drivers/net/ethernet/stmicro/stmmac/common.h
@@ -257,6 +257,7 @@ struct stmmac_safety_stats {
        (sizeof(struct stmmac_safety_stats) / sizeof(unsigned long))
 
 /* CSR Frequency Access Defines*/
+#define CSR_F_20M      20000000
 #define CSR_F_35M      35000000
 #define CSR_F_60M      60000000
 #define CSR_F_100M     100000000

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
index c4123d2260bdede02bf3b321b8b5acb509f1bc3c..6292911fb54b68ce504be29670f7e5a2cb34a05b 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
@@ -484,15 +484,16 @@ struct stmmac_clk_rate {
  * clock frequencies.
  */
 static const struct stmmac_clk_rate stmmac_std_csr_to_mdc[] = {
-       { CSR_F_35M, STMMAC_CSR_20_35M },
-       { CSR_F_60M, STMMAC_CSR_35_60M },
-       { CSR_F_100M, STMMAC_CSR_60_100M },
-       { CSR_F_150M, STMMAC_CSR_100_150M },
-       { CSR_F_250M, STMMAC_CSR_150_250M },
-       { CSR_F_300M, STMMAC_CSR_250_300M },
-       { CSR_F_500M, STMMAC_CSR_300_500M },
-       { CSR_F_800M, STMMAC_CSR_500_800M },
-       { },
+       { CSR_F_800M, ~0 },
+       { CSR_F_500M, STMMAC_CSR_500_800M },
+       { CSR_F_300M, STMMAC_CSR_300_500M },
+       { CSR_F_250M, STMMAC_CSR_250_300M },
+       { CSR_F_150M, STMMAC_CSR_150_250M },
+       { CSR_F_100M, STMMAC_CSR_100_150M },
+       { CSR_F_60M,  STMMAC_CSR_60_100M },
+       { CSR_F_35M,  STMMAC_CSR_35_60M },
+       { CSR_F_20M,  STMMAC_CSR_20_35M },
+       { 0, ~0 },
 };
 
 /* The sun8i clk_csr_i to GMII_Address CR field mapping uses rate as the
@@ -548,13 +549,12 @@ static u32 stmmac_clk_csr_set(struct stmmac_priv *priv)
         * divider.
         */
        for (i = 0; stmmac_std_csr_to_mdc[i].rate; i++)
-               if (clk_rate < stmmac_std_csr_to_mdc[i].rate) {
-                       value = stmmac_std_csr_to_mdc[i].cr;
+               if (clk_rate > stmmac_std_csr_to_mdc[i].rate)
                        break;
-               }
+       if (stmmac_std_csr_to_mdc[i].cr != (u8)~0)
+               value = stmmac_std_csr_to_mdc[i].cr;
 
        if (priv->plat->flags & STMMAC_FLAG_HAS_SUN8I) {
-               /* Note the different test - this is intentional. */
                for (i = 0; stmmac_sun8i_csr_to_mdc[i].rate; i++)
                        if (clk_rate > stmmac_sun8i_csr_to_mdc[i].rate)
                                break;
@@ -562,7 +562,6 @@ static u32 stmmac_clk_csr_set(struct stmmac_priv *priv)
        }
 
        if (priv->plat->core_type == DWMAC_CORE_XGMAC) {
-               /* Note the different test - this is intentional. */
                for (i = 0; stmmac_xgmac_csr_to_mdc[i].rate; i++)
                        if (clk_rate > stmmac_xgmac_csr_to_mdc[i].rate)
                                break;