drm/tidss: dispc: Switch VP_REG_GET to using a mask

The VP_REG_GET function takes the start and end bits as parameter and
will generate a mask out of them.

This makes it difficult to share the masks between callers, since we now
need two arguments and to keep them consistent.

Let's change VP_REG_GET to take the mask as an argument instead, and let
the caller create the mask. Eventually, this mask will be moved to a
define.

Signed-off-by: Maxime Ripard <mripard@kernel.org>
Link: https://lore.kernel.org/r/20250827-drm-tidss-field-api-v3-11-7689b664cc63@kernel.org
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>

diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c
index 27ac57d770327707c3b6d8bc97a683e4d770cffa..3d807b129c09f1b78016e9d04fa501ed745e5aad 100644 (file)
--- a/drivers/gpu/drm/tidss/tidss_dispc.c
+++ b/drivers/gpu/drm/tidss/tidss_dispc.c
@@ -619,9 +619,8 @@ void tidss_disable_oldi(struct tidss_device *tidss, u32 hw_videoport)
                dispc_vid_write(_dispc, _hw_plane, _idx, _reg);         \
        })
 
-#define VP_REG_GET(dispc, vp, idx, start, end)                         \
-       ((u32)FIELD_GET(GENMASK((start), (end)),                        \
-                       dispc_vp_read((dispc), (vp), (idx))))
+#define VP_REG_GET(dispc, vp, idx, mask)                               \
+       ((u32)FIELD_GET((mask), dispc_vp_read((dispc), (vp), (idx))))
 
 #define VP_REG_FLD_MOD(dispc, vp, idx, val, start, end)                        \
        ({                                                              \
@@ -1260,12 +1259,13 @@ void dispc_vp_unprepare(struct dispc_device *dispc, u32 hw_videoport)
 
 bool dispc_vp_go_busy(struct dispc_device *dispc, u32 hw_videoport)
 {
-       return VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, 5, 5);
+       return VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL,
+                         GENMASK(5, 5));
 }
 
 void dispc_vp_go(struct dispc_device *dispc, u32 hw_videoport)
 {
-       WARN_ON(VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, 5, 5));
+       WARN_ON(VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, GENMASK(5, 5)));
        VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 5, 5);
 }