drm/amd/display: Add get_default_tiling_info for dcn42

Add DCN42 portion that was stripped during previously.

Fixes: 8333f22e44a9 ("drm/amd/display: Query DC for gfx handling when setting linear tiling")
Reviewed-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Signed-off-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
index aef187bcf5c343ab1c967bfdb2ceda6d6e063ee7..7b451c7db02c6266f1cade071bc3c61af1aa896a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
@@ -1792,6 +1792,7 @@ static struct resource_funcs dcn42_res_pool_funcs = {
        .build_pipe_pix_clk_params = dcn42_build_pipe_pix_clk_params,
        .get_vstartup_for_pipe = dcn401_get_vstartup_for_pipe,
        .get_max_hw_cursor_size = dcn42_get_max_hw_cursor_size,
+       .get_default_tiling_info = dcn10_get_default_tiling_info
 };
 
 static uint32_t read_pipe_fuses(struct dc_context *ctx)