drop asoc patch

diff --git a/queue-5.10/asoc-fsl_sai-don-t-disable-bitclock-for-i.mx8mp.patch b/queue-5.10/asoc-fsl_sai-don-t-disable-bitclock-for-i.mx8mp.patch
deleted file mode 100644 (file)
index 5d67965..0000000
--- a/queue-5.10/asoc-fsl_sai-don-t-disable-bitclock-for-i.mx8mp.patch
+++ /dev/null
@@ -1,53 +0,0 @@
-From 197c53c8ecb34f2cd5922f4bdcffa8f701a134eb Mon Sep 17 00:00:00 2001
-From: Shengjiu Wang <shengjiu.wang@nxp.com>
-Date: Tue, 19 Sep 2023 17:42:13 +0800
-Subject: ASoC: fsl_sai: Don't disable bitclock for i.MX8MP
-
-From: Shengjiu Wang <shengjiu.wang@nxp.com>
-
-commit 197c53c8ecb34f2cd5922f4bdcffa8f701a134eb upstream.
-
-On i.MX8MP, the BCE and TERE bit are binding with mclk
-enablement, if BCE and TERE are cleared the MCLK also be
-disabled on output pin, that cause the external codec (wm8960)
-in wrong state.
-
-Codec (wm8960) is using the mclk to generate PLL clock,
-if mclk is disabled before disabling PLL, the codec (wm8960)
-won't generate bclk and frameclk when sysclk switch to
-MCLK source in next test case.
-
-The test case:
-$aplay -r44100 test1.wav (PLL source)
-$aplay -r48000 test2.wav (MCLK source)
-aplay: pcm_write:2127: write error: Input/output error
-
-Fixes: 269f399dc19f ("ASoC: fsl_sai: Disable bit clock with transmitter")
-Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
-Link: https://lore.kernel.org/r/1695116533-23287-1-git-send-email-shengjiu.wang@nxp.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- sound/soc/fsl/fsl_sai.c |    9 +++++++--
- 1 file changed, 7 insertions(+), 2 deletions(-)
-
---- a/sound/soc/fsl/fsl_sai.c
-+++ b/sound/soc/fsl/fsl_sai.c
-@@ -549,10 +549,15 @@ static void fsl_sai_config_disable(struc
- {
-       unsigned int ofs = sai->soc_data->reg_offset;
-       bool tx = dir == TX;
--      u32 xcsr, count = 100;
-+      u32 xcsr, count = 100, mask;
-+
-+      if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output)
-+              mask = FSL_SAI_CSR_TERE;
-+      else
-+              mask = FSL_SAI_CSR_TERE | FSL_SAI_CSR_BCE;
- 
-       regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
--                         FSL_SAI_CSR_TERE | FSL_SAI_CSR_BCE, 0);
-+                         mask, 0);
- 
-       /* TERE will remain set till the end of current frame */
-       do {

diff --git a/queue-5.10/series b/queue-5.10/series
index ed20dc12ff9ee53190885c21359609fbaad50d8a..8a2b93e9b4831ac59041f0e87719d669bb2d8bae 100644 (file)
--- a/queue-5.10/series
+++ b/queue-5.10/series
@@ -7,4 +7,3 @@ lib-test_meminit-fix-off-by-one-error-in-test_pages.patch
 hid-logitech-hidpp-fix-kernel-crash-on-receiver-usb-disconnect.patch
 quota-fix-slow-quotaoff.patch
 net-prevent-address-rewrite-in-kernel_bind.patch
-asoc-fsl_sai-don-t-disable-bitclock-for-i.mx8mp.patch

diff --git a/queue-5.15/asoc-fsl_sai-don-t-disable-bitclock-for-i.mx8mp.patch b/queue-5.15/asoc-fsl_sai-don-t-disable-bitclock-for-i.mx8mp.patch
deleted file mode 100644 (file)
index 7dd285c..0000000
--- a/queue-5.15/asoc-fsl_sai-don-t-disable-bitclock-for-i.mx8mp.patch
+++ /dev/null
@@ -1,53 +0,0 @@
-From 197c53c8ecb34f2cd5922f4bdcffa8f701a134eb Mon Sep 17 00:00:00 2001
-From: Shengjiu Wang <shengjiu.wang@nxp.com>
-Date: Tue, 19 Sep 2023 17:42:13 +0800
-Subject: ASoC: fsl_sai: Don't disable bitclock for i.MX8MP
-
-From: Shengjiu Wang <shengjiu.wang@nxp.com>
-
-commit 197c53c8ecb34f2cd5922f4bdcffa8f701a134eb upstream.
-
-On i.MX8MP, the BCE and TERE bit are binding with mclk
-enablement, if BCE and TERE are cleared the MCLK also be
-disabled on output pin, that cause the external codec (wm8960)
-in wrong state.
-
-Codec (wm8960) is using the mclk to generate PLL clock,
-if mclk is disabled before disabling PLL, the codec (wm8960)
-won't generate bclk and frameclk when sysclk switch to
-MCLK source in next test case.
-
-The test case:
-$aplay -r44100 test1.wav (PLL source)
-$aplay -r48000 test2.wav (MCLK source)
-aplay: pcm_write:2127: write error: Input/output error
-
-Fixes: 269f399dc19f ("ASoC: fsl_sai: Disable bit clock with transmitter")
-Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
-Link: https://lore.kernel.org/r/1695116533-23287-1-git-send-email-shengjiu.wang@nxp.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- sound/soc/fsl/fsl_sai.c |    9 +++++++--
- 1 file changed, 7 insertions(+), 2 deletions(-)
-
---- a/sound/soc/fsl/fsl_sai.c
-+++ b/sound/soc/fsl/fsl_sai.c
-@@ -557,10 +557,15 @@ static void fsl_sai_config_disable(struc
- {
-       unsigned int ofs = sai->soc_data->reg_offset;
-       bool tx = dir == TX;
--      u32 xcsr, count = 100;
-+      u32 xcsr, count = 100, mask;
-+
-+      if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output)
-+              mask = FSL_SAI_CSR_TERE;
-+      else
-+              mask = FSL_SAI_CSR_TERE | FSL_SAI_CSR_BCE;
- 
-       regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
--                         FSL_SAI_CSR_TERE | FSL_SAI_CSR_BCE, 0);
-+                         mask, 0);
- 
-       /* TERE will remain set till the end of current frame */
-       do {

diff --git a/queue-5.15/series b/queue-5.15/series
index ecf92ba308f2fdeb07001ad8385adebc7951fd32..692d398011b2367d1128b9d487ace1352ead0a46 100644 (file)
--- a/queue-5.15/series
+++ b/queue-5.15/series
@@ -13,4 +13,3 @@ hid-logitech-hidpp-fix-kernel-crash-on-receiver-usb-disconnect.patch
 quota-fix-slow-quotaoff.patch
 net-prevent-address-rewrite-in-kernel_bind.patch
 alsa-usb-audio-fix-microphone-sound-on-opencomm2-headset.patch
-asoc-fsl_sai-don-t-disable-bitclock-for-i.mx8mp.patch

diff --git a/queue-5.4/asoc-fsl_sai-don-t-disable-bitclock-for-i.mx8mp.patch b/queue-5.4/asoc-fsl_sai-don-t-disable-bitclock-for-i.mx8mp.patch
deleted file mode 100644 (file)
index 3466b4d..0000000
--- a/queue-5.4/asoc-fsl_sai-don-t-disable-bitclock-for-i.mx8mp.patch
+++ /dev/null
@@ -1,53 +0,0 @@
-From 197c53c8ecb34f2cd5922f4bdcffa8f701a134eb Mon Sep 17 00:00:00 2001
-From: Shengjiu Wang <shengjiu.wang@nxp.com>
-Date: Tue, 19 Sep 2023 17:42:13 +0800
-Subject: ASoC: fsl_sai: Don't disable bitclock for i.MX8MP
-
-From: Shengjiu Wang <shengjiu.wang@nxp.com>
-
-commit 197c53c8ecb34f2cd5922f4bdcffa8f701a134eb upstream.
-
-On i.MX8MP, the BCE and TERE bit are binding with mclk
-enablement, if BCE and TERE are cleared the MCLK also be
-disabled on output pin, that cause the external codec (wm8960)
-in wrong state.
-
-Codec (wm8960) is using the mclk to generate PLL clock,
-if mclk is disabled before disabling PLL, the codec (wm8960)
-won't generate bclk and frameclk when sysclk switch to
-MCLK source in next test case.
-
-The test case:
-$aplay -r44100 test1.wav (PLL source)
-$aplay -r48000 test2.wav (MCLK source)
-aplay: pcm_write:2127: write error: Input/output error
-
-Fixes: 269f399dc19f ("ASoC: fsl_sai: Disable bit clock with transmitter")
-Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
-Link: https://lore.kernel.org/r/1695116533-23287-1-git-send-email-shengjiu.wang@nxp.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- sound/soc/fsl/fsl_sai.c |    9 +++++++--
- 1 file changed, 7 insertions(+), 2 deletions(-)
-
---- a/sound/soc/fsl/fsl_sai.c
-+++ b/sound/soc/fsl/fsl_sai.c
-@@ -545,10 +545,15 @@ static void fsl_sai_config_disable(struc
- {
-       unsigned int ofs = sai->soc_data->reg_offset;
-       bool tx = dir == TX;
--      u32 xcsr, count = 100;
-+      u32 xcsr, count = 100, mask;
-+
-+      if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output)
-+              mask = FSL_SAI_CSR_TERE;
-+      else
-+              mask = FSL_SAI_CSR_TERE | FSL_SAI_CSR_BCE;
- 
-       regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
--                         FSL_SAI_CSR_TERE | FSL_SAI_CSR_BCE, 0);
-+                         mask, 0);
- 
-       /* TERE will remain set till the end of current frame */
-       do {

diff --git a/queue-5.4/series b/queue-5.4/series
index f0f981fd3de22c0adc11d599242ab354024e0c7f..19ebec718dd4f343d45fed92189f37c6c10d49f3 100644 (file)
--- a/queue-5.4/series
+++ b/queue-5.4/series
@@ -6,4 +6,3 @@ hid-logitech-hidpp-fix-kernel-crash-on-receiver-usb-disconnect.patch
 quota-fix-slow-quotaoff.patch
 net-prevent-address-rewrite-in-kernel_bind.patch
 drm-etvnaviv-fix-bad-backport-leading-to-warning.patch
-asoc-fsl_sai-don-t-disable-bitclock-for-i.mx8mp.patch

diff --git a/queue-6.1/asoc-fsl_sai-don-t-disable-bitclock-for-i.mx8mp.patch b/queue-6.1/asoc-fsl_sai-don-t-disable-bitclock-for-i.mx8mp.patch
deleted file mode 100644 (file)
index 748d0dc..0000000
--- a/queue-6.1/asoc-fsl_sai-don-t-disable-bitclock-for-i.mx8mp.patch
+++ /dev/null
@@ -1,53 +0,0 @@
-From 197c53c8ecb34f2cd5922f4bdcffa8f701a134eb Mon Sep 17 00:00:00 2001
-From: Shengjiu Wang <shengjiu.wang@nxp.com>
-Date: Tue, 19 Sep 2023 17:42:13 +0800
-Subject: ASoC: fsl_sai: Don't disable bitclock for i.MX8MP
-
-From: Shengjiu Wang <shengjiu.wang@nxp.com>
-
-commit 197c53c8ecb34f2cd5922f4bdcffa8f701a134eb upstream.
-
-On i.MX8MP, the BCE and TERE bit are binding with mclk
-enablement, if BCE and TERE are cleared the MCLK also be
-disabled on output pin, that cause the external codec (wm8960)
-in wrong state.
-
-Codec (wm8960) is using the mclk to generate PLL clock,
-if mclk is disabled before disabling PLL, the codec (wm8960)
-won't generate bclk and frameclk when sysclk switch to
-MCLK source in next test case.
-
-The test case:
-$aplay -r44100 test1.wav (PLL source)
-$aplay -r48000 test2.wav (MCLK source)
-aplay: pcm_write:2127: write error: Input/output error
-
-Fixes: 269f399dc19f ("ASoC: fsl_sai: Disable bit clock with transmitter")
-Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
-Link: https://lore.kernel.org/r/1695116533-23287-1-git-send-email-shengjiu.wang@nxp.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- sound/soc/fsl/fsl_sai.c |    9 +++++++--
- 1 file changed, 7 insertions(+), 2 deletions(-)
-
---- a/sound/soc/fsl/fsl_sai.c
-+++ b/sound/soc/fsl/fsl_sai.c
-@@ -710,10 +710,15 @@ static void fsl_sai_config_disable(struc
- {
-       unsigned int ofs = sai->soc_data->reg_offset;
-       bool tx = dir == TX;
--      u32 xcsr, count = 100;
-+      u32 xcsr, count = 100, mask;
-+
-+      if (sai->soc_data->mclk_with_tere && sai->mclk_direction_output)
-+              mask = FSL_SAI_CSR_TERE;
-+      else
-+              mask = FSL_SAI_CSR_TERE | FSL_SAI_CSR_BCE;
- 
-       regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
--                         FSL_SAI_CSR_TERE | FSL_SAI_CSR_BCE, 0);
-+                         mask, 0);
- 
-       /* TERE will remain set till the end of current frame */
-       do {

diff --git a/queue-6.1/series b/queue-6.1/series
index 975ace0f629a0d94bc2a759ea950be1b42ad48ae..c5362001f2f1d310af4e9a73939930e3e47ffc05 100644 (file)
--- a/queue-6.1/series
+++ b/queue-6.1/series
@@ -26,6 +26,5 @@ alsa-hda-realtek-change-model-for-intel-rvp-board.patch
 asoc-sof-amd-fix-for-firmware-reload-failure-after-playback.patch
 asoc-simple-card-utils-fixup-simple_util_startup-error-handling.patch
 asoc-intel-soc-acpi-add-entry-for-hdmi_in-capture-support-in-mtl-match-table.patch
-asoc-fsl_sai-don-t-disable-bitclock-for-i.mx8mp.patch
 asoc-intel-sof_sdw-add-support-for-sku-0b14.patch
 asoc-intel-soc-acpi-add-entry-for-sof_es8336-in-mtl-match-table.patch