6.1-stable patches

added patches:
	tools-headers-arm64-sync-arm64-s-cputype.h-with-the-kernel-sources.patch

diff --git a/queue-6.1/series b/queue-6.1/series
index 74828eb890317e44346bf94b0a2ed25e30a3cb59..e335a9f3416f178b9d575637a4e1dc0d8356a744 100644 (file)
--- a/queue-6.1/series
+++ b/queue-6.1/series
@@ -137,3 +137,4 @@ revert-drm-amd-display-add-null-check-for-afb-before-dereferencing-in-amdgpu_dm_
 mm-huge_memory-use-config_64bit-to-relax-huge-page-alignment-on-32-bit-machines.patch
 btrfs-fix-corruption-after-buffer-fault-in-during-direct-io-append-write.patch
 ipv6-fix-source-address-selection-with-route-leak.patch
+tools-headers-arm64-sync-arm64-s-cputype.h-with-the-kernel-sources.patch

diff --git a/queue-6.1/tools-headers-arm64-sync-arm64-s-cputype.h-with-the-kernel-sources.patch b/queue-6.1/tools-headers-arm64-sync-arm64-s-cputype.h-with-the-kernel-sources.patch
new file mode 100644 (file)
index 0000000..78ce331
--- /dev/null
+++ b/queue-6.1/tools-headers-arm64-sync-arm64-s-cputype.h-with-the-kernel-sources.patch
@@ -0,0 +1,79 @@
+From dc6abbbde4b099e936cd5428e196d86a5e119aae Mon Sep 17 00:00:00 2001
+From: Arnaldo Carvalho de Melo <acme@redhat.com>
+Date: Mon, 3 Jun 2024 15:25:23 -0300
+Subject: tools headers arm64: Sync arm64's cputype.h with the kernel sources
+
+From: Arnaldo Carvalho de Melo <acme@redhat.com>
+
+commit dc6abbbde4b099e936cd5428e196d86a5e119aae upstream.
+
+To get the changes in:
+
+  0ce85db6c2141b7f ("arm64: cputype: Add Neoverse-V3 definitions")
+  02a0a04676fa7796 ("arm64: cputype: Add Cortex-X4 definitions")
+  f4d9d9dcc70b96b5 ("arm64: Add Neoverse-V2 part")
+
+That makes this perf source code to be rebuilt:
+
+  CC      /tmp/build/perf-tools/util/arm-spe.o
+
+The changes in the above patch add MIDR_NEOVERSE_V[23] and
+MIDR_NEOVERSE_V1 is used in arm-spe.c, so probably we need to add those
+and perhaps MIDR_CORTEX_X4 to that array? Or maybe we need to leave this
+for later when this is all tested on those machines?
+
+  static const struct midr_range neoverse_spe[] = {
+          MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1),
+          MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
+          MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1),
+          {},
+  };
+
+Mark Rutland recommended about arm-spe.c:
+
+"I would not touch this for now -- someone would have to go audit the
+TRMs to check that those other cores have the same encoding, and I think
+it'd be better to do that as a follow-up."
+
+That addresses this perf build warning:
+
+  Warning: Kernel ABI header differences:
+    diff -u tools/arch/arm64/include/asm/cputype.h arch/arm64/include/asm/cputype.h
+
+Acked-by: Mark Rutland <mark.rutland@arm.com>
+Cc: Adrian Hunter <adrian.hunter@intel.com>
+Cc: Besar Wicaksono <bwicaksono@nvidia.com>
+Cc: Ian Rogers <irogers@google.com>
+Cc: Jiri Olsa <jolsa@kernel.org>
+Cc: Kan Liang <kan.liang@linux.intel.com>
+Cc: Namhyung Kim <namhyung@kernel.org>
+Cc: Will Deacon <will@kernel.org>
+Link: https://lore.kernel.org/lkml/Zl8cYk0Tai2fs7aM@x1
+Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ tools/arch/arm64/include/asm/cputype.h |    6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/tools/arch/arm64/include/asm/cputype.h
++++ b/tools/arch/arm64/include/asm/cputype.h
+@@ -83,6 +83,9 @@
+ #define ARM_CPU_PART_CORTEX_X2                0xD48
+ #define ARM_CPU_PART_NEOVERSE_N2      0xD49
+ #define ARM_CPU_PART_CORTEX_A78C      0xD4B
++#define ARM_CPU_PART_NEOVERSE_V2      0xD4F
++#define ARM_CPU_PART_CORTEX_X4                0xD82
++#define ARM_CPU_PART_NEOVERSE_V3      0xD84
+ 
+ #define APM_CPU_PART_POTENZA          0x000
+ 
+@@ -145,6 +148,9 @@
+ #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)
+ #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)
+ #define MIDR_CORTEX_A78C      MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C)
++#define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2)
++#define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4)
++#define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)
+ #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
+ #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
+ #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)