Drop iommu-vt-d-omit-devtlb-invalidation-requests-when-te.patch-10784

Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/queue-6.1/iommu-vt-d-omit-devtlb-invalidation-requests-when-te.patch-10784 b/queue-6.1/iommu-vt-d-omit-devtlb-invalidation-requests-when-te.patch-10784
deleted file mode 100644 (file)
index c54b76d..0000000
--- a/queue-6.1/iommu-vt-d-omit-devtlb-invalidation-requests-when-te.patch-10784
+++ /dev/null
@@ -1,69 +0,0 @@
-From a345a9eb682af6391e25e0a9bb9dd0b1e9440a89 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Wed, 22 Nov 2023 11:26:03 +0800
-Subject: iommu/vt-d: Omit devTLB invalidation requests when TES=0
-
-From: Lu Baolu <baolu.lu@linux.intel.com>
-
-[ Upstream commit 0f5432a9b839847dcfe9fa369d72e3d646102ddf ]
-
-The latest VT-d spec indicates that when remapping hardware is disabled
-(TES=0 in Global Status Register), upstream ATS Invalidation Completion
-requests are treated as UR (Unsupported Request).
-
-Consequently, the spec recommends in section 4.3 Handling of Device-TLB
-Invalidations that software refrain from submitting any Device-TLB
-invalidation requests when address remapping hardware is disabled.
-
-Verify address remapping hardware is enabled prior to submitting Device-
-TLB invalidation requests.
-
-Fixes: 792fb43ce2c9 ("iommu/vt-d: Enable Intel IOMMU scalable mode by default")
-Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
-Reviewed-by: Kevin Tian <kevin.tian@intel.com>
-Link: https://lore.kernel.org/r/20231114011036.70142-2-baolu.lu@linux.intel.com
-Signed-off-by: Joerg Roedel <jroedel@suse.de>
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/iommu/intel/dmar.c | 18 ++++++++++++++++++
- 1 file changed, 18 insertions(+)
-
-diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c
-index f800989ea0462..418af1db0192d 100644
---- a/drivers/iommu/intel/dmar.c
-+++ b/drivers/iommu/intel/dmar.c
-@@ -1495,6 +1495,15 @@ void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid,
- {
-       struct qi_desc desc;
- 
-+      /*
-+       * VT-d spec, section 4.3:
-+       *
-+       * Software is recommended to not submit any Device-TLB invalidation
-+       * requests while address remapping hardware is disabled.
-+       */
-+      if (!(iommu->gcmd & DMA_GCMD_TE))
-+              return;
-+
-       if (mask) {
-               addr |= (1ULL << (VTD_PAGE_SHIFT + mask - 1)) - 1;
-               desc.qw1 = QI_DEV_IOTLB_ADDR(addr) | QI_DEV_IOTLB_SIZE;
-@@ -1560,6 +1569,15 @@ void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid,
-       unsigned long mask = 1UL << (VTD_PAGE_SHIFT + size_order - 1);
-       struct qi_desc desc = {.qw1 = 0, .qw2 = 0, .qw3 = 0};
- 
-+      /*
-+       * VT-d spec, section 4.3:
-+       *
-+       * Software is recommended to not submit any Device-TLB invalidation
-+       * requests while address remapping hardware is disabled.
-+       */
-+      if (!(iommu->gcmd & DMA_GCMD_TE))
-+              return;
-+
-       desc.qw0 = QI_DEV_EIOTLB_PASID(pasid) | QI_DEV_EIOTLB_SID(sid) |
-               QI_DEV_EIOTLB_QDEP(qdep) | QI_DEIOTLB_TYPE |
-               QI_DEV_IOTLB_PFSID(pfsid);
--- 
-2.42.0
-

diff --git a/queue-6.1/series b/queue-6.1/series
index 3e99f95bbe7e452886d93efe46f3c74748b72cdd..faafa6d7297a78c6049048cbf6d85d4b827e0cf5 100644 (file)
--- a/queue-6.1/series
+++ b/queue-6.1/series
@@ -92,7 +92,6 @@ iommu-vt-d-add-device_block_translation-helper.patch
 iommu-vt-d-disable-pci-ats-in-legacy-passthrough-mod.patch
 iommu-vt-d-make-context-clearing-consistent-with-con.patch
 drm-amd-pm-fix-a-memleak-in-aldebaran_tables_init.patch
-iommu-vt-d-omit-devtlb-invalidation-requests-when-te.patch-10784
 iommu-vt-d-allocate-pasid-table-in-device-probe-path.patch-8635
 iommu-vt-d-add-device_block_translation-helper.patch-1231
 iommu-vt-d-disable-pci-ats-in-legacy-passthrough-mod.patch-15652