arm64: dts: qcom: sm6150: add venus node to devicetree

Add the venus node to the devicetree for the sm6150 platform to enable
video functionality. The sm6150 platform currently lacks video
functionality due to the absence of the venus node. Fallback to sc7180 due
to the same video core.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Renjiang Han <quic_renjiang@quicinc.com>
Link: https://lore.kernel.org/r/20250826-enable-venus-for-sm6150-v9-1-486d167639a1@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm6150.dtsi b/arch/arm64/boot/dts/qcom/sm6150.dtsi
index 53496241479a05fec7bffa893b96b2d12b2d7614..8757e05015915c17062f2066f5812100b57c1cbb 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm6150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6150.dtsi
@@ -494,6 +494,11 @@
                        hwlocks = <&tcsr_mutex 3>;
                };
 
+               pil_video_mem: pil-video@93400000 {
+                       reg = <0x0 0x93400000 0x0 0x500000>;
+                       no-map;
+               };
+
                rproc_cdsp_mem: rproc-cdsp@93b00000 {
                        reg = <0x0 0x93b00000 0x0 0x1e00000>;
                        no-map;
@@ -3556,6 +3561,79 @@
                        qcom,bcm-voters = <&apps_bcm_voter>;
                };
 
+               venus: video-codec@aa00000 {
+                       compatible = "qcom,qcs615-venus", "qcom,sc7180-venus";
+                       reg = <0x0 0x0aa00000 0x0 0x100000>;
+                       interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+
+                       clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
+                                <&videocc VIDEO_CC_VENUS_AHB_CLK>,
+                                <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
+                                <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
+                                <&videocc VIDEO_CC_VCODEC0_AXI_CLK>;
+                       clock-names = "core",
+                                     "iface",
+                                     "bus",
+                                     "vcodec0_core",
+                                     "vcodec0_bus";
+
+                       power-domains = <&videocc VENUS_GDSC>,
+                                       <&videocc VCODEC0_GDSC>,
+                                       <&rpmhpd RPMHPD_CX>;
+                       power-domain-names = "venus",
+                                            "vcodec0",
+                                            "cx";
+
+                       operating-points-v2 = <&venus_opp_table>;
+
+                       interconnects = <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS
+                                        &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+                                       <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+                                        &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+                       interconnect-names = "video-mem",
+                                            "cpu-cfg";
+
+                       iommus = <&apps_smmu 0xe60 0x20>;
+
+                       memory-region = <&pil_video_mem>;
+
+                       status = "disabled";
+
+                       venus_opp_table: opp-table {
+                               compatible = "operating-points-v2";
+
+                               opp-133330000 {
+                                       opp-hz = /bits/ 64 <133330000>;
+                                       required-opps = <&rpmhpd_opp_low_svs>;
+                               };
+
+                               opp-240000000 {
+                                       opp-hz = /bits/ 64 <240000000>;
+                                       required-opps = <&rpmhpd_opp_svs>;
+                               };
+
+                               opp-300000000 {
+                                       opp-hz = /bits/ 64 <300000000>;
+                                       required-opps = <&rpmhpd_opp_svs_l1>;
+                               };
+
+                               opp-380000000 {
+                                       opp-hz = /bits/ 64 <380000000>;
+                                       required-opps = <&rpmhpd_opp_nom>;
+                               };
+
+                               opp-410000000 {
+                                       opp-hz = /bits/ 64 <410000000>;
+                                       required-opps = <&rpmhpd_opp_nom_l1>;
+                               };
+
+                               opp-460000000 {
+                                       opp-hz = /bits/ 64 <460000000>;
+                                       required-opps = <&rpmhpd_opp_turbo>;
+                               };
+                       };
+               };
+
                videocc: clock-controller@ab00000 {
                        compatible = "qcom,qcs615-videocc";
                        reg = <0 0x0ab00000 0 0x10000>;