#define ZYNQMP_SATA_BASEADDR 0xFD0C0000
-#define ZYNQMP_USB0_XHCI_BASEADDR 0xFE200000
-#define ZYNQMP_USB1_XHCI_BASEADDR 0xFE300000
-
#define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000
#define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000
#define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT 0
config USB_XHCI_ZYNQMP
bool "Support for Xilinx ZynqMP on-chip xHCI USB controller"
- depends on ARCH_ZYNQMP
+ depends on ARCH_ZYNQMP && DM_USB
help
Enables support for the on-chip xHCI controller on Xilinx ZynqMP SoCs.
#define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN BIT(17)
struct zynqmp_xhci {
-#ifdef CONFIG_DM_USB
struct usb_platdata usb_plat;
-#endif
struct xhci_ctrl ctrl;
struct xhci_hccr *hcd;
struct dwc3 *dwc3_reg;
};
-#ifdef CONFIG_DM_USB
struct zynqmp_xhci_platdata {
fdt_addr_t hcd_base;
};
-#else
-static struct zynqmp_xhci zynqmp_xhci;
-
-unsigned long ctr_addr[] = CONFIG_ZYNQMP_XHCI_LIST;
-#endif
static int zynqmp_xhci_core_init(struct zynqmp_xhci *zynqmp_xhci)
{
return ret;
}
-#ifndef CONFIG_DM_USB
-int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
-{
- struct zynqmp_xhci *ctx = &zynqmp_xhci;
- int ret = 0;
- uint32_t hclen;
-
- if (index < 0 || index >= ARRAY_SIZE(ctr_addr))
- return -EINVAL;
-
- ctx->hcd = (struct xhci_hccr *)ctr_addr[index];
- ctx->dwc3_reg = (struct dwc3 *)((void *)ctx->hcd + DWC3_REG_OFFSET);
-
- ret = board_usb_init(index, USB_INIT_HOST);
- if (ret != 0) {
- puts("Failed to initialize board for USB\n");
- return ret;
- }
-
- ret = zynqmp_xhci_core_init(ctx);
- if (ret < 0) {
- puts("Failed to initialize xhci\n");
- return ret;
- }
-
- *hccr = (struct xhci_hccr *)ctx->hcd;
- hclen = HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase));
- *hcor = (struct xhci_hcor *)((uintptr_t) *hccr + hclen);
-
- debug("zynqmp-xhci: init hccr %p and hcor %p hc_length %d\n",
- *hccr, *hcor, hclen);
-
- return ret;
-}
-#endif
-
void xhci_hcd_stop(int index)
{
/*
return;
}
-#ifdef CONFIG_DM_USB
static int xhci_usb_probe(struct udevice *dev)
{
struct zynqmp_xhci_platdata *plat = dev_get_platdata(dev);
.priv_auto_alloc_size = sizeof(struct zynqmp_xhci),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
-#endif
#define CONFIG_ZYNQ_SDHCI_MIN_FREQ (CONFIG_ZYNQ_SDHCI_MAX_FREQ >> 9)
#define CONFIG_ZYNQ_EEPROM
#define CONFIG_SATA_CEVA
-#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \
- ZYNQMP_USB1_XHCI_BASEADDR}
#define COUNTER_FREQUENCY 4000000
#define CONFIG_ZYNQ_SDHCI0
#define CONFIG_ZYNQ_SDHCI1
#define CONFIG_AHCI
-#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR}
#include <configs/xilinx_zynqmp.h>
#ifndef __CONFIG_ZYNQMP_ZC1751_XM016_DC2_H
#define __CONFIG_ZYNQMP_ZC1751_XM016_DC2_H
-#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB1_XHCI_BASEADDR}
-
#include <configs/xilinx_zynqmp.h>
#endif /* __CONFIG_ZYNQMP_ZC1751_XM016_DC2_H */
#define CONFIG_ZYNQ_I2C0
#define CONFIG_ZYNQ_I2C1
-#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, ZYNQMP_USB1_XHCI_BASEADDR}
-
#define CONFIG_AHCI
#define CONFIG_SATA_CEVA
/* #define CONFIG_ZYNQ_I2C1 */ /* FIXME for 96 compatible bitstream */
#define CONFIG_SYS_I2C_ZYNQ
-#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \
- ZYNQMP_USB1_XHCI_BASEADDR}
-
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
#define CONFIG_SATA_CEVA
-#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR}
-
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_CMD_EEPROM
#define CONFIG_ZYNQ_EEPROM_BUS 5
#define CONFIG_SATA_CEVA
-#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR}
-
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_CMD_EEPROM
#define CONFIG_ZYNQ_EEPROM_BUS 5