--- /dev/null
+From 9451c79bc39e610882bdd12370f01af5004a3c4f Mon Sep 17 00:00:00 2001
+From: Ilie Halip <ilie.halip@gmail.com>
+Date: Fri, 20 Sep 2019 18:39:51 +0300
+Subject: powerpc/pmac/smp: Avoid unused-variable warnings
+
+From: Ilie Halip <ilie.halip@gmail.com>
+
+commit 9451c79bc39e610882bdd12370f01af5004a3c4f upstream.
+
+When building with ppc64_defconfig, the compiler reports
+that these 2 variables are not used:
+ warning: unused variable 'core99_l2_cache' [-Wunused-variable]
+ warning: unused variable 'core99_l3_cache' [-Wunused-variable]
+
+They are only used when CONFIG_PPC64 is not defined. Move
+them into a section which does the same macro check.
+
+Reported-by: Nathan Chancellor <natechancellor@gmail.com>
+Signed-off-by: Ilie Halip <ilie.halip@gmail.com>
+[mpe: Move them into core99_init_caches() which is their only user]
+Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
+Link: https://lore.kernel.org/r/20190920153951.25762-1-ilie.halip@gmail.com
+Cc: Nathan Chancellor <nathan@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/powerpc/platforms/powermac/smp.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+--- a/arch/powerpc/platforms/powermac/smp.c
++++ b/arch/powerpc/platforms/powermac/smp.c
+@@ -660,13 +660,13 @@ static void smp_core99_gpio_tb_freeze(in
+
+ #endif /* !CONFIG_PPC64 */
+
+-/* L2 and L3 cache settings to pass from CPU0 to CPU1 on G4 cpus */
+-volatile static long int core99_l2_cache;
+-volatile static long int core99_l3_cache;
+-
+ static void core99_init_caches(int cpu)
+ {
+ #ifndef CONFIG_PPC64
++ /* L2 and L3 cache settings to pass from CPU0 to CPU1 on G4 cpus */
++ volatile static long int core99_l2_cache;
++ volatile static long int core99_l3_cache;
++
+ if (!cpu_has_feature(CPU_FTR_L2CR))
+ return;
+
--- /dev/null
+From a4037d1f1fc4e92b69d7196d4568c33078d465ea Mon Sep 17 00:00:00 2001
+From: YueHaibing <yuehaibing@huawei.com>
+Date: Tue, 3 Mar 2020 16:56:04 +0800
+Subject: powerpc/pmac/smp: Drop unnecessary volatile qualifier
+
+From: YueHaibing <yuehaibing@huawei.com>
+
+commit a4037d1f1fc4e92b69d7196d4568c33078d465ea upstream.
+
+core99_l2_cache/core99_l3_cache do not need to be marked as volatile,
+remove it.
+
+Signed-off-by: YueHaibing <yuehaibing@huawei.com>
+Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
+Link: https://lore.kernel.org/r/20200303085604.24952-1-yuehaibing@huawei.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/powerpc/platforms/powermac/smp.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/powerpc/platforms/powermac/smp.c
++++ b/arch/powerpc/platforms/powermac/smp.c
+@@ -664,8 +664,8 @@ static void core99_init_caches(int cpu)
+ {
+ #ifndef CONFIG_PPC64
+ /* L2 and L3 cache settings to pass from CPU0 to CPU1 on G4 cpus */
+- volatile static long int core99_l2_cache;
+- volatile static long int core99_l3_cache;
++ static long int core99_l2_cache;
++ static long int core99_l3_cache;
+
+ if (!cpu_has_feature(CPU_FTR_L2CR))
+ return;