memory: tegra: Group error handling related registers

Group MC error related registers into a struct as they could have SoC
specific values. Tegra264 has different register offsets than the
existing devices and so in order to add support for Tegra264 we need to
first make this change.

Signed-off-by: Ketan Patil <ketanp@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Link: https://patch.msgid.link/20260226163115.1152181-2-ketanp@nvidia.com
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>

diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c
index 67a0b0c077128f68328b158dfe5dc8ba13c67a26..63f402aa1976e55a814d61dd41b05c33b1f304c9 100644 (file)
--- a/drivers/memory/tegra/mc.c
+++ b/drivers/memory/tegra/mc.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2014-2025 NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (C) 2014-2026 NVIDIA CORPORATION.  All rights reserved.
  */
 
 #include <linux/clk.h>
@@ -56,6 +56,23 @@ static const struct of_device_id tegra_mc_of_match[] = {
 };
 MODULE_DEVICE_TABLE(of, tegra_mc_of_match);
 
+const struct tegra_mc_regs tegra20_mc_regs = {
+       .cfg_channel_enable = 0xdf8,
+       .err_status = 0x08,
+       .err_add = 0x0c,
+       .err_add_hi = 0x11fc,
+       .err_vpr_status = 0x654,
+       .err_vpr_add = 0x658,
+       .err_sec_status = 0x67c,
+       .err_sec_add = 0x680,
+       .err_mts_status = 0x9b0,
+       .err_mts_add = 0x9b4,
+       .err_gen_co_status = 0xc00,
+       .err_gen_co_add = 0xc04,
+       .err_route_status = 0x9c0,
+       .err_route_add = 0x9c4,
+};
+
 static void tegra_mc_devm_action_put_device(void *data)
 {
        struct tegra_mc *mc = data;
@@ -591,37 +608,37 @@ irqreturn_t tegra30_mc_handle_irq(int irq, void *data)
 
                switch (intmask) {
                case MC_INT_DECERR_VPR:
-                       status_reg = MC_ERR_VPR_STATUS;
-                       addr_reg = MC_ERR_VPR_ADR;
+                       status_reg = mc->soc->regs->err_vpr_status;
+                       addr_reg = mc->soc->regs->err_vpr_add;
                        break;
 
                case MC_INT_SECERR_SEC:
-                       status_reg = MC_ERR_SEC_STATUS;
-                       addr_reg = MC_ERR_SEC_ADR;
+                       status_reg = mc->soc->regs->err_sec_status;
+                       addr_reg = mc->soc->regs->err_sec_add;
                        break;
 
                case MC_INT_DECERR_MTS:
-                       status_reg = MC_ERR_MTS_STATUS;
-                       addr_reg = MC_ERR_MTS_ADR;
+                       status_reg = mc->soc->regs->err_mts_status;
+                       addr_reg = mc->soc->regs->err_mts_add;
                        break;
 
                case MC_INT_DECERR_GENERALIZED_CARVEOUT:
-                       status_reg = MC_ERR_GENERALIZED_CARVEOUT_STATUS;
-                       addr_reg = MC_ERR_GENERALIZED_CARVEOUT_ADR;
+                       status_reg = mc->soc->regs->err_gen_co_status;
+                       addr_reg = mc->soc->regs->err_gen_co_add;
                        break;
 
                case MC_INT_DECERR_ROUTE_SANITY:
-                       status_reg = MC_ERR_ROUTE_SANITY_STATUS;
-                       addr_reg = MC_ERR_ROUTE_SANITY_ADR;
+                       status_reg = mc->soc->regs->err_route_status;
+                       addr_reg = mc->soc->regs->err_route_add;
                        break;
 
                default:
-                       status_reg = MC_ERR_STATUS;
-                       addr_reg = MC_ERR_ADR;
+                       status_reg = mc->soc->regs->err_status;
+                       addr_reg = mc->soc->regs->err_add;
 
 #ifdef CONFIG_PHYS_ADDR_T_64BIT
                        if (mc->soc->has_addr_hi_reg)
-                               addr_hi_reg = MC_ERR_ADR_HI;
+                               addr_hi_reg = mc->soc->regs->err_add_hi;
 #endif
                        break;
                }
@@ -874,7 +891,7 @@ static void tegra_mc_num_channel_enabled(struct tegra_mc *mc)
        unsigned int i;
        u32 value;
 
-       value = mc_ch_readl(mc, 0, MC_EMEM_ADR_CFG_CHANNEL_ENABLE);
+       value = mc_ch_readl(mc, 0, mc->soc->regs->cfg_channel_enable);
        if (value <= 0) {
                mc->num_channels = mc->soc->num_channels;
                return;

diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h
index 1d97cf4d3a944f015423240bfff5911f30cbe614..bbe3e2690c6479a388293e44b0af1266e7caff70 100644 (file)
--- a/drivers/memory/tegra/mc.h
+++ b/drivers/memory/tegra/mc.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (C) 2014-2025 NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (C) 2014-2026 NVIDIA CORPORATION.  All rights reserved.
  */
 
 #ifndef MEMORY_TEGRA_MC_H
@@ -14,8 +14,6 @@
 
 #define MC_INTSTATUS                                   0x00
 #define MC_INTMASK                                     0x04
-#define MC_ERR_STATUS                                  0x08
-#define MC_ERR_ADR                                     0x0c
 #define MC_GART_ERROR_REQ                              0x30
 #define MC_EMEM_ADR_CFG                                        0x54
 #define MC_DECERR_EMEM_OTHERS_STATUS                   0x58
@@ -43,19 +41,7 @@
 #define MC_EMEM_ARB_OVERRIDE                           0xe8
 #define MC_TIMING_CONTROL_DBG                          0xf8
 #define MC_TIMING_CONTROL                              0xfc
-#define MC_ERR_VPR_STATUS                              0x654
-#define MC_ERR_VPR_ADR                                 0x658
-#define MC_ERR_SEC_STATUS                              0x67c
-#define MC_ERR_SEC_ADR                                 0x680
-#define MC_ERR_MTS_STATUS                              0x9b0
-#define MC_ERR_MTS_ADR                                 0x9b4
-#define MC_ERR_ROUTE_SANITY_STATUS                     0x9c0
-#define MC_ERR_ROUTE_SANITY_ADR                                0x9c4
-#define MC_ERR_GENERALIZED_CARVEOUT_STATUS             0xc00
-#define MC_ERR_GENERALIZED_CARVEOUT_ADR                        0xc04
-#define MC_EMEM_ADR_CFG_CHANNEL_ENABLE                 0xdf8
 #define MC_GLOBAL_INTSTATUS                            0xf24
-#define MC_ERR_ADR_HI                                  0x11fc
 
 #define MC_INT_DECERR_ROUTE_SANITY                     BIT(20)
 #define MC_INT_DECERR_GENERALIZED_CARVEOUT             BIT(17)

diff --git a/drivers/memory/tegra/tegra114.c b/drivers/memory/tegra/tegra114.c
index 41350570c815cc752cc10161ab947d744730ac6e..ea7e4c7bb5f837b3da0b46c06be2cdb5633928d7 100644 (file)
--- a/drivers/memory/tegra/tegra114.c
+++ b/drivers/memory/tegra/tegra114.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2014 NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (C) 2014-2026 NVIDIA CORPORATION.  All rights reserved.
  */
 
 #include <linux/of.h>
@@ -1114,4 +1114,5 @@ const struct tegra_mc_soc tegra114_mc_soc = {
        .resets = tegra114_mc_resets,
        .num_resets = ARRAY_SIZE(tegra114_mc_resets),
        .ops = &tegra30_mc_ops,
+       .regs = &tegra20_mc_regs,
 };

diff --git a/drivers/memory/tegra/tegra124.c b/drivers/memory/tegra/tegra124.c
index 991d4f7bc070f41594abcbc03de304e475d3b209..f0cfe14bb47581617d2d5cbaa395bc6deb964fbb 100644 (file)
--- a/drivers/memory/tegra/tegra124.c
+++ b/drivers/memory/tegra/tegra124.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2014 NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (C) 2014-2026 NVIDIA CORPORATION.  All rights reserved.
  */
 
 #include <linux/of.h>
@@ -1275,6 +1275,7 @@ const struct tegra_mc_soc tegra124_mc_soc = {
        .num_resets = ARRAY_SIZE(tegra124_mc_resets),
        .icc_ops = &tegra124_mc_icc_ops,
        .ops = &tegra30_mc_ops,
+       .regs = &tegra20_mc_regs,
 };
 #endif /* CONFIG_ARCH_TEGRA_124_SOC */
 
@@ -1307,5 +1308,6 @@ const struct tegra_mc_soc tegra132_mc_soc = {
        .num_resets = ARRAY_SIZE(tegra124_mc_resets),
        .icc_ops = &tegra124_mc_icc_ops,
        .ops = &tegra30_mc_ops,
+       .regs = &tegra20_mc_regs,
 };
 #endif /* CONFIG_ARCH_TEGRA_132_SOC */

diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c
index aee11457bf8e032637d1772affb87da0cac68494..51e2dd628fb47eafafe6819135a0d711dcc47bef 100644 (file)
--- a/drivers/memory/tegra/tegra186.c
+++ b/drivers/memory/tegra/tegra186.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2017-2025 NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (C) 2017-2026 NVIDIA CORPORATION.  All rights reserved.
  */
 
 #include <linux/io.h>
@@ -914,5 +914,6 @@ const struct tegra_mc_soc tegra186_mc_soc = {
        .ops = &tegra186_mc_ops,
        .ch_intmask = 0x0000000f,
        .global_intstatus_channel_shift = 0,
+       .regs = &tegra20_mc_regs,
 };
 #endif

diff --git a/drivers/memory/tegra/tegra194.c b/drivers/memory/tegra/tegra194.c
index 26035ac3a1eb51a3d8ce3830427b4412b48baf3c..5b7ff2dd68122ad08ea7bac259d8f0bbf27cfbe8 100644 (file)
--- a/drivers/memory/tegra/tegra194.c
+++ b/drivers/memory/tegra/tegra194.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2017-2021 NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (C) 2017-2026 NVIDIA CORPORATION.  All rights reserved.
  */
 
 #include <soc/tegra/mc.h>
@@ -1358,4 +1358,5 @@ const struct tegra_mc_soc tegra194_mc_soc = {
        .icc_ops = &tegra_mc_icc_ops,
        .ch_intmask = 0x00000f00,
        .global_intstatus_channel_shift = 8,
+       .regs = &tegra20_mc_regs,
 };

diff --git a/drivers/memory/tegra/tegra20.c b/drivers/memory/tegra/tegra20.c
index 4748113bfe9d1bdb58eb78e108c31c6c27e82fff..1b2b598ab5645cbbae2d76795ae324d1f94d81f3 100644 (file)
--- a/drivers/memory/tegra/tegra20.c
+++ b/drivers/memory/tegra/tegra20.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2012 NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (C) 2012-2026 NVIDIA CORPORATION.  All rights reserved.
  */
 
 #include <linux/bitfield.h>
@@ -778,4 +778,5 @@ const struct tegra_mc_soc tegra20_mc_soc = {
        .num_resets = ARRAY_SIZE(tegra20_mc_resets),
        .icc_ops = &tegra20_mc_icc_ops,
        .ops = &tegra20_mc_ops,
+       .regs = &tegra20_mc_regs,
 };

diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c
index 3c2949c16fdef4911682da5e3cbfb91899e34c87..e166b33848e95563660e52e9ff418ebd1e40ed94 100644 (file)
--- a/drivers/memory/tegra/tegra210.c
+++ b/drivers/memory/tegra/tegra210.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2015 NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (C) 2015-2026 NVIDIA CORPORATION.  All rights reserved.
  */
 
 #include <dt-bindings/memory/tegra210-mc.h>
@@ -1287,4 +1287,5 @@ const struct tegra_mc_soc tegra210_mc_soc = {
        .resets = tegra210_mc_resets,
        .num_resets = ARRAY_SIZE(tegra210_mc_resets),
        .ops = &tegra30_mc_ops,
+       .regs = &tegra20_mc_regs,
 };

diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra234.c
index 5f57cea48b629740c50ce0f951df812c9c7dfde7..512d054d7592465135cf09dfdb927a0936f45ff3 100644 (file)
--- a/drivers/memory/tegra/tegra234.c
+++ b/drivers/memory/tegra/tegra234.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2022-2023, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (C) 2022-2026, NVIDIA CORPORATION.  All rights reserved.
  */
 
 #include <soc/tegra/mc.h>
@@ -1152,4 +1152,5 @@ const struct tegra_mc_soc tegra234_mc_soc = {
         * supported.
         */
        .num_carveouts = 32,
+       .regs = &tegra20_mc_regs,
 };

diff --git a/drivers/memory/tegra/tegra30.c b/drivers/memory/tegra/tegra30.c
index a6bcde4b92c03f23fc6f5c591016251f7950dcf3..337501a30a73f85d37bb8f358fb7fea73b353e70 100644 (file)
--- a/drivers/memory/tegra/tegra30.c
+++ b/drivers/memory/tegra/tegra30.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2014 NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (C) 2014-2026 NVIDIA CORPORATION.  All rights reserved.
  */
 
 #include <linux/device.h>
@@ -1400,4 +1400,5 @@ const struct tegra_mc_soc tegra30_mc_soc = {
        .num_resets = ARRAY_SIZE(tegra30_mc_resets),
        .icc_ops = &tegra30_mc_icc_ops,
        .ops = &tegra30_mc_ops,
+       .regs = &tegra20_mc_regs,
 };

diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h
index 6ee4c59db6201f9e2d415349f4385ce8d07226a3..372f47e824d5371764677aeede3ab2f431b05fd0 100644 (file)
--- a/include/soc/tegra/mc.h
+++ b/include/soc/tegra/mc.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (C) 2014 NVIDIA Corporation
+ * Copyright (C) 2014-2026 NVIDIA Corporation
  */
 
 #ifndef __SOC_TEGRA_MC_H__
@@ -168,6 +168,23 @@ struct tegra_mc_ops {
        int (*probe_device)(struct tegra_mc *mc, struct device *dev);
 };
 
+struct tegra_mc_regs {
+       unsigned int cfg_channel_enable;
+       unsigned int err_status;
+       unsigned int err_add;
+       unsigned int err_add_hi;
+       unsigned int err_vpr_status;
+       unsigned int err_vpr_add;
+       unsigned int err_sec_status;
+       unsigned int err_sec_add;
+       unsigned int err_mts_status;
+       unsigned int err_mts_add;
+       unsigned int err_gen_co_status;
+       unsigned int err_gen_co_add;
+       unsigned int err_route_status;
+       unsigned int err_route_add;
+};
+
 struct tegra_mc_soc {
        const struct tegra_mc_client *clients;
        unsigned int num_clients;
@@ -196,6 +213,7 @@ struct tegra_mc_soc {
 
        const struct tegra_mc_icc_ops *icc_ops;
        const struct tegra_mc_ops *ops;
+       const struct tegra_mc_regs *regs;
 };
 
 struct tegra_mc {
@@ -256,4 +274,6 @@ tegra_mc_get_carveout_info(struct tegra_mc *mc, unsigned int id,
 }
 #endif
 
+extern const struct tegra_mc_regs tegra20_mc_regs;
+
 #endif /* __SOC_TEGRA_MC_H__ */