[AArch64] Fix types for vqdmlals_lane_s32 and vqdmlsls_lane_s32 intrinsics.

	* config/aarch64/arm_neon.h (vqdmlals_lane_s32): Use scalar types
	rather than singleton vectors.
	(vqdmlsls_lane_s32): Likewise.

	* gcc.target/aarch64/scalar_intrinsics.c (test_vqdmlals_lane_s32):
	Fix types.
	(test_vqdmlsls_lane_s32): Likewise.
	* gcc.target/aarch64/simd/vqdmlals_lane_s32.c: Likewise.
	* gcc.target/aarch64/simd/vqdmlsls_lane_s32.c: Likewise.

From-SVN: r213636

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 491ff3870bba25f781599760eb123d4aa65a8ec5..560f6e43ecdcfdf5b71b2b987b0e82050d15f2fc 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2014-08-05  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       * config/aarch64/arm_neon.h (vqdmlals_lane_s32): Use scalar types
+       rather than singleton vectors.
+       (vqdmlsls_lane_s32): Likewise.
+
 2014-08-05  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
        * config/aarch64/aarch64-simd.md (aarch64_sqdmulh_laneq<mode>):

diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index 1289ce170fd10f40fa541192fee14051d21bbcca..0a86172ccb9aa9ab026f4aa020fd4418098e0923 100644 (file)
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -19457,11 +19457,10 @@ vqdmlals_s32 (int64_t __a, int32x1_t __b, int32x1_t __c)
   return __builtin_aarch64_sqdmlalsi (__a, __b, __c);
 }
 
-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
-vqdmlals_lane_s32 (int64x1_t __a, int32x1_t __b, int32x2_t __c, const int __d)
+__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+vqdmlals_lane_s32 (int64_t __a, int32_t __b, int32x2_t __c, const int __d)
 {
-  return (int64x1_t)
-      {__builtin_aarch64_sqdmlal_lanesi (__a[0], __b, __c, __d)};
+  return __builtin_aarch64_sqdmlal_lanesi (__a, __b, __c, __d);
 }
 
 __extension__ static __inline int64_t __attribute__ ((__always_inline__))
@@ -19596,10 +19595,10 @@ vqdmlsls_s32 (int64_t __a, int32x1_t __b, int32x1_t __c)
   return __builtin_aarch64_sqdmlslsi (__a, __b, __c);
 }
 
-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
-vqdmlsls_lane_s32 (int64x1_t __a, int32x1_t __b, int32x2_t __c, const int __d)
+__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+vqdmlsls_lane_s32 (int64_t __a, int32_t __b, int32x2_t __c, const int __d)
 {
-  return (int64x1_t) {__builtin_aarch64_sqdmlsl_lanesi (__a[0], __b, __c, __d)};
+  return __builtin_aarch64_sqdmlsl_lanesi (__a, __b, __c, __d);
 }
 
 __extension__ static __inline int64_t __attribute__ ((__always_inline__))

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index b218b0bda59f02826aec357823f17a36727a99dc..dbe59e58471d30085e62a7dacaa3e086652c4ac8 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2014-08-05  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       * gcc.target/aarch64/scalar_intrinsics.c (test_vqdmlals_lane_s32):
+       Fix types.
+       (test_vqdmlsls_lane_s32): Likewise.
+       * gcc.target/aarch64/simd/vqdmlals_lane_s32.c: Likewise.
+       * gcc.target/aarch64/simd/vqdmlsls_lane_s32.c: Likewise.
+
 2014-08-05  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
        * gcc.target/aarch64/simd/vqdmlalh_laneq_s16_1.c: New test.

diff --git a/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c b/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c
index 0e288f292e443b06b9654f24186eee3265b00994..2bd762cdcb86d327fb0ab7fc3d8e4f0d41b81a3e 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c
+++ b/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c
@@ -405,8 +405,8 @@ test_vqdmlals_s32 (int64_t a, int32x1_t b, int32x1_t c)
 
 /* { dg-final { scan-assembler-times "\\tsqdmlal\\td\[0-9\]+, s\[0-9\]+, v" 1 } } */
 
-int64x1_t
-test_vqdmlals_lane_s32 (int64x1_t a, int32x1_t b, int32x2_t c)
+int64_t
+test_vqdmlals_lane_s32 (int64_t a, int32_t b, int32x2_t c)
 {
   return vqdmlals_lane_s32 (a, b, c, 1);
 }
@@ -437,8 +437,8 @@ test_vqdmlsls_s32 (int64_t a, int32x1_t b, int32x1_t c)
 
 /* { dg-final { scan-assembler-times "\\tsqdmlsl\\td\[0-9\]+, s\[0-9\]+, v" 1 } } */
 
-int64x1_t
-test_vqdmlsls_lane_s32 (int64x1_t a, int32x1_t b, int32x2_t c)
+int64_t
+test_vqdmlsls_lane_s32 (int64_t a, int32_t b, int32x2_t c)
 {
   return vqdmlsls_lane_s32 (a, b, c, 1);
 }

diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmlals_lane_s32.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlals_lane_s32.c
index ef94e95d97142ad450824d39c74bad15b555fe31..38352c54dcaba70a29f84047925bdeef9a3226ef 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/simd/vqdmlals_lane_s32.c
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlals_lane_s32.c
@@ -5,8 +5,8 @@
 
 #include "arm_neon.h"
 
-int64x1_t
-t_vqdmlals_lane_s32 (int64x1_t a, int32x1_t b, int32x2_t c)
+int64_t
+t_vqdmlals_lane_s32 (int64_t a, int32_t b, int32x2_t c)
 {
   return vqdmlals_lane_s32 (a, b, c, 0);
 }

diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsls_lane_s32.c b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsls_lane_s32.c
index 9e351bc360fd578475480e79078153d3fb69b058..3c6089887d024703cce8587e3b78a38b760bba72 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsls_lane_s32.c
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vqdmlsls_lane_s32.c
@@ -5,8 +5,8 @@
 
 #include "arm_neon.h"
 
-int64x1_t
-t_vqdmlsls_lane_s32 (int64x1_t a, int32x1_t b, int32x2_t c)
+int64_t
+t_vqdmlsls_lane_s32 (int64_t a, int32_t b, int32x2_t c)
 {
   return vqdmlsls_lane_s32 (a, b, c, 0);
 }