--- /dev/null
+From aca7c13d3bee81a968337a5515411409ae9d095d Mon Sep 17 00:00:00 2001
+From: Helge Deller <deller@gmx.de>
+Date: Fri, 14 Oct 2022 10:13:55 +0200
+Subject: parisc: fbdev/stifb: Align graphics memory size to 4MB
+
+From: Helge Deller <deller@gmx.de>
+
+commit aca7c13d3bee81a968337a5515411409ae9d095d upstream.
+
+Independend of the current graphics resolution, adjust the reported
+graphics card memory size to the next 4MB boundary.
+This fixes the fbtest program which expects a naturally aligned size.
+
+Signed-off-by: Helge Deller <deller@gmx.de>
+Cc: <stable@vger.kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/video/fbdev/stifb.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/video/fbdev/stifb.c
++++ b/drivers/video/fbdev/stifb.c
+@@ -1298,7 +1298,7 @@ static int __init stifb_init_fb(struct s
+
+ /* limit fbsize to max visible screen size */
+ if (fix->smem_len > yres*fix->line_length)
+- fix->smem_len = yres*fix->line_length;
++ fix->smem_len = ALIGN(yres*fix->line_length, 4*1024*1024);
+
+ fix->accel = FB_ACCEL_NONE;
+
--- /dev/null
+From 70be49f2f6223ddd2fcddb0089a40864c37e1494 Mon Sep 17 00:00:00 2001
+From: Helge Deller <deller@gmx.de>
+Date: Fri, 14 Oct 2022 10:18:53 +0200
+Subject: parisc: Fix userspace graphics card breakage due to pgtable special bit
+
+From: Helge Deller <deller@gmx.de>
+
+commit 70be49f2f6223ddd2fcddb0089a40864c37e1494 upstream.
+
+Commit df24e1783e6e ("parisc: Add vDSO support") introduced the vDSO
+support, for which a _PAGE_SPECIAL page table flag was needed. Since we
+wanted to keep every page table entry in 32-bits, this patch re-used the
+existing - but yet unused - _PAGE_DMB flag (which triggers a hardware break
+if a page is accessed) to store the special bit.
+
+But when graphics card memory is mmapped into userspace, the kernel uses
+vm_iomap_memory() which sets the the special flag. So, with the DMB bit
+set, every access to the graphics memory now triggered a hardware
+exception and segfaulted the userspace program.
+
+Fix this breakage by dropping the DMB bit when writing the page
+protection bits to the CPU TLB.
+
+In addition this patch adds a small optimization: if huge pages aren't
+configured (which is at least the case for 32-bit kernels), then the
+special bit is stored in the hpage (HUGE PAGE) bit instead. That way we
+can skip to reset the DMB bit.
+
+Fixes: df24e1783e6e ("parisc: Add vDSO support")
+Cc: <stable@vger.kernel.org> # 5.18+
+Signed-off-by: Helge Deller <deller@gmx.de>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/parisc/include/asm/pgtable.h | 7 ++++++-
+ arch/parisc/kernel/entry.S | 8 ++++++++
+ 2 files changed, 14 insertions(+), 1 deletion(-)
+
+--- a/arch/parisc/include/asm/pgtable.h
++++ b/arch/parisc/include/asm/pgtable.h
+@@ -192,6 +192,11 @@ extern void __update_cache(pte_t pte);
+ #define _PAGE_PRESENT_BIT 22 /* (0x200) Software: translation valid */
+ #define _PAGE_HPAGE_BIT 21 /* (0x400) Software: Huge Page */
+ #define _PAGE_USER_BIT 20 /* (0x800) Software: User accessible page */
++#ifdef CONFIG_HUGETLB_PAGE
++#define _PAGE_SPECIAL_BIT _PAGE_DMB_BIT /* DMB feature is currently unused */
++#else
++#define _PAGE_SPECIAL_BIT _PAGE_HPAGE_BIT /* use unused HUGE PAGE bit */
++#endif
+
+ /* N.B. The bits are defined in terms of a 32 bit word above, so the */
+ /* following macro is ok for both 32 and 64 bit. */
+@@ -219,7 +224,7 @@ extern void __update_cache(pte_t pte);
+ #define _PAGE_PRESENT (1 << xlate_pabit(_PAGE_PRESENT_BIT))
+ #define _PAGE_HUGE (1 << xlate_pabit(_PAGE_HPAGE_BIT))
+ #define _PAGE_USER (1 << xlate_pabit(_PAGE_USER_BIT))
+-#define _PAGE_SPECIAL (_PAGE_DMB)
++#define _PAGE_SPECIAL (1 << xlate_pabit(_PAGE_SPECIAL_BIT))
+
+ #define _PAGE_TABLE (_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_ACCESSED)
+ #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_SPECIAL)
+--- a/arch/parisc/kernel/entry.S
++++ b/arch/parisc/kernel/entry.S
+@@ -499,6 +499,10 @@
+ * Finally, _PAGE_READ goes in the top bit of PL1 (so we
+ * trigger an access rights trap in user space if the user
+ * tries to read an unreadable page */
++#if _PAGE_SPECIAL_BIT == _PAGE_DMB_BIT
++ /* need to drop DMB bit, as it's used as SPECIAL flag */
++ depi 0,_PAGE_SPECIAL_BIT,1,\pte
++#endif
+ depd \pte,8,7,\prot
+
+ /* PAGE_USER indicates the page can be read with user privileges,
+@@ -529,6 +533,10 @@
+ * makes the tlb entry for the differently formatted pa11
+ * insertion instructions */
+ .macro make_insert_tlb_11 spc,pte,prot
++#if _PAGE_SPECIAL_BIT == _PAGE_DMB_BIT
++ /* need to drop DMB bit, as it's used as SPECIAL flag */
++ depi 0,_PAGE_SPECIAL_BIT,1,\pte
++#endif
+ zdep \spc,30,15,\prot
+ dep \pte,8,7,\prot
+ extru,= \pte,_PAGE_NO_CACHE_BIT,1,%r0
--- /dev/null
+From 9cc205e3c17d5716da7ebb7fa0c985555e95d009 Mon Sep 17 00:00:00 2001
+From: "Maciej W. Rozycki" <macro@orcam.me.uk>
+Date: Thu, 22 Sep 2022 22:56:06 +0100
+Subject: RISC-V: Make port I/O string accessors actually work
+
+From: Maciej W. Rozycki <macro@orcam.me.uk>
+
+commit 9cc205e3c17d5716da7ebb7fa0c985555e95d009 upstream.
+
+Fix port I/O string accessors such as `insb', `outsb', etc. which use
+the physical PCI port I/O address rather than the corresponding memory
+mapping to get at the requested location, which in turn breaks at least
+accesses made by our parport driver to a PCIe parallel port such as:
+
+PCI parallel port detected: 1415:c118, I/O at 0x1000(0x1008), IRQ 20
+parport0: PC-style at 0x1000 (0x1008), irq 20, using FIFO [PCSPP,TRISTATE,COMPAT,EPP,ECP]
+
+causing a memory access fault:
+
+Unable to handle kernel access to user memory without uaccess routines at virtual address 0000000000001008
+Oops [#1]
+Modules linked in:
+CPU: 1 PID: 350 Comm: cat Not tainted 6.0.0-rc2-00283-g10d4879f9ef0-dirty #23
+Hardware name: SiFive HiFive Unmatched A00 (DT)
+epc : parport_pc_fifo_write_block_pio+0x266/0x416
+ ra : parport_pc_fifo_write_block_pio+0xb4/0x416
+epc : ffffffff80542c3e ra : ffffffff80542a8c sp : ffffffd88899fc60
+ gp : ffffffff80fa2700 tp : ffffffd882b1e900 t0 : ffffffd883d0b000
+ t1 : ffffffffff000002 t2 : 4646393043330a38 s0 : ffffffd88899fcf0
+ s1 : 0000000000001000 a0 : 0000000000000010 a1 : 0000000000000000
+ a2 : ffffffd883d0a010 a3 : 0000000000000023 a4 : 00000000ffff8fbb
+ a5 : ffffffd883d0a001 a6 : 0000000100000000 a7 : ffffffc800000000
+ s2 : ffffffffff000002 s3 : ffffffff80d28880 s4 : ffffffff80fa1f50
+ s5 : 0000000000001008 s6 : 0000000000000008 s7 : ffffffd883d0a000
+ s8 : 0004000000000000 s9 : ffffffff80dc1d80 s10: ffffffd8807e4000
+ s11: 0000000000000000 t3 : 00000000000000ff t4 : 393044410a303930
+ t5 : 0000000000001000 t6 : 0000000000040000
+status: 0000000200000120 badaddr: 0000000000001008 cause: 000000000000000f
+[<ffffffff80543212>] parport_pc_compat_write_block_pio+0xfe/0x200
+[<ffffffff8053bbc0>] parport_write+0x46/0xf8
+[<ffffffff8050530e>] lp_write+0x158/0x2d2
+[<ffffffff80185716>] vfs_write+0x8e/0x2c2
+[<ffffffff80185a74>] ksys_write+0x52/0xc2
+[<ffffffff80185af2>] sys_write+0xe/0x16
+[<ffffffff80003770>] ret_from_syscall+0x0/0x2
+---[ end trace 0000000000000000 ]---
+
+For simplicity address the problem by adding PCI_IOBASE to the physical
+address requested in the respective wrapper macros only, observing that
+the raw accessors such as `__insb', `__outsb', etc. are not supposed to
+be used other than by said macros. Remove the cast to `long' that is no
+longer needed on `addr' now that it is used as an offset from PCI_IOBASE
+and add parentheses around `addr' needed for predictable evaluation in
+macro expansion. No need to make said adjustments in separate changes
+given that current code is gravely broken and does not ever work.
+
+Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
+Fixes: fab957c11efe2 ("RISC-V: Atomic and Locking Code")
+Cc: stable@vger.kernel.org # v4.15+
+Reviewed-by: Arnd Bergmann <arnd@arndb.de>
+Link: https://lore.kernel.org/r/alpine.DEB.2.21.2209220223080.29493@angie.orcam.me.uk
+Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/riscv/include/asm/io.h | 16 ++++++++--------
+ 1 file changed, 8 insertions(+), 8 deletions(-)
+
+--- a/arch/riscv/include/asm/io.h
++++ b/arch/riscv/include/asm/io.h
+@@ -101,9 +101,9 @@ __io_reads_ins(reads, u32, l, __io_br(),
+ __io_reads_ins(ins, u8, b, __io_pbr(), __io_par(addr))
+ __io_reads_ins(ins, u16, w, __io_pbr(), __io_par(addr))
+ __io_reads_ins(ins, u32, l, __io_pbr(), __io_par(addr))
+-#define insb(addr, buffer, count) __insb((void __iomem *)(long)addr, buffer, count)
+-#define insw(addr, buffer, count) __insw((void __iomem *)(long)addr, buffer, count)
+-#define insl(addr, buffer, count) __insl((void __iomem *)(long)addr, buffer, count)
++#define insb(addr, buffer, count) __insb(PCI_IOBASE + (addr), buffer, count)
++#define insw(addr, buffer, count) __insw(PCI_IOBASE + (addr), buffer, count)
++#define insl(addr, buffer, count) __insl(PCI_IOBASE + (addr), buffer, count)
+
+ __io_writes_outs(writes, u8, b, __io_bw(), __io_aw())
+ __io_writes_outs(writes, u16, w, __io_bw(), __io_aw())
+@@ -115,22 +115,22 @@ __io_writes_outs(writes, u32, l, __io_bw
+ __io_writes_outs(outs, u8, b, __io_pbw(), __io_paw())
+ __io_writes_outs(outs, u16, w, __io_pbw(), __io_paw())
+ __io_writes_outs(outs, u32, l, __io_pbw(), __io_paw())
+-#define outsb(addr, buffer, count) __outsb((void __iomem *)(long)addr, buffer, count)
+-#define outsw(addr, buffer, count) __outsw((void __iomem *)(long)addr, buffer, count)
+-#define outsl(addr, buffer, count) __outsl((void __iomem *)(long)addr, buffer, count)
++#define outsb(addr, buffer, count) __outsb(PCI_IOBASE + (addr), buffer, count)
++#define outsw(addr, buffer, count) __outsw(PCI_IOBASE + (addr), buffer, count)
++#define outsl(addr, buffer, count) __outsl(PCI_IOBASE + (addr), buffer, count)
+
+ #ifdef CONFIG_64BIT
+ __io_reads_ins(reads, u64, q, __io_br(), __io_ar(addr))
+ #define readsq(addr, buffer, count) __readsq(addr, buffer, count)
+
+ __io_reads_ins(ins, u64, q, __io_pbr(), __io_par(addr))
+-#define insq(addr, buffer, count) __insq((void __iomem *)addr, buffer, count)
++#define insq(addr, buffer, count) __insq(PCI_IOBASE + (addr), buffer, count)
+
+ __io_writes_outs(writes, u64, q, __io_bw(), __io_aw())
+ #define writesq(addr, buffer, count) __writesq(addr, buffer, count)
+
+ __io_writes_outs(outs, u64, q, __io_pbr(), __io_paw())
+-#define outsq(addr, buffer, count) __outsq((void __iomem *)addr, buffer, count)
++#define outsq(addr, buffer, count) __outsq(PCI_IOBASE + (addr), buffer, count)
+ #endif
+
+ #include <asm-generic/io.h>
--- /dev/null
+From 5a5294fbe0200d1327f0e089135dad77b45aa2ee Mon Sep 17 00:00:00 2001
+From: Palmer Dabbelt <palmer@rivosinc.com>
+Date: Wed, 28 Sep 2022 06:18:07 -0700
+Subject: RISC-V: Re-enable counter access from userspace
+
+From: Palmer Dabbelt <palmer@rivosinc.com>
+
+commit 5a5294fbe0200d1327f0e089135dad77b45aa2ee upstream.
+
+These counters were part of the ISA when we froze the uABI, removing
+them breaks userspace.
+
+Link: https://lore.kernel.org/all/YxEhC%2FmDW1lFt36J@aurel32.net/
+Fixes: e9991434596f ("RISC-V: Add perf platform driver based on SBI PMU extension")
+Tested-by: Conor Dooley <conor.dooley@microchip.com>
+Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
+Link: https://lore.kernel.org/r/20220928131807.30386-1-palmer@rivosinc.com
+Cc: stable@vger.kernel.org
+Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/perf/riscv_pmu_sbi.c | 7 +++++--
+ 1 file changed, 5 insertions(+), 2 deletions(-)
+
+--- a/drivers/perf/riscv_pmu_sbi.c
++++ b/drivers/perf/riscv_pmu_sbi.c
+@@ -645,8 +645,11 @@ static int pmu_sbi_starting_cpu(unsigned
+ struct riscv_pmu *pmu = hlist_entry_safe(node, struct riscv_pmu, node);
+ struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events);
+
+- /* Enable the access for TIME csr only from the user mode now */
+- csr_write(CSR_SCOUNTEREN, 0x2);
++ /*
++ * Enable the access for CYCLE, TIME, and INSTRET CSRs from userspace,
++ * as is necessary to maintain uABI compatibility.
++ */
++ csr_write(CSR_SCOUNTEREN, 0x7);
+
+ /* Stop all the counters so that they can be enabled from perf */
+ pmu_sbi_stop_all(pmu);
--- /dev/null
+From 9e2e6042a7ec6504fe8e366717afa2f40cf16488 Mon Sep 17 00:00:00 2001
+From: Andrew Bresticker <abrestic@rivosinc.com>
+Date: Thu, 15 Sep 2022 15:37:02 -0400
+Subject: riscv: Allow PROT_WRITE-only mmap()
+
+From: Andrew Bresticker <abrestic@rivosinc.com>
+
+commit 9e2e6042a7ec6504fe8e366717afa2f40cf16488 upstream.
+
+Commit 2139619bcad7 ("riscv: mmap with PROT_WRITE but no PROT_READ is
+invalid") made mmap() return EINVAL if PROT_WRITE was set wihtout
+PROT_READ with the justification that a write-only PTE is considered a
+reserved PTE permission bit pattern in the privileged spec. This check
+is unnecessary since we let VM_WRITE imply VM_READ on RISC-V, and it is
+inconsistent with other architectures that don't support write-only PTEs,
+creating a potential software portability issue. Just remove the check
+altogether and let PROT_WRITE imply PROT_READ as is the case on other
+architectures.
+
+Note that this also allows PROT_WRITE|PROT_EXEC mappings which were
+disallowed prior to the aforementioned commit; PROT_READ is implied in
+such mappings as well.
+
+Fixes: 2139619bcad7 ("riscv: mmap with PROT_WRITE but no PROT_READ is invalid")
+Reviewed-by: Atish Patra <atishp@rivosinc.com>
+Signed-off-by: Andrew Bresticker <abrestic@rivosinc.com>
+Cc: stable@vger.kernel.org
+Link: https://lore.kernel.org/r/20220915193702.2201018-3-abrestic@rivosinc.com/
+Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/riscv/kernel/sys_riscv.c | 3 ---
+ 1 file changed, 3 deletions(-)
+
+--- a/arch/riscv/kernel/sys_riscv.c
++++ b/arch/riscv/kernel/sys_riscv.c
+@@ -18,9 +18,6 @@ static long riscv_sys_mmap(unsigned long
+ if (unlikely(offset & (~PAGE_MASK >> page_shift_offset)))
+ return -EINVAL;
+
+- if (unlikely((prot & PROT_WRITE) && !(prot & PROT_READ)))
+- return -EINVAL;
+-
+ return ksys_mmap_pgoff(addr, len, prot, flags, fd,
+ offset >> (PAGE_SHIFT - page_shift_offset));
+ }
--- /dev/null
+From 10f6913c548b32ecb73801a16b120e761c6957ea Mon Sep 17 00:00:00 2001
+From: Wenting Zhang <zephray@outlook.com>
+Date: Fri, 8 Jul 2022 16:38:22 -0400
+Subject: riscv: always honor the CONFIG_CMDLINE_FORCE when parsing dtb
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Wenting Zhang <zephray@outlook.com>
+
+commit 10f6913c548b32ecb73801a16b120e761c6957ea upstream.
+
+When CONFIG_CMDLINE_FORCE is enabled, cmdline provided by
+CONFIG_CMDLINE are always used. This allows CONFIG_CMDLINE to be
+used regardless of the result of device tree scanning.
+
+This especially fixes the case where a device tree without the
+chosen node is supplied to the kernel. In such cases,
+early_init_dt_scan would return true. But inside
+early_init_dt_scan_chosen, the cmdline won't be updated as there
+is no chosen node in the device tree. As a result, CONFIG_CMDLINE
+is not copied into boot_command_line even if CONFIG_CMDLINE_FORCE
+is enabled. This commit allows properly update boot_command_line
+in this situation.
+
+Fixes: 8fd6e05c7463 ("arch: riscv: support kernel command line forcing when no DTB passed")
+Signed-off-by: Wenting Zhang <zephray@outlook.com>
+Reviewed-by: Björn Töpel <bjorn@kernel.org>
+Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
+Link: https://lore.kernel.org/r/PSBPR04MB399135DFC54928AB958D0638B1829@PSBPR04MB3991.apcprd04.prod.outlook.com
+Cc: stable@vger.kernel.org
+Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/riscv/kernel/setup.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/riscv/kernel/setup.c
++++ b/arch/riscv/kernel/setup.c
+@@ -252,10 +252,10 @@ static void __init parse_dtb(void)
+ pr_info("Machine model: %s\n", name);
+ dump_stack_set_arch_desc("%s (DT)", name);
+ }
+- return;
++ } else {
++ pr_err("No DTB passed to the kernel\n");
+ }
+
+- pr_err("No DTB passed to the kernel\n");
+ #ifdef CONFIG_CMDLINE_FORCE
+ strscpy(boot_command_line, CONFIG_CMDLINE, COMMAND_LINE_SIZE);
+ pr_info("Forcing kernel command line to: %s\n", boot_command_line);
--- /dev/null
+From 7ab72c597356be1e7f0f3d856e54ce78527f43c8 Mon Sep 17 00:00:00 2001
+From: Andrew Bresticker <abrestic@rivosinc.com>
+Date: Thu, 15 Sep 2022 15:37:01 -0400
+Subject: riscv: Make VM_WRITE imply VM_READ
+
+From: Andrew Bresticker <abrestic@rivosinc.com>
+
+commit 7ab72c597356be1e7f0f3d856e54ce78527f43c8 upstream.
+
+RISC-V does not presently have write-only mappings as that PTE bit pattern
+is considered reserved in the privileged spec, so allow handling of read
+faults in VMAs that have VM_WRITE without VM_READ in order to be consistent
+with other architectures that have similar limitations.
+
+Fixes: 2139619bcad7 ("riscv: mmap with PROT_WRITE but no PROT_READ is invalid")
+Reviewed-by: Atish Patra <atishp@rivosinc.com>
+Signed-off-by: Andrew Bresticker <abrestic@rivosinc.com>
+Cc: stable@vger.kernel.org
+Link: https://lore.kernel.org/r/20220915193702.2201018-2-abrestic@rivosinc.com/
+Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/riscv/mm/fault.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/arch/riscv/mm/fault.c
++++ b/arch/riscv/mm/fault.c
+@@ -184,7 +184,8 @@ static inline bool access_error(unsigned
+ }
+ break;
+ case EXC_LOAD_PAGE_FAULT:
+- if (!(vma->vm_flags & VM_READ)) {
++ /* Write implies read */
++ if (!(vma->vm_flags & (VM_READ | VM_WRITE))) {
+ return true;
+ }
+ break;
--- /dev/null
+From 3cebf80e9a0d3adcb174053be32c88a640b3344b Mon Sep 17 00:00:00 2001
+From: Fangrui Song <maskray@google.com>
+Date: Sun, 18 Sep 2022 02:29:34 -0700
+Subject: riscv: Pass -mno-relax only on lld < 15.0.0
+
+From: Fangrui Song <maskray@google.com>
+
+commit 3cebf80e9a0d3adcb174053be32c88a640b3344b upstream.
+
+lld since llvm:6611d58f5bbc ("[ELF] Relax R_RISCV_ALIGN"), which will be
+included in the 15.0.0 release, has implemented some RISC-V linker
+relaxation. -mno-relax is no longer needed in
+KBUILD_CFLAGS/KBUILD_AFLAGS to suppress R_RISCV_ALIGN which older lld
+can not handle:
+
+ ld.lld: error: capability.c:(.fixup+0x0): relocation R_RISCV_ALIGN
+ requires unimplemented linker relaxation; recompile with -mno-relax
+ but the .o is already compiled with -mno-relax
+
+Signed-off-by: Fangrui Song <maskray@google.com>
+Link: https://lore.kernel.org/r/20220710071117.446112-1-maskray@google.com/
+Link: https://lore.kernel.org/r/20220918092933.19943-1-palmer@rivosinc.com
+Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
+Tested-by: Nick Desaulniers <ndesaulniers@google.com>
+Tested-by: Nathan Chancellor <nathan@kernel.org>
+Tested-by: Conor Dooley <conor.dooley@microchip.com>
+Cc: stable@vger.kernel.org
+Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/riscv/Makefile | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/arch/riscv/Makefile
++++ b/arch/riscv/Makefile
+@@ -37,6 +37,7 @@ else
+ endif
+
+ ifeq ($(CONFIG_LD_IS_LLD),y)
++ifeq ($(shell test $(CONFIG_LLD_VERSION) -lt 150000; echo $$?),0)
+ KBUILD_CFLAGS += -mno-relax
+ KBUILD_AFLAGS += -mno-relax
+ ifndef CONFIG_AS_IS_LLVM
+@@ -44,6 +45,7 @@ ifndef CONFIG_AS_IS_LLVM
+ KBUILD_AFLAGS += -Wa,-mno-relax
+ endif
+ endif
++endif
+
+ # ISA string setting
+ riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima
--- /dev/null
+From fbd92809997a391f28075f1c8b5ee314c225557c Mon Sep 17 00:00:00 2001
+From: Conor Dooley <conor.dooley@microchip.com>
+Date: Fri, 15 Jul 2022 18:51:56 +0100
+Subject: riscv: topology: fix default topology reporting
+
+From: Conor Dooley <conor.dooley@microchip.com>
+
+commit fbd92809997a391f28075f1c8b5ee314c225557c upstream.
+
+RISC-V has no sane defaults to fall back on where there is no cpu-map
+in the devicetree.
+Without sane defaults, the package, core and thread IDs are all set to
+-1. This causes user-visible inaccuracies for tools like hwloc/lstopo
+which rely on the sysfs cpu topology files to detect a system's
+topology.
+
+On a PolarFire SoC, which should have 4 harts with a thread each,
+lstopo currently reports:
+
+Machine (793MB total)
+ Package L#0
+ NUMANode L#0 (P#0 793MB)
+ Core L#0
+ L1d L#0 (32KB) + L1i L#0 (32KB) + PU L#0 (P#0)
+ L1d L#1 (32KB) + L1i L#1 (32KB) + PU L#1 (P#1)
+ L1d L#2 (32KB) + L1i L#2 (32KB) + PU L#2 (P#2)
+ L1d L#3 (32KB) + L1i L#3 (32KB) + PU L#3 (P#3)
+
+Adding calls to store_cpu_topology() in {boot,smp} hart bringup code
+results in the correct topolgy being reported:
+
+Machine (793MB total)
+ Package L#0
+ NUMANode L#0 (P#0 793MB)
+ L1d L#0 (32KB) + L1i L#0 (32KB) + Core L#0 + PU L#0 (P#0)
+ L1d L#1 (32KB) + L1i L#1 (32KB) + Core L#1 + PU L#1 (P#1)
+ L1d L#2 (32KB) + L1i L#2 (32KB) + Core L#2 + PU L#2 (P#2)
+ L1d L#3 (32KB) + L1i L#3 (32KB) + Core L#3 + PU L#3 (P#3)
+
+CC: stable@vger.kernel.org # 456797da792f: arm64: topology: move store_cpu_topology() to shared code
+Fixes: 03f11f03dbfe ("RISC-V: Parse cpu topology during boot.")
+Reported-by: Brice Goglin <Brice.Goglin@inria.fr>
+Link: https://github.com/open-mpi/hwloc/issues/536
+Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
+Reviewed-by: Atish Patra <atishp@rivosinc.com>
+Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/riscv/Kconfig | 2 +-
+ arch/riscv/kernel/smpboot.c | 3 ++-
+ 2 files changed, 3 insertions(+), 2 deletions(-)
+
+--- a/arch/riscv/Kconfig
++++ b/arch/riscv/Kconfig
+@@ -52,7 +52,7 @@ config RISCV
+ select COMMON_CLK
+ select CPU_PM if CPU_IDLE
+ select EDAC_SUPPORT
+- select GENERIC_ARCH_TOPOLOGY if SMP
++ select GENERIC_ARCH_TOPOLOGY
+ select GENERIC_ATOMIC64 if !64BIT
+ select GENERIC_CLOCKEVENTS_BROADCAST if SMP
+ select GENERIC_EARLY_IOREMAP
+--- a/arch/riscv/kernel/smpboot.c
++++ b/arch/riscv/kernel/smpboot.c
+@@ -49,6 +49,7 @@ void __init smp_prepare_cpus(unsigned in
+ unsigned int curr_cpuid;
+
+ curr_cpuid = smp_processor_id();
++ store_cpu_topology(curr_cpuid);
+ numa_store_cpu_info(curr_cpuid);
+ numa_add_cpu(curr_cpuid);
+
+@@ -162,9 +163,9 @@ asmlinkage __visible void smp_callin(voi
+ mmgrab(mm);
+ current->active_mm = mm;
+
++ store_cpu_topology(curr_cpuid);
+ notify_cpu_starting(curr_cpuid);
+ numa_add_cpu(curr_cpuid);
+- update_siblings_masks(curr_cpuid);
+ set_cpu_online(curr_cpuid, 1);
+
+ /*
--- /dev/null
+From a8616d2dc193b6becc36b5f3cfeaa9ac7a5762f9 Mon Sep 17 00:00:00 2001
+From: Jisheng Zhang <jszhang@kernel.org>
+Date: Sat, 24 Sep 2022 15:07:37 +0800
+Subject: riscv: vdso: fix NULL deference in vdso_join_timens() when vfork
+
+From: Jisheng Zhang <jszhang@kernel.org>
+
+commit a8616d2dc193b6becc36b5f3cfeaa9ac7a5762f9 upstream.
+
+Testing tools/testing/selftests/timens/vfork_exec.c got below
+kernel log:
+
+[ 6.838454] Unable to handle kernel access to user memory without uaccess routines at virtual address 0000000000000020
+[ 6.842255] Oops [#1]
+[ 6.842871] Modules linked in:
+[ 6.844249] CPU: 1 PID: 64 Comm: vfork_exec Not tainted 6.0.0-rc3-rt15+ #8
+[ 6.845861] Hardware name: riscv-virtio,qemu (DT)
+[ 6.848009] epc : vdso_join_timens+0xd2/0x110
+[ 6.850097] ra : vdso_join_timens+0xd2/0x110
+[ 6.851164] epc : ffffffff8000635c ra : ffffffff8000635c sp : ff6000000181fbf0
+[ 6.852562] gp : ffffffff80cff648 tp : ff60000000fdb700 t0 : 3030303030303030
+[ 6.853852] t1 : 0000000000000030 t2 : 3030303030303030 s0 : ff6000000181fc40
+[ 6.854984] s1 : ff60000001e6c000 a0 : 0000000000000010 a1 : ffffffff8005654c
+[ 6.856221] a2 : 00000000ffffefff a3 : 0000000000000000 a4 : 0000000000000000
+[ 6.858114] a5 : 0000000000000000 a6 : 0000000000000008 a7 : 0000000000000038
+[ 6.859484] s2 : ff60000001e6c068 s3 : ff6000000108abb0 s4 : 0000000000000000
+[ 6.860751] s5 : 0000000000001000 s6 : ffffffff8089dc40 s7 : ffffffff8089dc38
+[ 6.862029] s8 : ffffffff8089dc30 s9 : ff60000000fdbe38 s10: 000000000000005e
+[ 6.863304] s11: ffffffff80cc3510 t3 : ffffffff80d1112f t4 : ffffffff80d1112f
+[ 6.864565] t5 : ffffffff80d11130 t6 : ff6000000181fa00
+[ 6.865561] status: 0000000000000120 badaddr: 0000000000000020 cause: 000000000000000d
+[ 6.868046] [<ffffffff8008dc94>] timens_commit+0x38/0x11a
+[ 6.869089] [<ffffffff8008dde8>] timens_on_fork+0x72/0xb4
+[ 6.870055] [<ffffffff80190096>] begin_new_exec+0x3c6/0x9f0
+[ 6.871231] [<ffffffff801d826c>] load_elf_binary+0x628/0x1214
+[ 6.872304] [<ffffffff8018ee7a>] bprm_execve+0x1f2/0x4e4
+[ 6.873243] [<ffffffff8018f90c>] do_execveat_common+0x16e/0x1ee
+[ 6.874258] [<ffffffff8018f9c8>] sys_execve+0x3c/0x48
+[ 6.875162] [<ffffffff80003556>] ret_from_syscall+0x0/0x2
+[ 6.877484] ---[ end trace 0000000000000000 ]---
+
+This is because the mm->context.vdso_info is NULL in vfork case. From
+another side, mm->context.vdso_info either points to vdso info
+for RV64 or vdso info for compat, there's no need to bloat riscv's
+mm_context_t, we can handle the difference when setup the additional
+page for vdso.
+
+Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
+Suggested-by: Palmer Dabbelt <palmer@rivosinc.com>
+Fixes: 3092eb456375 ("riscv: compat: vdso: Add setup additional pages implementation")
+Link: https://lore.kernel.org/r/20220924070737.3048-1-jszhang@kernel.org
+Cc: stable@vger.kernel.org
+Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/riscv/include/asm/mmu.h | 1 -
+ arch/riscv/kernel/vdso.c | 13 ++++++++++---
+ 2 files changed, 10 insertions(+), 4 deletions(-)
+
+--- a/arch/riscv/include/asm/mmu.h
++++ b/arch/riscv/include/asm/mmu.h
+@@ -16,7 +16,6 @@ typedef struct {
+ atomic_long_t id;
+ #endif
+ void *vdso;
+- void *vdso_info;
+ #ifdef CONFIG_SMP
+ /* A local icache flush is needed before user execution can resume. */
+ cpumask_t icache_stale_mask;
+--- a/arch/riscv/kernel/vdso.c
++++ b/arch/riscv/kernel/vdso.c
+@@ -60,6 +60,11 @@ struct __vdso_info {
+ struct vm_special_mapping *cm;
+ };
+
++static struct __vdso_info vdso_info;
++#ifdef CONFIG_COMPAT
++static struct __vdso_info compat_vdso_info;
++#endif
++
+ static int vdso_mremap(const struct vm_special_mapping *sm,
+ struct vm_area_struct *new_vma)
+ {
+@@ -114,15 +119,18 @@ int vdso_join_timens(struct task_struct
+ {
+ struct mm_struct *mm = task->mm;
+ struct vm_area_struct *vma;
+- struct __vdso_info *vdso_info = mm->context.vdso_info;
+
+ mmap_read_lock(mm);
+
+ for (vma = mm->mmap; vma; vma = vma->vm_next) {
+ unsigned long size = vma->vm_end - vma->vm_start;
+
+- if (vma_is_special_mapping(vma, vdso_info->dm))
++ if (vma_is_special_mapping(vma, vdso_info.dm))
+ zap_page_range(vma, vma->vm_start, size);
++#ifdef CONFIG_COMPAT
++ if (vma_is_special_mapping(vma, compat_vdso_info.dm))
++ zap_page_range(vma, vma->vm_start, size);
++#endif
+ }
+
+ mmap_read_unlock(mm);
+@@ -264,7 +272,6 @@ static int __setup_additional_pages(stru
+
+ vdso_base += VVAR_SIZE;
+ mm->context.vdso = (void *)vdso_base;
+- mm->context.vdso_info = (void *)vdso_info;
+
+ ret =
+ _install_special_mapping(mm, vdso_base, vdso_text_len,
hwmon-gsc-hwmon-call-of_node_get-before-of_find_xxx-api.patch
net-thunderbolt-enable-dma-paths-only-after-rings-are-enabled.patch
regulator-qcom_rpm-fix-circular-deferral-regression.patch
+riscv-topology-fix-default-topology-reporting.patch
+risc-v-re-enable-counter-access-from-userspace.patch
+risc-v-make-port-i-o-string-accessors-actually-work.patch
+parisc-fbdev-stifb-align-graphics-memory-size-to-4mb.patch
+parisc-fix-userspace-graphics-card-breakage-due-to-pgtable-special-bit.patch
+riscv-vdso-fix-null-deference-in-vdso_join_timens-when-vfork.patch
+riscv-allow-prot_write-only-mmap.patch
+riscv-make-vm_write-imply-vm_read.patch
+riscv-always-honor-the-config_cmdline_force-when-parsing-dtb.patch
+riscv-pass-mno-relax-only-on-lld-15.0.0.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
