clk: samsung: pll: Fix possible truncation in a9fraco recalc rate

samsung_a9fraco_recalc_rate(), unlike other functions in the unit, is
the first case dividing u64 by u64, thus it should rather use div64_u64
to avoid possible truncation.  Note that the original code did not
use remainder.

This fixes Coccinelle warning:

  clk-pll.c:1489:1-7: WARNING: do_div() does a 64-by-32 division, please consider using div64_u64 instead.

Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202602250053.wEU1hlpY-lkp@intel.com/
Fixes: f051dc5bc8e7 ("clk: samsung: Add clock PLL support for ARTPEC-9 SoC")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/20260226205445.336839-3-krzysztof.kozlowski@oss.qualcomm.com
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>

diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 0d0494927e59664943d6505551371f0ddb1d6b78..fdb84bcec9127b22f4635d2cb8a702d55f2f6be7 100644 (file)
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -1485,7 +1485,7 @@ static unsigned long samsung_a9fraco_recalc_rate(struct clk_hw *hw,
        /* fvco = fref * (M + K/2^24) / p * (S+1) */
        fvco *= mdiv;
        fvco = (fvco << 24) + kdiv;
-       do_div(fvco, ((pdiv * (sdiv + 1)) << 24));
+       fvco = div64_u64(fvco, ((pdiv * (sdiv + 1)) << 24));
 
        return (unsigned long)fvco;
 }