mtd: rawnand: pl353: make sure optimal timings are applied

Timings of the nand are adjusted by pl35x_nfc_setup_interface() but
actually applied by the pl35x_nand_select_target() function.
If there is only one nand chip, the pl35x_nand_select_target() will only
apply the timings once since the test at its beginning will always be true
after the first call to this function. As a result, the hardware will
keep using the default timings set at boot to detect the nand chip, not
the optimal ones.

With this patch, we program directly the new timings when
pl35x_nfc_setup_interface() is called.

Fixes: 08d8c62164a3 ("mtd: rawnand: pl353: Add support for the ARM PL353 SMC NAND controller")
Signed-off-by: Olivier Sobrie <olivier@sobrie.be>
Cc: stable@vger.kernel.org
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>

diff --git a/drivers/mtd/nand/raw/pl35x-nand-controller.c b/drivers/mtd/nand/raw/pl35x-nand-controller.c
index 947fd86ac5fa2b75a13cd02dc598522f33158929..f2c65eb7a8d9aaa36c44d78ddbb39f4bb639fc04 100644 (file)
--- a/drivers/mtd/nand/raw/pl35x-nand-controller.c
+++ b/drivers/mtd/nand/raw/pl35x-nand-controller.c
@@ -862,6 +862,9 @@ static int pl35x_nfc_setup_interface(struct nand_chip *chip, int cs,
                          PL35X_SMC_NAND_TAR_CYCLES(tmgs.t_ar) |
                          PL35X_SMC_NAND_TRR_CYCLES(tmgs.t_rr);
 
+       writel(plnand->timings, nfc->conf_regs + PL35X_SMC_CYCLES);
+       pl35x_smc_update_regs(nfc);
+
        return 0;
 }