arm64: dts: qcom: ipq6018: switch TCSR mutex to MMIO

[ Upstream commit f5e303aefc06b7508d7a490f9a2d80e4dc134c70 ]

The TCSR mutex bindings allow device to be described only with address
space (so it uses MMIO, not syscon regmap).  This seems reasonable as
TCSR mutex is actually a dedicated IO address space and it also fixes DT
schema checks:

  qcom/ipq6018-cp01-c1.dtb: hwlock: 'reg' is a required property
  qcom/ipq6018-cp01-c1.dtb: hwlock: 'syscon' does not match any of the regexes: 'pinctrl-[0-9]+'

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220909092035.223915-12-krzysztof.kozlowski@linaro.org
Stable-dep-of: 72fc3d58b87b ("arm64: dts: qcom: ipq6018: Fix tcsr_mutex register size")
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index 13651a5ac5a6936b66a1868757aa50d07b80963b..43339557d7e5aee215c4b7f7e3d6ec2245f7b68f 100644 (file)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -129,12 +129,6 @@
                };
        };
 
-       tcsr_mutex: hwlock {
-               compatible = "qcom,tcsr-mutex";
-               syscon = <&tcsr_mutex_regs 0 0x80>;
-               #hwlock-cells = <1>;
-       };
-
        pmuv8: pmu {
                compatible = "arm,cortex-a53-pmu";
                interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
@@ -253,9 +247,10 @@
                        #reset-cells = <1>;
                };
 
-               tcsr_mutex_regs: syscon@1905000 {
-                       compatible = "syscon";
-                       reg = <0x0 0x01905000 0x0 0x8000>;
+               tcsr_mutex: hwlock@1905000 {
+                       compatible = "qcom,ipq6018-tcsr-mutex", "qcom,tcsr-mutex";
+                       reg = <0x0 0x01905000 0x0 0x1000>;
+                       #hwlock-cells = <1>;
                };
 
                tcsr: syscon@1937000 {