clk: xgene: Fix divider with non-zero shift value

commit 1382ea631ddddb634850a3795527db0feeff5aaf upstream.

The X-Gene clock driver missed the divider shift operation when
set the divider value.

Signed-off-by: Loc Ho <lho@apm.com>
Fixes: 308964caeebc ("clk: Add APM X-Gene SoC clock driver")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Luis Henriques <luis.henriques@canonical.com>

diff --git a/drivers/clk/clk-xgene.c b/drivers/clk/clk-xgene.c
index dd8a62d8f11f12da7aa51b6bace5287bf4532b7d..1ec5fe8494a157253f257cabf5249e0d82998f38 100644 (file)
--- a/drivers/clk/clk-xgene.c
+++ b/drivers/clk/clk-xgene.c
@@ -351,7 +351,8 @@ static int xgene_clk_set_rate(struct clk_hw *hw, unsigned long rate,
                /* Set new divider */
                data = xgene_clk_read(pclk->param.divider_reg +
                                pclk->param.reg_divider_offset);
-               data &= ~((1 << pclk->param.reg_divider_width) - 1);
+               data &= ~((1 << pclk->param.reg_divider_width) - 1)
+                               << pclk->param.reg_divider_shift;
                data |= divider;
                xgene_clk_write(data, pclk->param.divider_reg +
                                        pclk->param.reg_divider_offset);