Similar to Bug 417452, where the instruction selector sometimes attempted
to generate vector stores with a 20-bit displacement, the same problem has
now been reported with vector loads.
The problem is caused in s390_isel_vec_expr_wrk(), where the addressing
mode is generated with s390_isel_amode() instead of
s390_isel_amode_short(). This is fixed.
426123 PPC ISA 3.1 support is missing, part 3
427787 Support new faccessat2 linux syscall (439)
428035 drd: Unbreak the musl build
+428648 s390_emit_load_mem panics due to 20-bit offset for vector load
Release 3.16.1 (?? June 2020)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/* --------- LOAD --------- */
case Iex_Load: {
HReg dst = newVRegV(env);
- s390_amode *am = s390_isel_amode(env, expr->Iex.Load.addr);
+ s390_amode *am = s390_isel_amode_short(env, expr->Iex.Load.addr);
if (expr->Iex.Load.end != Iend_BE)
goto irreducible;