mmc: sdhci-pci: Fix Braswell eMMC timeout clock frequency

commit a06586b62db5c63752e2e68daffec4baa275d594 upstream.

Braswell eMMC host controller specifies an incorrect
timeout clock frequncy in the capabilities registers.
The correct value is 1 MHz.

Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Luis Henriques <luis.henriques@canonical.com>

diff --git a/drivers/mmc/host/sdhci-pci.c b/drivers/mmc/host/sdhci-pci.c
index e958926300a4a7701eee75d8407ef5eb0cf95e0b..7a55466d81da5d9b991301efe49cb26d5229af2b 100644 (file)
--- a/drivers/mmc/host/sdhci-pci.c
+++ b/drivers/mmc/host/sdhci-pci.c
@@ -271,6 +271,8 @@ static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
                                 MMC_CAP_HW_RESET;
        slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ;
        slot->hw_reset = sdhci_pci_int_hw_reset;
+       if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
+               slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
        return 0;
 }