default:
break;
}
+ /* Parse family and model for family 0x12. */
+ else if (cpu_model2->__cpu_family == 0x12)
+ switch (cpu_model2->__cpu_model)
+ {
+ case 0x01:
+ case 0x03:
+ /* Nova Lake. */
+ cpu = "novalake";
+ CHECK___builtin_cpu_is ("corei7");
+ CHECK___builtin_cpu_is ("novalake");
+ cpu_model->__cpu_type = INTEL_COREI7;
+ cpu_model->__cpu_subtype = INTEL_COREI7_NOVALAKE;
+ break;
+ default:
+ break;
+ }
/* Parse family and model for family 0x13. */
else if (cpu_model2->__cpu_family == 0x13)
switch (cpu_model2->__cpu_model)
"arrowlake-s",
"pantherlake",
"diamondrapids",
+ "novalake",
"intel",
"lujiazui",
"yongfeng",
M_CPU_SUBTYPE (INTEL_COREI7_DIAMONDRAPIDS), P_PROC_AVX10_1},
{"wildcatlake", PROCESSOR_PANTHERLAKE, CPU_HASWELL, PTA_PANTHERLAKE,
M_CPU_SUBTYPE (INTEL_COREI7_PANTHERLAKE), P_PROC_AVX2},
+ {"novalake", PROCESSOR_NOVALAKE, CPU_HASWELL, PTA_NOVALAKE,
+ M_CPU_SUBTYPE (INTEL_COREI7_NOVALAKE), P_PROC_AVX2},
{"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL,
M_CPU_TYPE (INTEL_BONNELL), P_PROC_SSSE3},
{"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL,
AMDFAM1AH_ZNVER5,
ZHAOXIN_FAM7H_SHIJIDADAO,
INTEL_COREI7_DIAMONDRAPIDS,
+ INTEL_COREI7_NOVALAKE,
CPU_SUBTYPE_MAX
};
sapphirerapids alderlake rocketlake eden-x2 nano nano-1000 nano-2000 nano-3000 \
nano-x2 eden-x4 nano-x4 lujiazui yongfeng shijidadao x86-64 x86-64-v2 \
x86-64-v3 x86-64-v4 sierraforest graniterapids graniterapids-d grandridge \
-arrowlake arrowlake-s clearwaterforest pantherlake diamondrapids native"
+arrowlake arrowlake-s clearwaterforest pantherlake diamondrapids novalake \
+native"
# Additional x86 processors supported by --with-cpu=. Each processor
# MUST be separated by exactly one space.
processor = PROCESSOR_PENTIUM;
break;
case 6:
+ case 18:
case 19:
processor = PROCESSOR_PENTIUMPRO;
break;
/* Assume Clearwater Forest. */
if (has_feature (FEATURE_USER_MSR))
cpu = "clearwaterforest";
+ /* Assume Nova Lake. */
+ else if (has_feature (FEATURE_PREFETCHI))
+ cpu = "novalake";
else if (has_feature (FEATURE_SM3))
{
if (has_feature (FEATURE_KL))
def_or_undef (parse_in, "__diamondrapids");
def_or_undef (parse_in, "__diamondrapids__");
break;
+ case PROCESSOR_NOVALAKE:
+ def_or_undef (parse_in, "__novalake");
+ def_or_undef (parse_in, "__novalake__");
+ break;
/* use PROCESSOR_max to not set/unset the arch macro. */
case PROCESSOR_max:
case PROCESSOR_DIAMONDRAPIDS:
def_or_undef (parse_in, "__tune_diamondrapids__");
break;
+ case PROCESSOR_NOVALAKE:
+ def_or_undef (parse_in, "__tune_novalake__");
+ break;
case PROCESSOR_INTEL:
case PROCESSOR_GENERIC:
break;
#define m_ARROWLAKE_S (HOST_WIDE_INT_1U<<PROCESSOR_ARROWLAKE_S)
#define m_PANTHERLAKE (HOST_WIDE_INT_1U<<PROCESSOR_PANTHERLAKE)
#define m_DIAMONDRAPIDS (HOST_WIDE_INT_1U<<PROCESSOR_DIAMONDRAPIDS)
+#define m_NOVALAKE (HOST_WIDE_INT_1U<<PROCESSOR_NOVALAKE)
#define m_CORE_AVX512 (m_SKYLAKE_AVX512 | m_CANNONLAKE \
| m_ICELAKE_CLIENT | m_ICELAKE_SERVER | m_CASCADELAKE \
| m_TIGERLAKE | m_COOPERLAKE | m_SAPPHIRERAPIDS \
#define m_CORE_AVX2 (m_HASWELL | m_SKYLAKE | m_CORE_AVX512)
#define m_CORE_ALL (m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2)
#define m_CORE_HYBRID (m_ALDERLAKE | m_ARROWLAKE | m_ARROWLAKE_S \
- | m_PANTHERLAKE)
+ | m_PANTHERLAKE | m_NOVALAKE)
#define m_GOLDMONT (HOST_WIDE_INT_1U<<PROCESSOR_GOLDMONT)
#define m_GOLDMONT_PLUS (HOST_WIDE_INT_1U<<PROCESSOR_GOLDMONT_PLUS)
#define m_TREMONT (HOST_WIDE_INT_1U<<PROCESSOR_TREMONT)
&alderlake_cost, /* PROCESSOR_ARROWLAKE_S. */
&alderlake_cost, /* PROCESSOR_PANTHERLAKE. */
&icelake_cost, /* PROCESSOR_DIAMONDRAPIDS. */
+ &alderlake_cost, /* PROCESSOR_NOVALAKE. */
&alderlake_cost, /* PROCESSOR_INTEL. */
&lujiazui_cost, /* PROCESSOR_LUJIAZUI. */
&yongfeng_cost, /* PROCESSOR_YONGFENG. */
PROCESSOR_ARROWLAKE_S,
PROCESSOR_PANTHERLAKE,
PROCESSOR_DIAMONDRAPIDS,
+ PROCESSOR_NOVALAKE,
PROCESSOR_INTEL,
PROCESSOR_LUJIAZUI,
PROCESSOR_YONGFENG,
| PTA_CMPCCXADD | PTA_SHA512 | PTA_SM3 | PTA_SM4 | PTA_AVX10_2
| PTA_APX_F | PTA_AMX_AVX512 | PTA_AMX_FP8 | PTA_AMX_TF32 | PTA_MOVRS
| PTA_AMX_MOVRS;
+constexpr wide_int_bitmask PTA_NOVALAKE = PTA_PANTHERLAKE | PTA_PREFETCHI;
constexpr wide_int_bitmask PTA_BDVER1 = PTA_64BIT | PTA_MMX | PTA_SSE
| PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_POPCNT | PTA_LZCNT
@item diamondrapids
Intel Core i7 Diamond Rapids CPU.
+@item novalake
+Intel Core i7 Nova Lake CPU.
+
@item bonnell
Intel Atom Bonnell CPU.
AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, SHA512, SM3 and
SM4 instruction set support.
+@item novalake
+Intel Nova Lake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
+SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC,
+XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, MOVDIRI,
+MOVDIR64B, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT, PCONFIG, PKU,
+VAES, VPCLMULQDQ, SERIALIZE, HRESET, AVX-VNNI, UINTR, AVXIFMA, AVXVNNIINT8,
+AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, SHA512, SM3, SM4 and PREFETCHI
+instruction set support.
+
@item sapphirerapids
@itemx emeraldrapids
Intel Sapphire Rapids/Emerald Rapids CPU with 64-bit extensions, MMX, SSE,
return 33;
}
+int __attribute__ ((target("arch=novalake"))) foo () {
+ return 34;
+}
+
int main ()
{
int val = foo ();
assert (val == 32);
else if (__builtin_cpu_is ("diamondrapids"))
assert (val == 33);
+ else if (__builtin_cpu_is ("novalake"))
+ assert (val == 34);
else
assert (val == 0);
extern void test_arch_arrowlake_s (void) __attribute__((__target__("arch=arrowlake-s")));
extern void test_arch_pantherlake (void) __attribute__((__target__("arch=pantherlake")));
extern void test_arch_diamondrapids (void) __attribute__((__target__("arch=diamondrapids")));
+extern void test_arch_novalake (void) __attribute__((__target__("arch=novalake")));
extern void test_arch_lujiazui (void) __attribute__((__target__("arch=lujiazui")));
extern void test_arch_yongfeng (void) __attribute__((__target__("arch=yongfeng")));
extern void test_arch_shijidadao (void) __attribute__((__target__("arch=shijidadao")));