clk: qcom: a53: Corrected frequency multiplier for 1152MHz

The 1152MHz frequency entry for the a53 currently selects a multiplier of 62, giving 1190MHz. This changes the mulitiplier to 60 giving the intended 1152MHz.

Signed-off-by: Phillip Varney <pbvarney@protonmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Fixes: 0c6ab1b8f894 ("clk: qcom: Add A53 PLL support")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260605005502.313928-1-pbvarney@protonmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/drivers/clk/qcom/a53-pll.c b/drivers/clk/qcom/a53-pll.c
index 724a642311e50bdf470647d0661ef33c9c037809..0549b214fcfc8ba812205cead1e3d3fc38ca5254 100644 (file)
--- a/drivers/clk/qcom/a53-pll.c
+++ b/drivers/clk/qcom/a53-pll.c
@@ -20,7 +20,7 @@
 static const struct pll_freq_tbl a53pll_freq[] = {
        {  998400000, 52, 0x0, 0x1, 0 },
        { 1094400000, 57, 0x0, 0x1, 0 },
-       { 1152000000, 62, 0x0, 0x1, 0 },
+       { 1152000000, 60, 0x0, 0x1, 0 },
        { 1209600000, 63, 0x0, 0x1, 0 },
        { 1248000000, 65, 0x0, 0x1, 0 },
        { 1363200000, 71, 0x0, 0x1, 0 },