guest_next = 0;
resteerOK
- = n_instrs < vex_control.guest_chase_thresh
- /* we can't afford to have a resteer once we're on the last
- extent slot. */
- && vge->n_used < 3;
+ = toBool(
+ n_instrs < vex_control.guest_chase_thresh
+ /* we can't afford to have a resteer once we're on the
+ last extent slot. */
+ && vge->n_used < 3
+ );
first_stmt_idx = irbb->stmts_used;
/* Bomb out if we can't handle something. */
__attribute__ ((noreturn))
-static void unimplemented ( Char* str )
+static void unimplemented ( HChar* str )
{
vex_printf("x86toIR: unimplemented feature\n");
vpanic(str);
where YYY is the register number. */
static Bool epartIsReg ( UChar mod_reg_rm )
{
- return (0xC0 == (mod_reg_rm & 0xC0));
+ return toBool(0xC0 == (mod_reg_rm & 0xC0));
}
/* ... and extract the register number ... */
/* Get a 8/16/32-bit unsigned value out of the insn stream. */
-static UInt getUChar ( UInt delta )
+static UChar getUChar ( UInt delta )
{
- UInt v = guest_code[delta+0];
+ UChar v = guest_code[delta+0];
return v & 0xFF;
}
switch (size) {
case 4: return getUDisp32(delta);
case 2: return getUDisp16(delta);
- case 1: return getUChar(delta);
+ case 1: return (UInt)getUChar(delta);
default: vpanic("getUDisp(x86)");
}
return 0; /*notreached*/
static IRExpr* mkU8 ( UInt i )
{
vassert(i < 256);
- return IRExpr_Const(IRConst_U8(i));
+ return IRExpr_Const(IRConst_U8( (UChar)i ));
}
static IRExpr* mkU16 ( UInt i )
{
vassert(i < 65536);
- return IRExpr_Const(IRConst_U16(i));
+ return IRExpr_Const(IRConst_U16( (UShort)i ));
}
static IRExpr* mkU32 ( UInt i )
static Bool isAddSub ( IROp op8 )
{
- return op8 == Iop_Add8 || op8 == Iop_Sub8;
+ return toBool(op8 == Iop_Add8 || op8 == Iop_Sub8);
}
static Bool isLogic ( IROp op8 )
{
- return op8 == Iop_And8 || op8 == Iop_Or8 || op8 == Iop_Xor8;
+ return toBool(op8 == Iop_And8 || op8 == Iop_Or8 || op8 == Iop_Xor8);
}
/* U-widen 8/16/32 bit int expr to 32. */
/* Condition codes, using the Intel encoding. */
-static Char* name_X86Condcode ( X86Condcode cond )
+static HChar* name_X86Condcode ( X86Condcode cond )
{
switch (cond) {
case X86CondO: return "o";
return xmm_names[xmmreg];
}
-static Char* nameMMXGran ( UChar gran )
+static HChar* nameMMXGran ( Int gran )
{
switch (gran) {
case 0: return "b";
}
}
-static Char nameISize ( Int size )
+static HChar nameISize ( Int size )
{
switch (size) {
case 4: return 'l';
/*------------------------------------------------------------*/
static
-UChar* sorbTxt ( UChar sorb )
+HChar* sorbTxt ( UChar sorb )
{
switch (sorb) {
case 0: return ""; /* no override */
}
static
-IRTemp disAMode ( Int* len, UChar sorb, UInt delta, UChar* buf )
+IRTemp disAMode ( Int* len, UChar sorb, UInt delta, HChar* buf )
{
UChar mod_reg_rm = getIByte(delta);
delta++;
/* ! 0C */ case 0x0D: case 0x0E: case 0x0F:
{ UChar rm = mod_reg_rm & 7;
UInt d = getSDisp8(delta);
- DIS(buf, "%s%d(%s)", sorbTxt(sorb), d, nameIReg(4,rm));
+ DIS(buf, "%s%d(%s)", sorbTxt(sorb), (Int)d, nameIReg(4,rm));
*len = 2;
return disAMode_copy2tmp(
handleSegOverride(sorb,
/* ! 14 */ case 0x15: case 0x16: case 0x17:
{ UChar rm = mod_reg_rm & 7;
UInt d = getUDisp32(delta);
- DIS(buf, "%s0x%x(%s)", sorbTxt(sorb), d, nameIReg(4,rm));
+ DIS(buf, "%s0x%x(%s)", sorbTxt(sorb), (Int)d, nameIReg(4,rm));
*len = 5;
return disAMode_copy2tmp(
handleSegOverride(sorb,
UInt d = getSDisp8(delta+1);
if (index_r == R_ESP) {
- DIS(buf, "%s%d(%s,,)", sorbTxt(sorb), d, nameIReg(4,base_r));
+ DIS(buf, "%s%d(%s,,)", sorbTxt(sorb),
+ (Int)d, nameIReg(4,base_r));
*len = 3;
return disAMode_copy2tmp(
handleSegOverride(sorb,
binop(Iop_Add32, getIReg(4,base_r), mkU32(d)) ));
} else {
- DIS(buf, "%s%d(%s,%s,%d)", sorbTxt(sorb), d,
+ DIS(buf, "%s%d(%s,%s,%d)", sorbTxt(sorb), (Int)d,
nameIReg(4,base_r), nameIReg(4,index_r), 1<<scale);
*len = 3;
return
UInt d = getUDisp32(delta+1);
if (index_r == R_ESP) {
- DIS(buf, "%s%d(%s,,)", sorbTxt(sorb), d, nameIReg(4,base_r));
+ DIS(buf, "%s%d(%s,,)", sorbTxt(sorb),
+ (Int)d, nameIReg(4,base_r));
*len = 6;
return disAMode_copy2tmp(
handleSegOverride(sorb,
binop(Iop_Add32, getIReg(4,base_r), mkU32(d)) ));
} else {
- DIS(buf, "%s%d(%s,%s,%d)", sorbTxt(sorb), d,
- nameIReg(4,base_r), nameIReg(4,index_r), 1<<scale);
+ DIS(buf, "%s%d(%s,%s,%d)", sorbTxt(sorb), (Int)d,
+ nameIReg(4,base_r), nameIReg(4,index_r), 1<<scale);
*len = 6;
return
disAMode_copy2tmp(
Bool keep,
Int size,
UInt delta0,
- Char* t_x86opc )
+ HChar* t_x86opc )
{
HChar dis_buf[50];
Int len;
Bool keep,
Int size,
UInt delta0,
- Char* t_x86opc )
+ HChar* t_x86opc )
{
HChar dis_buf[50];
Int len;
IROp op8,
Bool keep,
UInt delta,
- Char* t_x86opc )
+ HChar* t_x86opc )
{
IRType ty = szToITy(size);
IRTemp dst0 = newTemp(ty);
UInt dis_Grp2 ( UChar sorb,
UInt delta, UChar modrm,
Int am_sz, Int d_sz, Int sz, IRExpr* shift_expr,
- Char* shift_expr_txt )
+ HChar* shift_expr_txt )
{
/* delta on entry points at the modrm byte. */
HChar dis_buf[50];
isRotate = False;
switch (gregOfRM(modrm)) { case 0: case 1: isRotate = True; }
- isRotateRC = gregOfRM(modrm) == 3;
+ isRotateRC = toBool(gregOfRM(modrm) == 3);
if (!isShift && !isRotate && !isRotateRC) {
vex_printf("\ncase %d\n", gregOfRM(modrm));
else
if (isRotate) {
Int ccOp = ty==Ity_I8 ? 0 : (ty==Ity_I16 ? 1 : 2);
- Bool left = gregOfRM(modrm) == 0;
+ Bool left = toBool(gregOfRM(modrm) == 0);
IRTemp rot_amt = newTemp(Ity_I8);
IRTemp rot_amt32 = newTemp(Ity_I8);
IRTemp oldFlags = newTemp(Ity_I32);
EDX:EAX/DX:AX/AX.
*/
static void codegen_mulL_A_D ( Int sz, Bool syned,
- IRTemp tmp, Char* tmp_txt )
+ IRTemp tmp, HChar* tmp_txt )
{
IRType ty = szToITy(sz);
IRTemp t1 = newTemp(ty);
break;
default:
vex_printf(
- "unhandled Grp3(R) case %d\n", (UInt)gregOfRM(modrm));
+ "unhandled Grp3(R) case %d\n", (Int)gregOfRM(modrm));
vpanic("Grp3(x86)");
}
} else {
break;
default:
vex_printf(
- "unhandled Grp3(M) case %d\n", (UInt)gregOfRM(modrm));
+ "unhandled Grp3(M) case %d\n", (Int)gregOfRM(modrm));
vpanic("Grp3(x86)");
}
}
break;
default:
vex_printf(
- "unhandled Grp4(R) case %d\n", (UInt)gregOfRM(modrm));
+ "unhandled Grp4(R) case %d\n", (Int)gregOfRM(modrm));
vpanic("Grp4(x86,R)");
}
delta++;
break;
default:
vex_printf(
- "unhandled Grp4(M) case %d\n", (UInt)gregOfRM(modrm));
+ "unhandled Grp4(M) case %d\n", (Int)gregOfRM(modrm));
vpanic("Grp4(x86,M)");
}
delta += alen;
break;
default:
vex_printf(
- "unhandled Grp5(R) case %d\n", (UInt)gregOfRM(modrm));
+ "unhandled Grp5(R) case %d\n", (Int)gregOfRM(modrm));
vpanic("Grp5(x86)");
}
delta++;
break;
default:
vex_printf(
- "unhandled Grp5(M) case %d\n", (UInt)gregOfRM(modrm));
+ "unhandled Grp5(M) case %d\n", (Int)gregOfRM(modrm));
vpanic("Grp5(x86)");
}
delta += len;
static
void dis_string_op( void (*dis_OP)( Int, IRTemp ),
- Int sz, Char* name, UChar sorb )
+ Int sz, HChar* name, UChar sorb )
{
IRTemp t_inc = newTemp(Ity_I32);
vassert(sorb == 0);
static
void dis_REP_op ( X86Condcode cond,
void (*dis_OP)(Int, IRTemp),
- Int sz, Addr32 eip, Addr32 eip_next, Char* name )
+ Int sz, Addr32 eip, Addr32 eip_next, HChar* name )
{
IRTemp t_inc = newTemp(Ity_I32);
IRTemp tc = newTemp(Ity_I32); /* ECX */
Need to check ST(0)'s tag on read, but not on write.
*/
static
-void fp_do_op_mem_ST_0 ( IRTemp addr, UChar* op_txt, UChar* dis_buf,
+void fp_do_op_mem_ST_0 ( IRTemp addr, HChar* op_txt, HChar* dis_buf,
IROp op, Bool dbl )
{
DIP("f%s%c %s\n", op_txt, dbl?'l':'s', dis_buf);
Need to check ST(0)'s tag on read, but not on write.
*/
static
-void fp_do_oprev_mem_ST_0 ( IRTemp addr, UChar* op_txt, UChar* dis_buf,
+void fp_do_oprev_mem_ST_0 ( IRTemp addr, HChar* op_txt, HChar* dis_buf,
IROp op, Bool dbl )
{
DIP("f%s%c %s\n", op_txt, dbl?'l':'s', dis_buf);
Check dst and src tags when reading but not on write.
*/
static
-void fp_do_op_ST_ST ( UChar* op_txt, IROp op, UInt st_src, UInt st_dst,
+void fp_do_op_ST_ST ( HChar* op_txt, IROp op, UInt st_src, UInt st_dst,
Bool pop_after )
{
- DIP("f%s%s st(%d), st(%d)\n", op_txt, pop_after?"p":"", st_src, st_dst );
+ DIP("f%s%s st(%d), st(%d)\n", op_txt, pop_after?"p":"",
+ (Int)st_src, (Int)st_dst );
put_ST_UNCHECKED(
st_dst,
binop(op, get_ST(st_dst), get_ST(st_src) )
Check dst and src tags when reading but not on write.
*/
static
-void fp_do_oprev_ST_ST ( UChar* op_txt, IROp op, UInt st_src, UInt st_dst,
+void fp_do_oprev_ST_ST ( HChar* op_txt, IROp op, UInt st_src, UInt st_dst,
Bool pop_after )
{
- DIP("f%s%s st(%d), st(%d)\n", op_txt, pop_after?"p":"", st_src, st_dst );
+ DIP("f%s%s st(%d), st(%d)\n", op_txt, pop_after?"p":"",
+ (Int)st_src, (Int)st_dst );
put_ST_UNCHECKED(
st_dst,
binop(op, get_ST(st_src), get_ST(st_dst) )
/* %eflags(Z,P,C) = UCOMI( st(0), st(i) ) */
static void fp_do_ucomi_ST0_STi ( UInt i, Bool pop_after )
{
- DIP("fucomi%s %%st(0),%%st(%d)\n", pop_after ? "p" : "", i);
+ DIP("fucomi%s %%st(0),%%st(%d)\n", pop_after ? "p" : "", (Int)i );
/* This is a bit of a hack (and isn't really right). It sets
Z,P,C,O correctly, but forces A and S to zero, whereas the Intel
documentation implies A and S are unchanged.
fp_do_op_ST_ST ( "mul", Iop_MulF64, modrm - 0xC8, 0, False );
break;
-#if 1
/* Dunno if this is right */
case 0xD0 ... 0xD7: /* FCOM %st(?),%st(0) */
r_dst = (UInt)modrm - 0xD0;
- DIP("fcom %%st(0),%%st(%d)\n", r_dst);
+ DIP("fcom %%st(0),%%st(%d)\n", (Int)r_dst);
/* This forces C1 to zero, which isn't right. */
put_C3210(
binop( Iop_And32,
mkU32(0x4500)
));
break;
-#endif
-#if 1
+
/* Dunno if this is right */
case 0xD8 ... 0xDF: /* FCOMP %st(?),%st(0) */
r_dst = (UInt)modrm - 0xD8;
- DIP("fcomp %%st(0),%%st(%d)\n", r_dst);
+ DIP("fcomp %%st(0),%%st(%d)\n", (Int)r_dst);
/* This forces C1 to zero, which isn't right. */
put_C3210(
binop( Iop_And32,
));
fp_pop();
break;
-#endif
+
case 0xE0 ... 0xE7: /* FSUB %st(?),%st(0) */
fp_do_op_ST_ST ( "sub", Iop_SubF64, modrm - 0xE0, 0, False );
break;
case 0xC0 ... 0xC7: /* FLD %st(?) */
r_src = (UInt)modrm - 0xC0;
- DIP("fld %%st(%d)\n", r_src);
+ DIP("fld %%st(%d)\n", (Int)r_src);
t1 = newTemp(Ity_F64);
assign(t1, get_ST(r_src));
fp_push();
case 0xC8 ... 0xCF: /* FXCH %st(?) */
r_src = (UInt)modrm - 0xC8;
- DIP("fxch %%st(%d)\n", r_src);
+ DIP("fxch %%st(%d)\n", (Int)r_src);
t1 = newTemp(Ity_F64);
t2 = newTemp(Ity_F64);
assign(t1, get_ST(0));
case 0xC0 ... 0xC7: /* FCMOVB ST(i), ST(0) */
r_src = (UInt)modrm - 0xC0;
- DIP("fcmovb %%st(%d), %%st(0)\n", r_src);
+ DIP("fcmovb %%st(%d), %%st(0)\n", (Int)r_src);
put_ST_UNCHECKED(0,
IRExpr_Mux0X(
unop(Iop_1Uto8,
case 0xC8 ... 0xCF: /* FCMOVE(Z) ST(i), ST(0) */
r_src = (UInt)modrm - 0xC8;
- DIP("fcmovz %%st(%d), %%st(0)\n", r_src);
+ DIP("fcmovz %%st(%d), %%st(0)\n", (Int)r_src);
put_ST_UNCHECKED(0,
IRExpr_Mux0X(
unop(Iop_1Uto8,
case 0xD0 ... 0xD7: /* FCMOVBE ST(i), ST(0) */
r_src = (UInt)modrm - 0xD0;
- DIP("fcmovbe %%st(%d), %%st(0)\n", r_src);
+ DIP("fcmovbe %%st(%d), %%st(0)\n", (Int)r_src);
put_ST_UNCHECKED(0,
IRExpr_Mux0X(
unop(Iop_1Uto8,
case 0xC0 ... 0xC7: /* FCMOVNB ST(i), ST(0) */
r_src = (UInt)modrm - 0xC0;
- DIP("fcmovnb %%st(%d), %%st(0)\n", r_src);
+ DIP("fcmovnb %%st(%d), %%st(0)\n", (Int)r_src);
put_ST_UNCHECKED(0,
IRExpr_Mux0X(
unop(Iop_1Uto8,
case 0xC8 ... 0xCF: /* FCMOVNE(NZ) ST(i), ST(0) */
r_src = (UInt)modrm - 0xC8;
- DIP("fcmovnz %%st(%d), %%st(0)\n", r_src);
+ DIP("fcmovnz %%st(%d), %%st(0)\n", (Int)r_src);
put_ST_UNCHECKED(0,
IRExpr_Mux0X(
unop(Iop_1Uto8,
case 0xD0 ... 0xD7: /* FCMOVNBE ST(i), ST(0) */
r_src = (UInt)modrm - 0xD0;
- DIP("fcmovnbe %%st(%d), %%st(0)\n", r_src);
+ DIP("fcmovnbe %%st(%d), %%st(0)\n", (Int)r_src);
put_ST_UNCHECKED(0,
IRExpr_Mux0X(
unop(Iop_1Uto8,
case 0xD0 ... 0xD7: /* FST %st(0),%st(?) */
r_dst = (UInt)modrm - 0xD0;
- DIP("fst %%st(0),%%st(%d)\n", r_dst);
+ DIP("fst %%st(0),%%st(%d)\n", (Int)r_dst);
/* P4 manual says: "If the destination operand is a
non-empty register, the invalid-operation exception
is not generated. Hence put_ST_UNCHECKED. */
case 0xD8 ... 0xDF: /* FSTP %st(0),%st(?) */
r_dst = (UInt)modrm - 0xD8;
- DIP("fstp %%st(0),%%st(%d)\n", r_dst);
+ DIP("fstp %%st(0),%%st(%d)\n", (Int)r_dst);
/* P4 manual says: "If the destination operand is a
non-empty register, the invalid-operation exception
is not generated. Hence put_ST_UNCHECKED. */
case 0xE0 ... 0xE7: /* FUCOM %st(0),%st(?) */
r_dst = (UInt)modrm - 0xE0;
- DIP("fucom %%st(0),%%st(%d)\n", r_dst);
+ DIP("fucom %%st(0),%%st(%d)\n", (Int)r_dst);
/* This forces C1 to zero, which isn't right. */
put_C3210(
binop( Iop_And32,
case 0xE8 ... 0xEF: /* FUCOMP %st(0),%st(?) */
r_dst = (UInt)modrm - 0xE8;
- DIP("fucomp %%st(0),%%st(%d)\n", r_dst);
+ DIP("fucomp %%st(0),%%st(%d)\n", (Int)r_dst);
/* This forces C1 to zero, which isn't right. */
put_C3210(
binop( Iop_And32,
responsibility of its caller. */
static
-UInt dis_MMXop_regmem_to_reg ( UChar sorb,
- UInt delta,
- UChar opc,
- Char* name,
- Bool show_granularity )
+UInt dis_MMXop_regmem_to_reg ( UChar sorb,
+ UInt delta,
+ UChar opc,
+ HChar* name,
+ Bool show_granularity )
{
HChar dis_buf[50];
UChar modrm = getIByte(delta);
Bool invG = False;
IROp op = Iop_INVALID;
void* hAddr = NULL;
- Char* hName = NULL;
+ HChar* hName = NULL;
Bool eLeft = False;
# define XXX(_name) do { hAddr = &_name; hName = #_name; } while (0)
putMMXReg( gregOfRM(modrm), mkexpr(res) );
DIP("%s%s %s, %s\n",
- name, show_granularity ? nameMMXGran(opc & 3) : (Char*)"",
+ name, show_granularity ? nameMMXGran(opc & 3) : "",
( isReg ? nameMMXReg(eregOfRM(modrm)) : dis_buf ),
nameMMXReg(gregOfRM(modrm)) );
vassert(epartIsReg(rm));
vassert(gregOfRM(rm) == 2
|| gregOfRM(rm) == 4 || gregOfRM(rm) == 6);
- amt = (Int)(getIByte(delta+1));
+ amt = getIByte(delta+1);
delta += 2;
DIP("%s $%d,%s\n", opname,
(Int)amt,
Int sz,
IRExpr* shift_amt,
Bool amt_is_literal,
- Char* shift_amt_txt,
+ HChar* shift_amt_txt,
Bool left_shift )
{
/* shift_amt :: Ity_I8 is the amount to shift. shift_amt_txt is used
typedef enum { BtOpNone, BtOpSet, BtOpReset, BtOpComp } BtOp;
-static Char* nameBtOp ( BtOp op )
+static HChar* nameBtOp ( BtOp op )
{
switch (op) {
case BtOpNone: return "";
vassert(epartIsReg(rm));
vassert(gregOfRM(rm) == 2
|| gregOfRM(rm) == 4 || gregOfRM(rm) == 6);
- amt = (Int)(getIByte(delta+1));
+ amt = getIByte(delta+1);
delta += 2;
DIP("%s $%d,%s\n", opname,
(Int)amt,
IRTemp rmode = newTemp(Ity_I32);
IRTemp f32lo = newTemp(Ity_F32);
IRTemp f32hi = newTemp(Ity_F32);
- Bool r2zero = insn[1] == 0x2C;
+ Bool r2zero = toBool(insn[1] == 0x2C);
do_MMX_preamble();
modrm = getIByte(delta+2);
&& (insn[2] == 0x2D || insn[2] == 0x2C)) {
IRTemp rmode = newTemp(Ity_I32);
IRTemp f32lo = newTemp(Ity_F32);
- Bool r2zero = insn[2] == 0x2C;
+ Bool r2zero = toBool(insn[2] == 0x2C);
vassert(sz == 4);
modrm = getIByte(delta+3);
if (sz == 4 && insn[0] == 0x0F && (insn[1] == 0x15 || insn[1] == 0x14)) {
IRTemp sV, dV;
IRTemp s3, s2, s1, s0, d3, d2, d1, d0;
- Bool hi = insn[1] == 0x15;
+ Bool hi = toBool(insn[1] == 0x15);
sV = newTemp(Ity_V128);
dV = newTemp(Ity_V128);
s3 = s2 = s1 = s0 = d3 = d2 = d1 = d0 = IRTemp_INVALID;
IRTemp rmode = newTemp(Ity_I32);
IRTemp f64lo = newTemp(Ity_F64);
IRTemp f64hi = newTemp(Ity_F64);
- Bool r2zero = insn[1] == 0x2C;
+ Bool r2zero = toBool(insn[1] == 0x2C);
do_MMX_preamble();
modrm = getIByte(delta+2);
&& (insn[2] == 0x2D || insn[2] == 0x2C)) {
IRTemp rmode = newTemp(Ity_I32);
IRTemp f64lo = newTemp(Ity_F64);
- Bool r2zero = insn[2] == 0x2C;
+ Bool r2zero = toBool(insn[2] == 0x2C);
vassert(sz == 4);
modrm = getIByte(delta+3);
IRTemp d0 = newTemp(Ity_I64);
IRTemp sV = newTemp(Ity_V128);
IRTemp dV = newTemp(Ity_V128);
- Bool hi = insn[1] == 0x15;
+ Bool hi = toBool(insn[1] == 0x15);
modrm = insn[2];
assign( dV, getXMMReg(gregOfRM(modrm)) );
delta += 2;
dis_ret(d32);
whatNext = Dis_StopHere;
- DIP("ret %d\n", d32);
+ DIP("ret %d\n", (Int)d32);
break;
case 0xC3: /* RET */
dis_ret(0);
case 0xA4: /* SHLDv imm8,Gv,Ev */
modrm = getIByte(delta);
d32 = delta + lengthAMode(delta);
- vex_sprintf(dis_buf, "$%d", delta);
+ vex_sprintf(dis_buf, "$%d", getIByte(d32));
delta = dis_SHLRD_Gv_Ev (
sorb, delta, modrm, sz,
mkU8(getIByte(d32)), True, /* literal */
case 0xAC: /* SHRDv imm8,Gv,Ev */
modrm = getIByte(delta);
d32 = delta + lengthAMode(delta);
- vex_sprintf(dis_buf, "$%d", delta);
+ vex_sprintf(dis_buf, "$%d", getIByte(d32));
delta = dis_SHLRD_Gv_Ev (
sorb, delta, modrm, sz,
mkU8(getIByte(d32)), True, /* literal */
projects / thirdparty / valgrind.git / commitdiff
