]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
arm64: dts: qcom: monaco: correct Iris corners for the MXC rail
authorDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Fri, 13 Mar 2026 15:27:10 +0000 (17:27 +0200)
committerBjorn Andersson <andersson@kernel.org>
Thu, 26 Mar 2026 14:40:38 +0000 (09:40 -0500)
The corners of the MVS0 / MVS0C clocks on the MMCX rail don't always
match the PLL corners on the MXC rail. Correct the performance corners
for the MXC rail following the PLL documentation.

Fixes: bf6ec39c3f36 ("arm64: dts: qcom: qcs8300: add video node")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260313-iris-fix-corners-v1-3-32a393c25dda@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
arch/arm64/boot/dts/qcom/monaco.dtsi

index 2ac600854fb3daec3b183ec314b30373fe30efff..0fd3168d0f62bdc5a7c042b33fc9971cf2b85cf4 100644 (file)
 
                                opp-444000000 {
                                        opp-hz = /bits/ 64 <444000000>;
-                                       required-opps = <&rpmhpd_opp_nom>,
+                                       required-opps = <&rpmhpd_opp_svs_l1>,
                                                        <&rpmhpd_opp_nom>;
                                };
 
                                opp-533000000 {
                                        opp-hz = /bits/ 64 <533000000>;
-                                       required-opps = <&rpmhpd_opp_turbo>,
+                                       required-opps = <&rpmhpd_opp_nom>,
                                                        <&rpmhpd_opp_turbo>;
                                };
 
                                opp-560000000 {
                                        opp-hz = /bits/ 64 <560000000>;
-                                       required-opps = <&rpmhpd_opp_turbo_l1>,
+                                       required-opps = <&rpmhpd_opp_nom>,
                                                        <&rpmhpd_opp_turbo_l1>;
                                };
                        };