+++ /dev/null
-From foo@baz Mon Apr 10 18:08:16 CEST 2017
-From: alexander.levin@verizon.com
-Date: Tue, 4 Apr 2017 19:32:20 +0000
-Subject: ARM: OMAP2+: Fix init for multiple quirks for the same SoC
-To: "gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>
-Cc: "stable@vger.kernel.org" <stable@vger.kernel.org>
-Message-ID: <20170404193158.19041-51-alexander.levin@verizon.com>
-
-From: Tony Lindgren <tony@atomide.com>
-
-[ Upstream commit 6e613ebf4405fc09e2a8c16ed193b47f80a3cbed ]
-
-It's possible that there are multiple quirks that need to be initialized
-for the same SoC. Fix the issue by not returning on the first match.
-
-Signed-off-by: Tony Lindgren <tony@atomide.com>
-Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- arch/arm/mach-omap2/pdata-quirks.c | 1 -
- 1 file changed, 1 deletion(-)
-
---- a/arch/arm/mach-omap2/pdata-quirks.c
-+++ b/arch/arm/mach-omap2/pdata-quirks.c
-@@ -599,7 +599,6 @@ static void pdata_quirks_check(struct pd
- if (of_machine_is_compatible(quirks->compatible)) {
- if (quirks->fn)
- quirks->fn();
-- break;
- }
- quirks++;
- }
+++ /dev/null
-From foo@baz Mon Apr 10 18:08:16 CEST 2017
-From: alexander.levin@verizon.com
-Date: Tue, 4 Apr 2017 19:32:26 +0000
-Subject: [media] rx51: broken build
-To: "gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>
-Cc: "stable@vger.kernel.org" <stable@vger.kernel.org>
-Message-ID: <20170404193158.19041-67-alexander.levin@verizon.com>
-
-From: Sean Young <sean@mess.org>
-
-[ Upstream commit 922ee72da7c739157ed02ea04a5c100d19f67226 ]
-
-As reported by kernel build test:
-
- In file included from arch/arm/mach-omap2/pdata-quirks.c:15:0:
->> arch/arm/mach-omap2/pdata-quirks.c:536:49: error: 'rx51_lirc_data' undeclared here (not in a function)
- OF_DEV_AUXDATA("nokia,n900-ir", 0, "n900-ir", &rx51_lirc_data),
- ^
- include/linux/of_platform.h:52:21: note: in definition of macro 'OF_DEV_AUXDATA'
- .platform_data = _pdata }
- ^~~~~~
-
-Since "a92def1 [media] ir-rx51: port to rc-core" the build fails on
-some arm configurations.
-
-Reported-by: kbuild test robot <fengguang.wu@intel.com>
-Signed-off-by: Sean Young <sean@mess.org>
-Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
-Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- arch/arm/mach-omap2/pdata-quirks.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm/mach-omap2/pdata-quirks.c
-+++ b/arch/arm/mach-omap2/pdata-quirks.c
-@@ -533,7 +533,7 @@ static struct of_dev_auxdata omap_auxdat
- &omap3_iommu_pdata),
- OF_DEV_AUXDATA("ti,omap3-hsmmc", 0x4809c000, "4809c000.mmc", &mmc_pdata[0]),
- OF_DEV_AUXDATA("ti,omap3-hsmmc", 0x480b4000, "480b4000.mmc", &mmc_pdata[1]),
-- OF_DEV_AUXDATA("nokia,n900-ir", 0, "n900-ir", &rx51_lirc_data),
-+ OF_DEV_AUXDATA("nokia,n900-ir", 0, "n900-ir", &rx51_ir_data),
- /* Only on am3517 */
- OF_DEV_AUXDATA("ti,davinci_mdio", 0x5c030000, "davinci_mdio.0", NULL),
- OF_DEV_AUXDATA("ti,am3517-emac", 0x5c000000, "davinci_emac.0",
drm-i915-more-.is_mobile-cleanups-for-bdw.patch
drm-i915-actually-drive-the-bdw-reserved-ids.patch
asoc-intel-bytcr_rt5640-quirks-for-insyde-devices.patch
-arm-omap2-fix-init-for-multiple-quirks-for-the-same-soc.patch
usb-chipidea-msm-rely-on-core-to-override-ahbburst.patch
serial-8250_omap-add-omap_dma_tx_kick-quirk-for-am437x.patch
arm-davinci-add-skeleton-for-pdata-quirks.patch
drm-mga-remove-device_is_agp-callback.patch
pci-add-acs-quirk-for-intel-union-point.patch
pci-xgene-fix-double-free-on-init-error.patch
-rx51-broken-build.patch
sata-ahci-da850-implement-a-workaround-for-the-softreset-quirk.patch
acpi-button-change-default-behavior-to-lid_init_state-open.patch
asoc-codecs-rt5670-add-quirk-for-lenovo-thinkpad-10.patch
asoc-intel-cht_bsw_rt5645-harden-acpi-device-detection.patch
asoc-intel-cht_bsw_rt5645-add-baytrail-mclk-support.patch
acpi-save-nvs-memory-for-lenovo-g50-45.patch
-usb-musb-da8xx-fix-host-mode-suspend.patch
asoc-sun4i-i2s-add-quirks-to-handle-a31-compatible.patch
hid-wacom-don-t-apply-generic-settings-to-old-devices.patch
arm-kernel-add-smc-structure-parameter.patch
+++ /dev/null
-From foo@baz Mon Apr 10 18:08:16 CEST 2017
-From: alexander.levin@verizon.com
-Date: Tue, 4 Apr 2017 19:32:30 +0000
-Subject: usb: musb: da8xx: Fix host mode suspend
-To: "gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>
-Cc: "stable@vger.kernel.org" <stable@vger.kernel.org>
-Message-ID: <20170404193158.19041-76-alexander.levin@verizon.com>
-
-From: Alexandre Bailon <abailon@baylibre.com>
-
-[ Upstream commit 486fc20ac8391338a42b015801b846acda4db7b7 ]
-
-On da8xx, VBUS is not maintained during suspend when musb is in host mode.
-On resume, all the connected devices will be disconnected and then will
-be enumerated again.
-This happens because MUSB_DEVCTL is cleared during suspend.
-
-Use the quirk MUSB_PRESERVE_SESSION to preseve MUSB_DEVCTL during suspend.
-
-Signed-off-by: Alexandre Bailon <abailon@baylibre.com>
-Signed-off-by: Bin Liu <b-liu@ti.com>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- drivers/usb/musb/da8xx.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/usb/musb/da8xx.c
-+++ b/drivers/usb/musb/da8xx.c
-@@ -458,7 +458,7 @@ static inline u8 get_vbus_power(struct d
- }
-
- static const struct musb_platform_ops da8xx_ops = {
-- .quirks = MUSB_INDEXED_EP,
-+ .quirks = MUSB_INDEXED_EP | MUSB_PRESERVE_SESSION,
- .init = da8xx_musb_init,
- .exit = da8xx_musb_exit,
-
+++ /dev/null
-From foo@baz Mon Apr 10 17:43:56 CEST 2017
-From: alexander.levin@verizon.com
-Date: Tue, 4 Apr 2017 19:32:20 +0000
-Subject: ARM: OMAP2+: Fix init for multiple quirks for the same SoC
-To: "gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>
-Cc: "stable@vger.kernel.org" <stable@vger.kernel.org>
-Message-ID: <20170404193158.19041-51-alexander.levin@verizon.com>
-
-From: Tony Lindgren <tony@atomide.com>
-
-[ Upstream commit 6e613ebf4405fc09e2a8c16ed193b47f80a3cbed ]
-
-It's possible that there are multiple quirks that need to be initialized
-for the same SoC. Fix the issue by not returning on the first match.
-
-Signed-off-by: Tony Lindgren <tony@atomide.com>
-Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- arch/arm/mach-omap2/pdata-quirks.c | 1 -
- 1 file changed, 1 deletion(-)
-
---- a/arch/arm/mach-omap2/pdata-quirks.c
-+++ b/arch/arm/mach-omap2/pdata-quirks.c
-@@ -600,7 +600,6 @@ static void pdata_quirks_check(struct pd
- if (of_machine_is_compatible(quirks->compatible)) {
- if (quirks->fn)
- quirks->fn();
-- break;
- }
- quirks++;
- }
+++ /dev/null
-From foo@baz Mon Apr 10 17:43:56 CEST 2017
-From: alexander.levin@verizon.com
-Date: Tue, 4 Apr 2017 19:32:09 +0000
-Subject: arm64: PCI: Search ACPI namespace to ensure ECAM space is reserved
-To: "gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>
-Cc: "stable@vger.kernel.org" <stable@vger.kernel.org>
-Message-ID: <20170404193158.19041-21-alexander.levin@verizon.com>
-
-From: Bjorn Helgaas <bhelgaas@google.com>
-
-[ Upstream commit 08b1c19606b5fc7f895dae4d43d507b4da4a83bf ]
-
-The static MCFG table tells us the base of ECAM space, but it does not
-reserve the space -- the reservation should be done via a device in the
-ACPI namespace whose _CRS includes the ECAM region.
-
-Use acpi_resource_consumer() to check whether the ECAM space is reserved by
-an ACPI namespace device. If it is, emit a message showing which device
-reserves it. If not, emit a "[Firmware Bug]" warning.
-
-Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
-Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- arch/arm64/kernel/pci.c | 12 +++++++++++-
- 1 file changed, 11 insertions(+), 1 deletion(-)
-
---- a/arch/arm64/kernel/pci.c
-+++ b/arch/arm64/kernel/pci.c
-@@ -124,8 +124,9 @@ pci_acpi_setup_ecam_mapping(struct acpi_
- struct device *dev = &root->device->dev;
- struct resource *bus_res = &root->secondary;
- u16 seg = root->segment;
-- struct pci_config_window *cfg;
- struct resource cfgres;
-+ struct acpi_device *adev;
-+ struct pci_config_window *cfg;
- unsigned int bsz;
-
- /* Use address from _CBA if present, otherwise lookup MCFG */
-@@ -141,6 +142,15 @@ pci_acpi_setup_ecam_mapping(struct acpi_
- cfgres.start = root->mcfg_addr + bus_res->start * bsz;
- cfgres.end = cfgres.start + resource_size(bus_res) * bsz - 1;
- cfgres.flags = IORESOURCE_MEM;
-+
-+ adev = acpi_resource_consumer(&cfgres);
-+ if (adev)
-+ dev_info(dev, "ECAM area %pR reserved by %s\n", &cfgres,
-+ dev_name(&adev->dev));
-+ else
-+ dev_warn(dev, FW_BUG "ECAM area %pR not reserved in ACPI namespace\n",
-+ &cfgres);
-+
- cfg = pci_ecam_create(dev, &cfgres, bus_res, &pci_generic_ecam_ops);
- if (IS_ERR(cfg)) {
- dev_err(dev, "%04x:%pR error %ld mapping ECAM\n", seg, bus_res,
+++ /dev/null
-From foo@baz Mon Apr 10 17:43:56 CEST 2017
-From: alexander.levin@verizon.com
-Date: Tue, 4 Apr 2017 19:32:10 +0000
-Subject: PCI/ACPI: Check for platform-specific MCFG quirks
-To: "gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>
-Cc: "stable@vger.kernel.org" <stable@vger.kernel.org>
-Message-ID: <20170404193158.19041-23-alexander.levin@verizon.com>
-
-From: Tomasz Nowicki <tn@semihalf.com>
-
-[ Upstream commit 5b69b85ba1ddd36be01f5c57830b37a3c8256009 ]
-
-The PCIe spec (r3.0, sec 7.2.2) specifies an "Enhanced Configuration Access
-Mechanism" (ECAM) for memory-mapped access to configuration space. ECAM is
-required for PCIe systems unless there's a standard firmware interface for
-config access.
-
-In the absence of a firmware interface, we use pci_generic_ecam_ops, and on
-ACPI systems, we discover the ECAM space via the MCFG table and/or the _CBA
-method.
-
-Unfortunately some systems provide MCFG but don't implement ECAM according
-to spec, so we need a mechanism for quirks to make those systems work.
-
-Add an MCFG quirk mechanism to override the config accessor functions
-and/or the memory-mapped address space.
-
-A quirk is selected if it matches all of the following:
-
- - OEM ID
- - OEM Table ID
- - OEM Revision
- - PCI segment (from _SEG)
- - PCI bus number range (from _CRS, wildcard allowed)
-
-If the quirk specifies config accessor functions or a memory-mapped address
-range, these override the defaults.
-
-[bhelgaas: changelog, reorder quirk matching, fix oem_revision typo per
-Duc, add under #ifdef CONFIG_PCI_QUIRKS]
-Signed-off-by: Tomasz Nowicki <tn@semihalf.com>
-Signed-off-by: Dongdong Liu <liudongdong3@huawei.com>
-Signed-off-by: Christopher Covington <cov@codeaurora.org>
-Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- drivers/acpi/pci_mcfg.c | 92 ++++++++++++++++++++++++++++++++++++++++++++----
- 1 file changed, 86 insertions(+), 6 deletions(-)
-
---- a/drivers/acpi/pci_mcfg.c
-+++ b/drivers/acpi/pci_mcfg.c
-@@ -33,6 +33,69 @@ struct mcfg_entry {
- u8 bus_end;
- };
-
-+#ifdef CONFIG_PCI_QUIRKS
-+struct mcfg_fixup {
-+ char oem_id[ACPI_OEM_ID_SIZE + 1];
-+ char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
-+ u32 oem_revision;
-+ u16 segment;
-+ struct resource bus_range;
-+ struct pci_ecam_ops *ops;
-+ struct resource cfgres;
-+};
-+
-+#define MCFG_BUS_RANGE(start, end) DEFINE_RES_NAMED((start), \
-+ ((end) - (start) + 1), \
-+ NULL, IORESOURCE_BUS)
-+#define MCFG_BUS_ANY MCFG_BUS_RANGE(0x0, 0xff)
-+
-+static struct mcfg_fixup mcfg_quirks[] = {
-+/* { OEM_ID, OEM_TABLE_ID, REV, SEGMENT, BUS_RANGE, ops, cfgres }, */
-+};
-+
-+static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
-+static char mcfg_oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
-+static u32 mcfg_oem_revision;
-+
-+static int pci_mcfg_quirk_matches(struct mcfg_fixup *f, u16 segment,
-+ struct resource *bus_range)
-+{
-+ if (!memcmp(f->oem_id, mcfg_oem_id, ACPI_OEM_ID_SIZE) &&
-+ !memcmp(f->oem_table_id, mcfg_oem_table_id,
-+ ACPI_OEM_TABLE_ID_SIZE) &&
-+ f->oem_revision == mcfg_oem_revision &&
-+ f->segment == segment &&
-+ resource_contains(&f->bus_range, bus_range))
-+ return 1;
-+
-+ return 0;
-+}
-+#endif
-+
-+static void pci_mcfg_apply_quirks(struct acpi_pci_root *root,
-+ struct resource *cfgres,
-+ struct pci_ecam_ops **ecam_ops)
-+{
-+#ifdef CONFIG_PCI_QUIRKS
-+ u16 segment = root->segment;
-+ struct resource *bus_range = &root->secondary;
-+ struct mcfg_fixup *f;
-+ int i;
-+
-+ for (i = 0, f = mcfg_quirks; i < ARRAY_SIZE(mcfg_quirks); i++, f++) {
-+ if (pci_mcfg_quirk_matches(f, segment, bus_range)) {
-+ if (f->cfgres.start)
-+ *cfgres = f->cfgres;
-+ if (f->ops)
-+ *ecam_ops = f->ops;
-+ dev_info(&root->device->dev, "MCFG quirk: ECAM at %pR for %pR with %ps\n",
-+ cfgres, bus_range, *ecam_ops);
-+ return;
-+ }
-+ }
-+#endif
-+}
-+
- /* List to save MCFG entries */
- static LIST_HEAD(pci_mcfg_list);
-
-@@ -61,14 +124,24 @@ int pci_mcfg_lookup(struct acpi_pci_root
-
- }
-
-- if (!root->mcfg_addr)
-- return -ENXIO;
--
- skip_lookup:
- memset(&res, 0, sizeof(res));
-- res.start = root->mcfg_addr + (bus_res->start << 20);
-- res.end = res.start + (resource_size(bus_res) << 20) - 1;
-- res.flags = IORESOURCE_MEM;
-+ if (root->mcfg_addr) {
-+ res.start = root->mcfg_addr + (bus_res->start << 20);
-+ res.end = res.start + (resource_size(bus_res) << 20) - 1;
-+ res.flags = IORESOURCE_MEM;
-+ }
-+
-+ /*
-+ * Allow quirks to override default ECAM ops and CFG resource
-+ * range. This may even fabricate a CFG resource range in case
-+ * MCFG does not have it. Invalid CFG start address means MCFG
-+ * firmware bug or we need another quirk in array.
-+ */
-+ pci_mcfg_apply_quirks(root, &res, &ops);
-+ if (!res.start)
-+ return -ENXIO;
-+
- *cfgres = res;
- *ecam_ops = ops;
- return 0;
-@@ -101,6 +174,13 @@ static __init int pci_mcfg_parse(struct
- list_add(&e->list, &pci_mcfg_list);
- }
-
-+#ifdef CONFIG_PCI_QUIRKS
-+ /* Save MCFG IDs and revision for quirks matching */
-+ memcpy(mcfg_oem_id, header->oem_id, ACPI_OEM_ID_SIZE);
-+ memcpy(mcfg_oem_table_id, header->oem_table_id, ACPI_OEM_TABLE_ID_SIZE);
-+ mcfg_oem_revision = header->oem_revision;
-+#endif
-+
- pr_info("MCFG table detected, %d entries\n", n);
- return 0;
- }
+++ /dev/null
-From foo@baz Mon Apr 10 17:43:56 CEST 2017
-From: alexander.levin@verizon.com
-Date: Tue, 4 Apr 2017 19:32:09 +0000
-Subject: PCI/ACPI: Extend pci_mcfg_lookup() to return ECAM config accessors
-To: "gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>
-Cc: "stable@vger.kernel.org" <stable@vger.kernel.org>
-Message-ID: <20170404193158.19041-22-alexander.levin@verizon.com>
-
-From: Tomasz Nowicki <tn@semihalf.com>
-
-[ Upstream commit 13983eb89d5afaa65acd4479fad151cbd4de5509 ]
-
-pci_mcfg_lookup() is the external interface to the generic MCFG code.
-Previously it merely looked up the ECAM base address for a given domain and
-bus range. We want a way to add MCFG quirks, some of which may require
-special config accessors and adjustments to the ECAM address range.
-
-Extend pci_mcfg_lookup() so it can return a pointer to a pci_ecam_ops
-structure and a struct resource for the ECAM address space. For now, it
-always returns &pci_generic_ecam_ops (the standard accessor) and the
-resource described by the MCFG.
-
-No functional changes intended.
-
-[bhelgaas: changelog]
-Signed-off-by: Tomasz Nowicki <tn@semihalf.com>
-Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- arch/arm64/kernel/pci.c | 17 +++++------------
- drivers/acpi/pci_mcfg.c | 28 +++++++++++++++++++++++++---
- include/linux/pci-acpi.h | 4 +++-
- 3 files changed, 33 insertions(+), 16 deletions(-)
-
---- a/arch/arm64/kernel/pci.c
-+++ b/arch/arm64/kernel/pci.c
-@@ -124,25 +124,18 @@ pci_acpi_setup_ecam_mapping(struct acpi_
- struct device *dev = &root->device->dev;
- struct resource *bus_res = &root->secondary;
- u16 seg = root->segment;
-+ struct pci_ecam_ops *ecam_ops;
- struct resource cfgres;
- struct acpi_device *adev;
- struct pci_config_window *cfg;
-- unsigned int bsz;
-+ int ret;
-
-- /* Use address from _CBA if present, otherwise lookup MCFG */
-- if (!root->mcfg_addr)
-- root->mcfg_addr = pci_mcfg_lookup(seg, bus_res);
--
-- if (!root->mcfg_addr) {
-+ ret = pci_mcfg_lookup(root, &cfgres, &ecam_ops);
-+ if (ret) {
- dev_err(dev, "%04x:%pR ECAM region not found\n", seg, bus_res);
- return NULL;
- }
-
-- bsz = 1 << pci_generic_ecam_ops.bus_shift;
-- cfgres.start = root->mcfg_addr + bus_res->start * bsz;
-- cfgres.end = cfgres.start + resource_size(bus_res) * bsz - 1;
-- cfgres.flags = IORESOURCE_MEM;
--
- adev = acpi_resource_consumer(&cfgres);
- if (adev)
- dev_info(dev, "ECAM area %pR reserved by %s\n", &cfgres,
-@@ -151,7 +144,7 @@ pci_acpi_setup_ecam_mapping(struct acpi_
- dev_warn(dev, FW_BUG "ECAM area %pR not reserved in ACPI namespace\n",
- &cfgres);
-
-- cfg = pci_ecam_create(dev, &cfgres, bus_res, &pci_generic_ecam_ops);
-+ cfg = pci_ecam_create(dev, &cfgres, bus_res, ecam_ops);
- if (IS_ERR(cfg)) {
- dev_err(dev, "%04x:%pR error %ld mapping ECAM\n", seg, bus_res,
- PTR_ERR(cfg));
---- a/drivers/acpi/pci_mcfg.c
-+++ b/drivers/acpi/pci_mcfg.c
-@@ -22,6 +22,7 @@
- #include <linux/kernel.h>
- #include <linux/pci.h>
- #include <linux/pci-acpi.h>
-+#include <linux/pci-ecam.h>
-
- /* Structure to hold entries from the MCFG table */
- struct mcfg_entry {
-@@ -35,9 +36,18 @@ struct mcfg_entry {
- /* List to save MCFG entries */
- static LIST_HEAD(pci_mcfg_list);
-
--phys_addr_t pci_mcfg_lookup(u16 seg, struct resource *bus_res)
-+int pci_mcfg_lookup(struct acpi_pci_root *root, struct resource *cfgres,
-+ struct pci_ecam_ops **ecam_ops)
- {
-+ struct pci_ecam_ops *ops = &pci_generic_ecam_ops;
-+ struct resource *bus_res = &root->secondary;
-+ u16 seg = root->segment;
- struct mcfg_entry *e;
-+ struct resource res;
-+
-+ /* Use address from _CBA if present, otherwise lookup MCFG */
-+ if (root->mcfg_addr)
-+ goto skip_lookup;
-
- /*
- * We expect exact match, unless MCFG entry end bus covers more than
-@@ -45,10 +55,22 @@ phys_addr_t pci_mcfg_lookup(u16 seg, str
- */
- list_for_each_entry(e, &pci_mcfg_list, list) {
- if (e->segment == seg && e->bus_start == bus_res->start &&
-- e->bus_end >= bus_res->end)
-- return e->addr;
-+ e->bus_end >= bus_res->end) {
-+ root->mcfg_addr = e->addr;
-+ }
-+
- }
-
-+ if (!root->mcfg_addr)
-+ return -ENXIO;
-+
-+skip_lookup:
-+ memset(&res, 0, sizeof(res));
-+ res.start = root->mcfg_addr + (bus_res->start << 20);
-+ res.end = res.start + (resource_size(bus_res) << 20) - 1;
-+ res.flags = IORESOURCE_MEM;
-+ *cfgres = res;
-+ *ecam_ops = ops;
- return 0;
- }
-
---- a/include/linux/pci-acpi.h
-+++ b/include/linux/pci-acpi.h
-@@ -24,7 +24,9 @@ static inline acpi_status pci_acpi_remov
- }
- extern phys_addr_t acpi_pci_root_get_mcfg_addr(acpi_handle handle);
-
--extern phys_addr_t pci_mcfg_lookup(u16 domain, struct resource *bus_res);
-+struct pci_ecam_ops;
-+extern int pci_mcfg_lookup(struct acpi_pci_root *root, struct resource *cfgres,
-+ struct pci_ecam_ops **ecam_ops);
-
- static inline acpi_handle acpi_find_root_bridge_handle(struct pci_dev *pdev)
- {
+++ /dev/null
-From foo@baz Mon Apr 10 17:43:56 CEST 2017
-From: alexander.levin@verizon.com
-Date: Tue, 4 Apr 2017 19:32:12 +0000
-Subject: PCI: Add MCFG quirks for Cavium ThunderX pass1.x host controller
-To: "gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>
-Cc: "stable@vger.kernel.org" <stable@vger.kernel.org>
-Message-ID: <20170404193158.19041-28-alexander.levin@verizon.com>
-
-From: Tomasz Nowicki <tn@semihalf.com>
-
-[ Upstream commit 648d93fc77da4f655cf13108417f33c91d745e2c ]
-
-ThunderX pass1.x requires to emulate the EA headers for on-chip devices
-hence it has to use custom pci_thunder_ecam_ops for accessing PCI config
-space (pci-thunder-ecam.c). Add new entries to MCFG quirk array where it
-can be applied while probing ACPI based PCI host controller.
-
-ThunderX pass1.x is using the same way for accessing off-chip devices
-(so-called PEM) as silicon pass-2.x so we need to add PEM quirk entries
-too.
-
-Quirk is considered for ThunderX silicon pass1.x only which is identified
-via MCFG revision 2.
-
-ThunderX pass 1.x requires the following accessors:
-
- NUMA node 0 PCI segments 0- 3: pci_thunder_ecam_ops (MCFG quirk)
- NUMA node 0 PCI segments 4- 9: thunder_pem_ecam_ops (MCFG quirk)
- NUMA node 1 PCI segments 10-13: pci_thunder_ecam_ops (MCFG quirk)
- NUMA node 1 PCI segments 14-19: thunder_pem_ecam_ops (MCFG quirk)
-
-[bhelgaas: change Makefile/ifdefs so quirk doesn't depend on
-CONFIG_PCI_HOST_THUNDER_ECAM]
-Signed-off-by: Tomasz Nowicki <tn@semihalf.com>
-Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- drivers/acpi/pci_mcfg.c | 15 +++++++++++++++
- drivers/pci/host/Kconfig | 3 ++-
- drivers/pci/host/Makefile | 2 +-
- drivers/pci/host/pci-thunder-ecam.c | 9 ++++++++-
- include/linux/pci-ecam.h | 3 ++-
- 5 files changed, 28 insertions(+), 4 deletions(-)
-
---- a/drivers/acpi/pci_mcfg.c
-+++ b/drivers/acpi/pci_mcfg.c
-@@ -93,6 +93,21 @@ static struct mcfg_fixup mcfg_quirks[] =
- /* SoC pass2.x */
- THUNDER_PEM_QUIRK(1, 0),
- THUNDER_PEM_QUIRK(1, 1),
-+
-+#define THUNDER_ECAM_QUIRK(rev, seg) \
-+ { "CAVIUM", "THUNDERX", rev, seg, MCFG_BUS_ANY, \
-+ &pci_thunder_ecam_ops }
-+ /* SoC pass1.x */
-+ THUNDER_PEM_QUIRK(2, 0), /* off-chip devices */
-+ THUNDER_PEM_QUIRK(2, 1), /* off-chip devices */
-+ THUNDER_ECAM_QUIRK(2, 0),
-+ THUNDER_ECAM_QUIRK(2, 1),
-+ THUNDER_ECAM_QUIRK(2, 2),
-+ THUNDER_ECAM_QUIRK(2, 3),
-+ THUNDER_ECAM_QUIRK(2, 10),
-+ THUNDER_ECAM_QUIRK(2, 11),
-+ THUNDER_ECAM_QUIRK(2, 12),
-+ THUNDER_ECAM_QUIRK(2, 13),
- };
-
- static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
---- a/drivers/pci/host/Kconfig
-+++ b/drivers/pci/host/Kconfig
-@@ -248,7 +248,8 @@ config PCI_HOST_THUNDER_PEM
-
- config PCI_HOST_THUNDER_ECAM
- bool "Cavium Thunder ECAM controller to on-chip devices on pass-1.x silicon"
-- depends on OF && ARM64
-+ depends on ARM64
-+ depends on OF || (ACPI && PCI_QUIRKS)
- select PCI_HOST_COMMON
- help
- Say Y here if you want ECAM support for CN88XX-Pass-1.x Cavium Thunder SoCs.
---- a/drivers/pci/host/Makefile
-+++ b/drivers/pci/host/Makefile
-@@ -27,7 +27,7 @@ obj-$(CONFIG_PCIE_ALTERA) += pcie-altera
- obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
- obj-$(CONFIG_ARM64) += pcie-hisi.o
- obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
--obj-$(CONFIG_PCI_HOST_THUNDER_ECAM) += pci-thunder-ecam.o
-+obj-$(CONFIG_ARM64) += pci-thunder-ecam.o
- obj-$(CONFIG_ARM64) += pci-thunder-pem.o
- obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
- obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
---- a/drivers/pci/host/pci-thunder-ecam.c
-+++ b/drivers/pci/host/pci-thunder-ecam.c
-@@ -14,6 +14,8 @@
- #include <linux/pci-ecam.h>
- #include <linux/platform_device.h>
-
-+#if defined(CONFIG_PCI_HOST_THUNDER_ECAM) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))
-+
- static void set_val(u32 v, int where, int size, u32 *val)
- {
- int shift = (where & 3) * 8;
-@@ -346,7 +348,7 @@ static int thunder_ecam_config_write(str
- return pci_generic_config_write(bus, devfn, where, size, val);
- }
-
--static struct pci_ecam_ops pci_thunder_ecam_ops = {
-+struct pci_ecam_ops pci_thunder_ecam_ops = {
- .bus_shift = 20,
- .pci_ops = {
- .map_bus = pci_ecam_map_bus,
-@@ -355,6 +357,8 @@ static struct pci_ecam_ops pci_thunder_e
- }
- };
-
-+#ifdef CONFIG_PCI_HOST_THUNDER_ECAM
-+
- static const struct of_device_id thunder_ecam_of_match[] = {
- { .compatible = "cavium,pci-host-thunder-ecam" },
- { },
-@@ -373,3 +377,6 @@ static struct platform_driver thunder_ec
- .probe = thunder_ecam_probe,
- };
- builtin_platform_driver(thunder_ecam_driver);
-+
-+#endif
-+#endif
---- a/include/linux/pci-ecam.h
-+++ b/include/linux/pci-ecam.h
-@@ -62,7 +62,8 @@ extern struct pci_ecam_ops pci_generic_e
- #if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
- extern struct pci_ecam_ops pci_32b_ops; /* 32-bit accesses only */
- extern struct pci_ecam_ops hisi_pcie_ops; /* HiSilicon */
--extern struct pci_ecam_ops thunder_pem_ecam_ops; /* Cavium ThunderX 2.x */
-+extern struct pci_ecam_ops thunder_pem_ecam_ops; /* Cavium ThunderX 1.x & 2.x */
-+extern struct pci_ecam_ops pci_thunder_ecam_ops; /* Cavium ThunderX 1.x */
- #endif
-
- #ifdef CONFIG_PCI_HOST_GENERIC
+++ /dev/null
-From foo@baz Mon Apr 10 17:43:56 CEST 2017
-From: alexander.levin@verizon.com
-Date: Tue, 4 Apr 2017 19:32:11 +0000
-Subject: PCI: Add MCFG quirks for Cavium ThunderX pass2.x host controller
-To: "gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>
-Cc: "stable@vger.kernel.org" <stable@vger.kernel.org>
-Message-ID: <20170404193158.19041-27-alexander.levin@verizon.com>
-
-From: Tomasz Nowicki <tn@semihalf.com>
-
-[ Upstream commit 44f22bd91e88f9a1203a6e564a237e593f5f2f74 ]
-
-ThunderX PCIe controller to off-chip devices (so-called PEM) is not fully
-compliant with ECAM standard. It uses non-standard configuration space
-accessors (see thunder_pem_ecam_ops) and custom configuration space
-granulation (see bus_shift = 24). In order to access configuration space
-and probe PEM as ACPI-based PCI host controller we need to add MCFG quirk
-infrastructure. This involves:
-1. A new thunder_pem_acpi_init() init function to locate PEM-specific
- register ranges using ACPI.
-2. Export PEM thunder_pem_ecam_ops structure so it is visible to MCFG quirk
- code.
-3. New quirk entries for each PEM segment. Each contains platform IDs,
- mentioned thunder_pem_ecam_ops and CFG resources.
-
-Quirk is considered for ThunderX silicon pass2.x only which is identified
-via MCFG revision 1.
-
-ThunderX pass 2.x requires the following accessors:
-
- NUMA Node 0 PCI segments 0- 3: pci_generic_ecam_ops (ECAM-compliant)
- NUMA Node 0 PCI segments 4- 9: thunder_pem_ecam_ops (MCFG quirk)
- NUMA Node 1 PCI segments 10-13: pci_generic_ecam_ops (ECAM-compliant)
- NUMA Node 1 PCI segments 14-19: thunder_pem_ecam_ops (MCFG quirk)
-
-[bhelgaas: adapt to use acpi_get_rc_resources(), update Makefile/ifdefs so
-quirk doesn't depend on CONFIG_PCI_HOST_THUNDER_PEM]
-Signed-off-by: Tomasz Nowicki <tn@semihalf.com>
-Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- drivers/acpi/pci_mcfg.c | 19 +++++++++++++++
- drivers/pci/host/Kconfig | 3 +-
- drivers/pci/host/Makefile | 2 -
- drivers/pci/host/pci-thunder-pem.c | 44 +++++++++++++++++++++++++++++++++++++
- include/linux/pci-ecam.h | 1
- 5 files changed, 67 insertions(+), 2 deletions(-)
-
---- a/drivers/acpi/pci_mcfg.c
-+++ b/drivers/acpi/pci_mcfg.c
-@@ -74,6 +74,25 @@ static struct mcfg_fixup mcfg_quirks[] =
- HISI_QUAD_DOM("HIP07 ", 4, &hisi_pcie_ops),
- HISI_QUAD_DOM("HIP07 ", 8, &hisi_pcie_ops),
- HISI_QUAD_DOM("HIP07 ", 12, &hisi_pcie_ops),
-+
-+#define THUNDER_PEM_RES(addr, node) \
-+ DEFINE_RES_MEM((addr) + ((u64) (node) << 44), 0x39 * SZ_16M)
-+#define THUNDER_PEM_QUIRK(rev, node) \
-+ { "CAVIUM", "THUNDERX", rev, 4 + (10 * (node)), MCFG_BUS_ANY, \
-+ &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x88001f000000UL, node) }, \
-+ { "CAVIUM", "THUNDERX", rev, 5 + (10 * (node)), MCFG_BUS_ANY, \
-+ &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x884057000000UL, node) }, \
-+ { "CAVIUM", "THUNDERX", rev, 6 + (10 * (node)), MCFG_BUS_ANY, \
-+ &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x88808f000000UL, node) }, \
-+ { "CAVIUM", "THUNDERX", rev, 7 + (10 * (node)), MCFG_BUS_ANY, \
-+ &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x89001f000000UL, node) }, \
-+ { "CAVIUM", "THUNDERX", rev, 8 + (10 * (node)), MCFG_BUS_ANY, \
-+ &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x894057000000UL, node) }, \
-+ { "CAVIUM", "THUNDERX", rev, 9 + (10 * (node)), MCFG_BUS_ANY, \
-+ &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x89808f000000UL, node) }
-+ /* SoC pass2.x */
-+ THUNDER_PEM_QUIRK(1, 0),
-+ THUNDER_PEM_QUIRK(1, 1),
- };
-
- static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
---- a/drivers/pci/host/Kconfig
-+++ b/drivers/pci/host/Kconfig
-@@ -240,7 +240,8 @@ config PCIE_QCOM
-
- config PCI_HOST_THUNDER_PEM
- bool "Cavium Thunder PCIe controller to off-chip devices"
-- depends on OF && ARM64
-+ depends on ARM64
-+ depends on OF || (ACPI && PCI_QUIRKS)
- select PCI_HOST_COMMON
- help
- Say Y here if you want PCIe support for CN88XX Cavium Thunder SoCs.
---- a/drivers/pci/host/Makefile
-+++ b/drivers/pci/host/Makefile
-@@ -28,7 +28,7 @@ obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-al
- obj-$(CONFIG_ARM64) += pcie-hisi.o
- obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
- obj-$(CONFIG_PCI_HOST_THUNDER_ECAM) += pci-thunder-ecam.o
--obj-$(CONFIG_PCI_HOST_THUNDER_PEM) += pci-thunder-pem.o
-+obj-$(CONFIG_ARM64) += pci-thunder-pem.o
- obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
- obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
- obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
---- a/drivers/pci/host/pci-thunder-pem.c
-+++ b/drivers/pci/host/pci-thunder-pem.c
-@@ -18,8 +18,12 @@
- #include <linux/init.h>
- #include <linux/of_address.h>
- #include <linux/of_pci.h>
-+#include <linux/pci-acpi.h>
- #include <linux/pci-ecam.h>
- #include <linux/platform_device.h>
-+#include "../pci.h"
-+
-+#if defined(CONFIG_PCI_HOST_THUNDER_PEM) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))
-
- #define PEM_CFG_WR 0x28
- #define PEM_CFG_RD 0x30
-@@ -313,6 +317,43 @@ static int thunder_pem_init(struct devic
- return 0;
- }
-
-+#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
-+
-+static int thunder_pem_acpi_init(struct pci_config_window *cfg)
-+{
-+ struct device *dev = cfg->parent;
-+ struct acpi_device *adev = to_acpi_device(dev);
-+ struct acpi_pci_root *root = acpi_driver_data(adev);
-+ struct resource *res_pem;
-+ int ret;
-+
-+ res_pem = devm_kzalloc(&adev->dev, sizeof(*res_pem), GFP_KERNEL);
-+ if (!res_pem)
-+ return -ENOMEM;
-+
-+ ret = acpi_get_rc_resources(dev, "THRX0002", root->segment, res_pem);
-+ if (ret) {
-+ dev_err(dev, "can't get rc base address\n");
-+ return ret;
-+ }
-+
-+ return thunder_pem_init(dev, cfg, res_pem);
-+}
-+
-+struct pci_ecam_ops thunder_pem_ecam_ops = {
-+ .bus_shift = 24,
-+ .init = thunder_pem_acpi_init,
-+ .pci_ops = {
-+ .map_bus = pci_ecam_map_bus,
-+ .read = thunder_pem_config_read,
-+ .write = thunder_pem_config_write,
-+ }
-+};
-+
-+#endif
-+
-+#ifdef CONFIG_PCI_HOST_THUNDER_PEM
-+
- static int thunder_pem_platform_init(struct pci_config_window *cfg)
- {
- struct device *dev = cfg->parent;
-@@ -364,3 +405,6 @@ static struct platform_driver thunder_pe
- .probe = thunder_pem_probe,
- };
- builtin_platform_driver(thunder_pem_driver);
-+
-+#endif
-+#endif
---- a/include/linux/pci-ecam.h
-+++ b/include/linux/pci-ecam.h
-@@ -62,6 +62,7 @@ extern struct pci_ecam_ops pci_generic_e
- #if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
- extern struct pci_ecam_ops pci_32b_ops; /* 32-bit accesses only */
- extern struct pci_ecam_ops hisi_pcie_ops; /* HiSilicon */
-+extern struct pci_ecam_ops thunder_pem_ecam_ops; /* Cavium ThunderX 2.x */
- #endif
-
- #ifdef CONFIG_PCI_HOST_GENERIC
+++ /dev/null
-From foo@baz Mon Apr 10 17:43:56 CEST 2017
-From: alexander.levin@verizon.com
-Date: Tue, 4 Apr 2017 19:32:11 +0000
-Subject: PCI: Add MCFG quirks for HiSilicon Hip05/06/07 host controllers
-To: "gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>
-Cc: "stable@vger.kernel.org" <stable@vger.kernel.org>
-Message-ID: <20170404193158.19041-25-alexander.levin@verizon.com>
-
-From: Dongdong Liu <liudongdong3@huawei.com>
-
-[ Upstream commit 5f00f1a0178cf52928366a5e1f376a65f1f3f389 ]
-
-The PCIe controller in Hip05/Hip06/Hip07 SoCs is not completely
-ECAM-compliant. It is non-ECAM only for the RC bus config space; for any
-other bus underneath the root bus it does support ECAM access.
-
-Add specific quirks for PCI config space accessors. This involves:
-1. New initialization call hisi_pcie_init() to obtain RC base
-addresses from PNP0C02 at the root of the ACPI namespace (under \_SB).
-2. New entry in common quirk array.
-
-[bhelgaas: move to pcie-hisi.c and change Makefile/ifdefs so quirk doesn't
-depend on CONFIG_PCI_HISI]
-Signed-off-by: Dongdong Liu <liudongdong3@huawei.com>
-Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
-Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- drivers/acpi/pci_mcfg.c | 12 +++++
- drivers/pci/host/Makefile | 2
- drivers/pci/host/pcie-hisi.c | 101 +++++++++++++++++++++++++++++++++++++++++++
- include/linux/pci-ecam.h | 1
- 4 files changed, 115 insertions(+), 1 deletion(-)
-
---- a/drivers/acpi/pci_mcfg.c
-+++ b/drivers/acpi/pci_mcfg.c
-@@ -62,6 +62,18 @@ static struct mcfg_fixup mcfg_quirks[] =
- QCOM_ECAM32(5),
- QCOM_ECAM32(6),
- QCOM_ECAM32(7),
-+
-+#define HISI_QUAD_DOM(table_id, seg, ops) \
-+ { "HISI ", table_id, 0, (seg) + 0, MCFG_BUS_ANY, ops }, \
-+ { "HISI ", table_id, 0, (seg) + 1, MCFG_BUS_ANY, ops }, \
-+ { "HISI ", table_id, 0, (seg) + 2, MCFG_BUS_ANY, ops }, \
-+ { "HISI ", table_id, 0, (seg) + 3, MCFG_BUS_ANY, ops }
-+ HISI_QUAD_DOM("HIP05 ", 0, &hisi_pcie_ops),
-+ HISI_QUAD_DOM("HIP06 ", 0, &hisi_pcie_ops),
-+ HISI_QUAD_DOM("HIP07 ", 0, &hisi_pcie_ops),
-+ HISI_QUAD_DOM("HIP07 ", 4, &hisi_pcie_ops),
-+ HISI_QUAD_DOM("HIP07 ", 8, &hisi_pcie_ops),
-+ HISI_QUAD_DOM("HIP07 ", 12, &hisi_pcie_ops),
- };
-
- static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
---- a/drivers/pci/host/Makefile
-+++ b/drivers/pci/host/Makefile
-@@ -25,7 +25,7 @@ obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pci
- obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
- obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
- obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
--obj-$(CONFIG_PCI_HISI) += pcie-hisi.o
-+obj-$(CONFIG_ARM64) += pcie-hisi.o
- obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
- obj-$(CONFIG_PCI_HOST_THUNDER_ECAM) += pci-thunder-ecam.o
- obj-$(CONFIG_PCI_HOST_THUNDER_PEM) += pci-thunder-pem.o
---- a/drivers/pci/host/pcie-hisi.c
-+++ b/drivers/pci/host/pcie-hisi.c
-@@ -18,7 +18,106 @@
- #include <linux/of_pci.h>
- #include <linux/platform_device.h>
- #include <linux/of_device.h>
-+#include <linux/pci.h>
-+#include <linux/pci-acpi.h>
-+#include <linux/pci-ecam.h>
- #include <linux/regmap.h>
-+#include "../pci.h"
-+
-+#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
-+
-+static int hisi_pcie_acpi_rd_conf(struct pci_bus *bus, u32 devfn, int where,
-+ int size, u32 *val)
-+{
-+ struct pci_config_window *cfg = bus->sysdata;
-+ int dev = PCI_SLOT(devfn);
-+
-+ if (bus->number == cfg->busr.start) {
-+ /* access only one slot on each root port */
-+ if (dev > 0)
-+ return PCIBIOS_DEVICE_NOT_FOUND;
-+ else
-+ return pci_generic_config_read32(bus, devfn, where,
-+ size, val);
-+ }
-+
-+ return pci_generic_config_read(bus, devfn, where, size, val);
-+}
-+
-+static int hisi_pcie_acpi_wr_conf(struct pci_bus *bus, u32 devfn,
-+ int where, int size, u32 val)
-+{
-+ struct pci_config_window *cfg = bus->sysdata;
-+ int dev = PCI_SLOT(devfn);
-+
-+ if (bus->number == cfg->busr.start) {
-+ /* access only one slot on each root port */
-+ if (dev > 0)
-+ return PCIBIOS_DEVICE_NOT_FOUND;
-+ else
-+ return pci_generic_config_write32(bus, devfn, where,
-+ size, val);
-+ }
-+
-+ return pci_generic_config_write(bus, devfn, where, size, val);
-+}
-+
-+static void __iomem *hisi_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
-+ int where)
-+{
-+ struct pci_config_window *cfg = bus->sysdata;
-+ void __iomem *reg_base = cfg->priv;
-+
-+ if (bus->number == cfg->busr.start)
-+ return reg_base + where;
-+ else
-+ return pci_ecam_map_bus(bus, devfn, where);
-+}
-+
-+static int hisi_pcie_init(struct pci_config_window *cfg)
-+{
-+ struct device *dev = cfg->parent;
-+ struct acpi_device *adev = to_acpi_device(dev);
-+ struct acpi_pci_root *root = acpi_driver_data(adev);
-+ struct resource *res;
-+ void __iomem *reg_base;
-+ int ret;
-+
-+ /*
-+ * Retrieve RC base and size from a HISI0081 device with _UID
-+ * matching our segment.
-+ */
-+ res = devm_kzalloc(dev, sizeof(*res), GFP_KERNEL);
-+ if (!res)
-+ return -ENOMEM;
-+
-+ ret = acpi_get_rc_resources(dev, "HISI0081", root->segment, res);
-+ if (ret) {
-+ dev_err(dev, "can't get rc base address\n");
-+ return -ENOMEM;
-+ }
-+
-+ reg_base = devm_ioremap(dev, res->start, resource_size(res));
-+ if (!reg_base)
-+ return -ENOMEM;
-+
-+ cfg->priv = reg_base;
-+ return 0;
-+}
-+
-+struct pci_ecam_ops hisi_pcie_ops = {
-+ .bus_shift = 20,
-+ .init = hisi_pcie_init,
-+ .pci_ops = {
-+ .map_bus = hisi_pcie_map_bus,
-+ .read = hisi_pcie_acpi_rd_conf,
-+ .write = hisi_pcie_acpi_wr_conf,
-+ }
-+};
-+
-+#endif
-+
-+#ifdef CONFIG_PCI_HISI
-
- #include "pcie-designware.h"
-
-@@ -227,3 +326,5 @@ static struct platform_driver hisi_pcie_
- },
- };
- builtin_platform_driver(hisi_pcie_driver);
-+
-+#endif
---- a/include/linux/pci-ecam.h
-+++ b/include/linux/pci-ecam.h
-@@ -61,6 +61,7 @@ extern struct pci_ecam_ops pci_generic_e
-
- #if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
- extern struct pci_ecam_ops pci_32b_ops; /* 32-bit accesses only */
-+extern struct pci_ecam_ops hisi_pcie_ops; /* HiSilicon */
- #endif
-
- #ifdef CONFIG_PCI_HOST_GENERIC
+++ /dev/null
-From foo@baz Mon Apr 10 17:43:56 CEST 2017
-From: alexander.levin@verizon.com
-Date: Tue, 4 Apr 2017 19:32:10 +0000
-Subject: PCI: Add MCFG quirks for Qualcomm QDF2432 host controller
-To: "gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>
-Cc: "stable@vger.kernel.org" <stable@vger.kernel.org>
-Message-ID: <20170404193158.19041-24-alexander.levin@verizon.com>
-
-From: Christopher Covington <cov@codeaurora.org>
-
-[ Upstream commit 2ca5b8ddc6f70d77a51851ba5e5cd0d39c27dd88 ]
-
-The Qualcomm Technologies QDF2432 SoC does not support accesses smaller
-than 32 bits to the PCI configuration space. Register the appropriate
-quirk.
-
-[bhelgaas: add QCOM_ECAM32 macro, ifdef for ACPI and PCI_QUIRKS]
-Signed-off-by: Christopher Covington <cov@codeaurora.org>
-Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- drivers/acpi/pci_mcfg.c | 11 +++++++++++
- drivers/pci/ecam.c | 12 ++++++++++++
- include/linux/pci-ecam.h | 4 ++++
- 3 files changed, 27 insertions(+)
-
---- a/drivers/acpi/pci_mcfg.c
-+++ b/drivers/acpi/pci_mcfg.c
-@@ -51,6 +51,17 @@ struct mcfg_fixup {
-
- static struct mcfg_fixup mcfg_quirks[] = {
- /* { OEM_ID, OEM_TABLE_ID, REV, SEGMENT, BUS_RANGE, ops, cfgres }, */
-+
-+#define QCOM_ECAM32(seg) \
-+ { "QCOM ", "QDF2432 ", 1, seg, MCFG_BUS_ANY, &pci_32b_ops }
-+ QCOM_ECAM32(0),
-+ QCOM_ECAM32(1),
-+ QCOM_ECAM32(2),
-+ QCOM_ECAM32(3),
-+ QCOM_ECAM32(4),
-+ QCOM_ECAM32(5),
-+ QCOM_ECAM32(6),
-+ QCOM_ECAM32(7),
- };
-
- static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
---- a/drivers/pci/ecam.c
-+++ b/drivers/pci/ecam.c
-@@ -162,3 +162,15 @@ struct pci_ecam_ops pci_generic_ecam_ops
- .write = pci_generic_config_write,
- }
- };
-+
-+#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
-+/* ECAM ops for 32-bit access only (non-compliant) */
-+struct pci_ecam_ops pci_32b_ops = {
-+ .bus_shift = 20,
-+ .pci_ops = {
-+ .map_bus = pci_ecam_map_bus,
-+ .read = pci_generic_config_read32,
-+ .write = pci_generic_config_write32,
-+ }
-+};
-+#endif
---- a/include/linux/pci-ecam.h
-+++ b/include/linux/pci-ecam.h
-@@ -59,6 +59,10 @@ void __iomem *pci_ecam_map_bus(struct pc
- /* default ECAM ops */
- extern struct pci_ecam_ops pci_generic_ecam_ops;
-
-+#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
-+extern struct pci_ecam_ops pci_32b_ops; /* 32-bit accesses only */
-+#endif
-+
- #ifdef CONFIG_PCI_HOST_GENERIC
- /* for DT-based PCI controllers that support ECAM */
- int pci_host_common_probe(struct platform_device *pdev,
+++ /dev/null
-From foo@baz Mon Apr 10 17:43:56 CEST 2017
-From: alexander.levin@verizon.com
-Date: Tue, 4 Apr 2017 19:32:12 +0000
-Subject: PCI: Add MCFG quirks for X-Gene host controller
-To: "gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>
-Cc: "stable@vger.kernel.org" <stable@vger.kernel.org>
-Message-ID: <20170404193158.19041-29-alexander.levin@verizon.com>
-
-From: Duc Dang <dhdang@apm.com>
-
-[ Upstream commit c5d4603961009c39de94725213d8b5420f110f9e ]
-
-PCIe controllers in X-Gene SoCs are not ECAM compliant: software needs to
-configure additional controller's register to address device at
-bus:dev:function.
-
-Add a quirk to discover controller MMIO register space and configure
-controller registers to select and address the target secondary device.
-
-The quirk will only be applied for X-Gene PCIe MCFG table with
-OEM revison 1, 2, 3 or 4 (PCIe controller v1 and v2 on X-Gene SoCs).
-
-Tested-by: Jon Masters <jcm@redhat.com>
-Signed-off-by: Duc Dang <dhdang@apm.com>
-Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- drivers/acpi/pci_mcfg.c | 25 ++++++++
- drivers/pci/host/Kconfig | 4 -
- drivers/pci/host/Makefile | 2
- drivers/pci/host/pci-xgene.c | 126 ++++++++++++++++++++++++++++++++++++++++---
- include/linux/pci-ecam.h | 2
- 5 files changed, 149 insertions(+), 10 deletions(-)
-
---- a/drivers/acpi/pci_mcfg.c
-+++ b/drivers/acpi/pci_mcfg.c
-@@ -108,6 +108,31 @@ static struct mcfg_fixup mcfg_quirks[] =
- THUNDER_ECAM_QUIRK(2, 11),
- THUNDER_ECAM_QUIRK(2, 12),
- THUNDER_ECAM_QUIRK(2, 13),
-+
-+#define XGENE_V1_ECAM_MCFG(rev, seg) \
-+ {"APM ", "XGENE ", rev, seg, MCFG_BUS_ANY, \
-+ &xgene_v1_pcie_ecam_ops }
-+#define XGENE_V2_ECAM_MCFG(rev, seg) \
-+ {"APM ", "XGENE ", rev, seg, MCFG_BUS_ANY, \
-+ &xgene_v2_pcie_ecam_ops }
-+ /* X-Gene SoC with v1 PCIe controller */
-+ XGENE_V1_ECAM_MCFG(1, 0),
-+ XGENE_V1_ECAM_MCFG(1, 1),
-+ XGENE_V1_ECAM_MCFG(1, 2),
-+ XGENE_V1_ECAM_MCFG(1, 3),
-+ XGENE_V1_ECAM_MCFG(1, 4),
-+ XGENE_V1_ECAM_MCFG(2, 0),
-+ XGENE_V1_ECAM_MCFG(2, 1),
-+ XGENE_V1_ECAM_MCFG(2, 2),
-+ XGENE_V1_ECAM_MCFG(2, 3),
-+ XGENE_V1_ECAM_MCFG(2, 4),
-+ /* X-Gene SoC with v2.1 PCIe controller */
-+ XGENE_V2_ECAM_MCFG(3, 0),
-+ XGENE_V2_ECAM_MCFG(3, 1),
-+ /* X-Gene SoC with v2.2 PCIe controller */
-+ XGENE_V2_ECAM_MCFG(4, 0),
-+ XGENE_V2_ECAM_MCFG(4, 1),
-+ XGENE_V2_ECAM_MCFG(4, 2),
- };
-
- static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
---- a/drivers/pci/host/Kconfig
-+++ b/drivers/pci/host/Kconfig
-@@ -133,8 +133,8 @@ config PCIE_XILINX
-
- config PCI_XGENE
- bool "X-Gene PCIe controller"
-- depends on ARCH_XGENE
-- depends on OF
-+ depends on ARM64
-+ depends on OF || (ACPI && PCI_QUIRKS)
- select PCIEPORTBUS
- help
- Say Y here if you want internal PCI support on APM X-Gene SoC.
---- a/drivers/pci/host/Makefile
-+++ b/drivers/pci/host/Makefile
-@@ -15,7 +15,7 @@ obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spe
- obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone-dw.o pci-keystone.o
- obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o
- obj-$(CONFIG_PCIE_XILINX_NWL) += pcie-xilinx-nwl.o
--obj-$(CONFIG_PCI_XGENE) += pci-xgene.o
-+obj-$(CONFIG_ARM64) += pci-xgene.o
- obj-$(CONFIG_PCI_XGENE_MSI) += pci-xgene-msi.o
- obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
- obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o
---- a/drivers/pci/host/pci-xgene.c
-+++ b/drivers/pci/host/pci-xgene.c
-@@ -27,6 +27,8 @@
- #include <linux/of_irq.h>
- #include <linux/of_pci.h>
- #include <linux/pci.h>
-+#include <linux/pci-acpi.h>
-+#include <linux/pci-ecam.h>
- #include <linux/platform_device.h>
- #include <linux/slab.h>
-
-@@ -64,7 +66,9 @@
- /* PCIe IP version */
- #define XGENE_PCIE_IP_VER_UNKN 0
- #define XGENE_PCIE_IP_VER_1 1
-+#define XGENE_PCIE_IP_VER_2 2
-
-+#if defined(CONFIG_PCI_XGENE) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))
- struct xgene_pcie_port {
- struct device_node *node;
- struct device *dev;
-@@ -91,13 +95,24 @@ static inline u32 pcie_bar_low_val(u32 a
- return (addr & PCI_BASE_ADDRESS_MEM_MASK) | flags;
- }
-
-+static inline struct xgene_pcie_port *pcie_bus_to_port(struct pci_bus *bus)
-+{
-+ struct pci_config_window *cfg;
-+
-+ if (acpi_disabled)
-+ return (struct xgene_pcie_port *)(bus->sysdata);
-+
-+ cfg = bus->sysdata;
-+ return (struct xgene_pcie_port *)(cfg->priv);
-+}
-+
- /*
- * When the address bit [17:16] is 2'b01, the Configuration access will be
- * treated as Type 1 and it will be forwarded to external PCIe device.
- */
- static void __iomem *xgene_pcie_get_cfg_base(struct pci_bus *bus)
- {
-- struct xgene_pcie_port *port = bus->sysdata;
-+ struct xgene_pcie_port *port = pcie_bus_to_port(bus);
-
- if (bus->number >= (bus->primary + 1))
- return port->cfg_base + AXI_EP_CFG_ACCESS;
-@@ -111,7 +126,7 @@ static void __iomem *xgene_pcie_get_cfg_
- */
- static void xgene_pcie_set_rtdid_reg(struct pci_bus *bus, uint devfn)
- {
-- struct xgene_pcie_port *port = bus->sysdata;
-+ struct xgene_pcie_port *port = pcie_bus_to_port(bus);
- unsigned int b, d, f;
- u32 rtdid_val = 0;
-
-@@ -158,7 +173,7 @@ static void __iomem *xgene_pcie_map_bus(
- static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn,
- int where, int size, u32 *val)
- {
-- struct xgene_pcie_port *port = bus->sysdata;
-+ struct xgene_pcie_port *port = pcie_bus_to_port(bus);
-
- if (pci_generic_config_read32(bus, devfn, where & ~0x3, 4, val) !=
- PCIBIOS_SUCCESSFUL)
-@@ -182,13 +197,103 @@ static int xgene_pcie_config_read32(stru
-
- return PCIBIOS_SUCCESSFUL;
- }
-+#endif
-
--static struct pci_ops xgene_pcie_ops = {
-- .map_bus = xgene_pcie_map_bus,
-- .read = xgene_pcie_config_read32,
-- .write = pci_generic_config_write32,
-+#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
-+static int xgene_get_csr_resource(struct acpi_device *adev,
-+ struct resource *res)
-+{
-+ struct device *dev = &adev->dev;
-+ struct resource_entry *entry;
-+ struct list_head list;
-+ unsigned long flags;
-+ int ret;
-+
-+ INIT_LIST_HEAD(&list);
-+ flags = IORESOURCE_MEM;
-+ ret = acpi_dev_get_resources(adev, &list,
-+ acpi_dev_filter_resource_type_cb,
-+ (void *) flags);
-+ if (ret < 0) {
-+ dev_err(dev, "failed to parse _CRS method, error code %d\n",
-+ ret);
-+ return ret;
-+ }
-+
-+ if (ret == 0) {
-+ dev_err(dev, "no IO and memory resources present in _CRS\n");
-+ return -EINVAL;
-+ }
-+
-+ entry = list_first_entry(&list, struct resource_entry, node);
-+ *res = *entry->res;
-+ acpi_dev_free_resource_list(&list);
-+ return 0;
-+}
-+
-+static int xgene_pcie_ecam_init(struct pci_config_window *cfg, u32 ipversion)
-+{
-+ struct device *dev = cfg->parent;
-+ struct acpi_device *adev = to_acpi_device(dev);
-+ struct xgene_pcie_port *port;
-+ struct resource csr;
-+ int ret;
-+
-+ port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
-+ if (!port)
-+ return -ENOMEM;
-+
-+ ret = xgene_get_csr_resource(adev, &csr);
-+ if (ret) {
-+ dev_err(dev, "can't get CSR resource\n");
-+ kfree(port);
-+ return ret;
-+ }
-+ port->csr_base = devm_ioremap_resource(dev, &csr);
-+ if (IS_ERR(port->csr_base)) {
-+ kfree(port);
-+ return -ENOMEM;
-+ }
-+
-+ port->cfg_base = cfg->win;
-+ port->version = ipversion;
-+
-+ cfg->priv = port;
-+ return 0;
-+}
-+
-+static int xgene_v1_pcie_ecam_init(struct pci_config_window *cfg)
-+{
-+ return xgene_pcie_ecam_init(cfg, XGENE_PCIE_IP_VER_1);
-+}
-+
-+struct pci_ecam_ops xgene_v1_pcie_ecam_ops = {
-+ .bus_shift = 16,
-+ .init = xgene_v1_pcie_ecam_init,
-+ .pci_ops = {
-+ .map_bus = xgene_pcie_map_bus,
-+ .read = xgene_pcie_config_read32,
-+ .write = pci_generic_config_write,
-+ }
-+};
-+
-+static int xgene_v2_pcie_ecam_init(struct pci_config_window *cfg)
-+{
-+ return xgene_pcie_ecam_init(cfg, XGENE_PCIE_IP_VER_2);
-+}
-+
-+struct pci_ecam_ops xgene_v2_pcie_ecam_ops = {
-+ .bus_shift = 16,
-+ .init = xgene_v2_pcie_ecam_init,
-+ .pci_ops = {
-+ .map_bus = xgene_pcie_map_bus,
-+ .read = xgene_pcie_config_read32,
-+ .write = pci_generic_config_write,
-+ }
- };
-+#endif
-
-+#if defined(CONFIG_PCI_XGENE)
- static u64 xgene_pcie_set_ib_mask(struct xgene_pcie_port *port, u32 addr,
- u32 flags, u64 size)
- {
-@@ -521,6 +626,12 @@ static int xgene_pcie_setup(struct xgene
- return 0;
- }
-
-+static struct pci_ops xgene_pcie_ops = {
-+ .map_bus = xgene_pcie_map_bus,
-+ .read = xgene_pcie_config_read32,
-+ .write = pci_generic_config_write32,
-+};
-+
- static int xgene_pcie_probe_bridge(struct platform_device *pdev)
- {
- struct device *dev = &pdev->dev;
-@@ -591,3 +702,4 @@ static struct platform_driver xgene_pcie
- .probe = xgene_pcie_probe_bridge,
- };
- builtin_platform_driver(xgene_pcie_driver);
-+#endif
---- a/include/linux/pci-ecam.h
-+++ b/include/linux/pci-ecam.h
-@@ -64,6 +64,8 @@ extern struct pci_ecam_ops pci_32b_ops;
- extern struct pci_ecam_ops hisi_pcie_ops; /* HiSilicon */
- extern struct pci_ecam_ops thunder_pem_ecam_ops; /* Cavium ThunderX 1.x & 2.x */
- extern struct pci_ecam_ops pci_thunder_ecam_ops; /* Cavium ThunderX 1.x */
-+extern struct pci_ecam_ops xgene_v1_pcie_ecam_ops; /* APM X-Gene PCIe v1 */
-+extern struct pci_ecam_ops xgene_v2_pcie_ecam_ops; /* APM X-Gene PCIe v2.x */
- #endif
-
- #ifdef CONFIG_PCI_HOST_GENERIC
+++ /dev/null
-From foo@baz Mon Apr 10 17:43:56 CEST 2017
-From: alexander.levin@verizon.com
-Date: Tue, 4 Apr 2017 19:32:13 +0000
-Subject: PCI: Explain ARM64 ACPI/MCFG quirk Kconfig and build strategy
-To: "gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>
-Cc: "stable@vger.kernel.org" <stable@vger.kernel.org>
-Message-ID: <20170404193158.19041-30-alexander.levin@verizon.com>
-
-From: Bjorn Helgaas <bhelgaas@google.com>
-
-[ Upstream commit ca5ab37b19dfd1d77787d0474b767ec1185670f4 ]
-
-Add Makefile comments to explain the Kconfig and build strategy for ARM64
-drivers that work around not-quite-ECAM issues. No functional change
-intended.
-
-Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- drivers/pci/host/Makefile | 19 +++++++++++++++----
- 1 file changed, 15 insertions(+), 4 deletions(-)
-
---- a/drivers/pci/host/Makefile
-+++ b/drivers/pci/host/Makefile
-@@ -15,7 +15,6 @@ obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spe
- obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone-dw.o pci-keystone.o
- obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o
- obj-$(CONFIG_PCIE_XILINX_NWL) += pcie-xilinx-nwl.o
--obj-$(CONFIG_ARM64) += pci-xgene.o
- obj-$(CONFIG_PCI_XGENE_MSI) += pci-xgene-msi.o
- obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
- obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o
-@@ -25,11 +24,23 @@ obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pci
- obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
- obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
- obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
--obj-$(CONFIG_ARM64) += pcie-hisi.o
- obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
--obj-$(CONFIG_ARM64) += pci-thunder-ecam.o
--obj-$(CONFIG_ARM64) += pci-thunder-pem.o
- obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
- obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
- obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
- obj-$(CONFIG_VMD) += vmd.o
-+
-+# The following drivers are for devices that use the generic ACPI
-+# pci_root.c driver but don't support standard ECAM config access.
-+# They contain MCFG quirks to replace the generic ECAM accessors with
-+# device-specific ones that are shared with the DT driver.
-+
-+# The ACPI driver is generic and should not require driver-specific
-+# config options to be enabled, so we always build these drivers on
-+# ARM64 and use internal ifdefs to only build the pieces we need
-+# depending on whether ACPI, the DT driver, or both are enabled.
-+
-+obj-$(CONFIG_ARM64) += pcie-hisi.o
-+obj-$(CONFIG_ARM64) += pci-thunder-ecam.o
-+obj-$(CONFIG_ARM64) += pci-thunder-pem.o
-+obj-$(CONFIG_ARM64) += pci-xgene.o
+++ /dev/null
-From foo@baz Mon Apr 10 17:43:56 CEST 2017
-From: alexander.levin@verizon.com
-Date: Tue, 4 Apr 2017 19:32:26 +0000
-Subject: PCI: xgene: Fix double free on init error
-To: "gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>
-Cc: "stable@vger.kernel.org" <stable@vger.kernel.org>
-Message-ID: <20170404193158.19041-66-alexander.levin@verizon.com>
-
-From: Dan Carpenter <dan.carpenter@oracle.com>
-
-[ Upstream commit 1ded56df3247d358390ae6dc09ccee620262ac5f ]
-
-The "port" variable was allocated with devm_kzalloc() so if we free it with
-kfree() it will be freed twice. Also I changed it to propogate the error
-from devm_ioremap_resource() instead of returning -ENOMEM.
-
-Fixes: c5d460396100 ("PCI: Add MCFG quirks for X-Gene host controller")
-Also-posted-by: Shawn Lin <shawn.lin@rock-chips.com>
-Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
-Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-Acked-by: Tanmay Inamdar <tinamdar@apm.com>
-Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- drivers/pci/host/pci-xgene.c | 7 ++-----
- 1 file changed, 2 insertions(+), 5 deletions(-)
-
---- a/drivers/pci/host/pci-xgene.c
-+++ b/drivers/pci/host/pci-xgene.c
-@@ -246,14 +246,11 @@ static int xgene_pcie_ecam_init(struct p
- ret = xgene_get_csr_resource(adev, &csr);
- if (ret) {
- dev_err(dev, "can't get CSR resource\n");
-- kfree(port);
- return ret;
- }
- port->csr_base = devm_ioremap_resource(dev, &csr);
-- if (IS_ERR(port->csr_base)) {
-- kfree(port);
-- return -ENOMEM;
-- }
-+ if (IS_ERR(port->csr_base))
-+ return PTR_ERR(port->csr_base);
-
- port->cfg_base = cfg->win;
- port->version = ipversion;
+++ /dev/null
-From foo@baz Mon Apr 10 17:43:56 CEST 2017
-From: alexander.levin@verizon.com
-Date: Tue, 4 Apr 2017 19:32:26 +0000
-Subject: [media] rx51: broken build
-To: "gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>
-Cc: "stable@vger.kernel.org" <stable@vger.kernel.org>
-Message-ID: <20170404193158.19041-67-alexander.levin@verizon.com>
-
-From: Sean Young <sean@mess.org>
-
-[ Upstream commit 922ee72da7c739157ed02ea04a5c100d19f67226 ]
-
-As reported by kernel build test:
-
- In file included from arch/arm/mach-omap2/pdata-quirks.c:15:0:
->> arch/arm/mach-omap2/pdata-quirks.c:536:49: error: 'rx51_lirc_data' undeclared here (not in a function)
- OF_DEV_AUXDATA("nokia,n900-ir", 0, "n900-ir", &rx51_lirc_data),
- ^
- include/linux/of_platform.h:52:21: note: in definition of macro 'OF_DEV_AUXDATA'
- .platform_data = _pdata }
- ^~~~~~
-
-Since "a92def1 [media] ir-rx51: port to rc-core" the build fails on
-some arm configurations.
-
-Reported-by: kbuild test robot <fengguang.wu@intel.com>
-Signed-off-by: Sean Young <sean@mess.org>
-Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
-Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- arch/arm/mach-omap2/pdata-quirks.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm/mach-omap2/pdata-quirks.c
-+++ b/arch/arm/mach-omap2/pdata-quirks.c
-@@ -534,7 +534,7 @@ static struct of_dev_auxdata omap_auxdat
- &omap3_iommu_pdata),
- OF_DEV_AUXDATA("ti,omap3-hsmmc", 0x4809c000, "4809c000.mmc", &mmc_pdata[0]),
- OF_DEV_AUXDATA("ti,omap3-hsmmc", 0x480b4000, "480b4000.mmc", &mmc_pdata[1]),
-- OF_DEV_AUXDATA("nokia,n900-ir", 0, "n900-ir", &rx51_lirc_data),
-+ OF_DEV_AUXDATA("nokia,n900-ir", 0, "n900-ir", &rx51_ir_data),
- /* Only on am3517 */
- OF_DEV_AUXDATA("ti,davinci_mdio", 0x5c030000, "davinci_mdio.0", NULL),
- OF_DEV_AUXDATA("ti,am3517-emac", 0x5c000000, "davinci_emac.0",
x86-intel_idle-add-cpu-model-0x4a-atom-z34xx-series.patch
arm64-pci-manage-controller-specific-data-on-per-controller-basis.patch
arm64-pci-add-local-struct-device-pointers.patch
-arm64-pci-search-acpi-namespace-to-ensure-ecam-space-is-reserved.patch
-pci-acpi-extend-pci_mcfg_lookup-to-return-ecam-config-accessors.patch
-pci-acpi-check-for-platform-specific-mcfg-quirks.patch
-pci-add-mcfg-quirks-for-qualcomm-qdf2432-host-controller.patch
-pci-add-mcfg-quirks-for-hisilicon-hip05-06-07-host-controllers.patch
pci-thunder-pem-factor-out-resource-lookup.patch
-pci-add-mcfg-quirks-for-cavium-thunderx-pass2.x-host-controller.patch
-pci-add-mcfg-quirks-for-cavium-thunderx-pass1.x-host-controller.patch
-pci-add-mcfg-quirks-for-x-gene-host-controller.patch
-pci-explain-arm64-acpi-mcfg-quirk-kconfig-and-build-strategy.patch
scsi-ufs-add-quirk-to-increase-host-pa_saveconfigtime.patch
alsa-usb-audio-add-implicit-fb-quirk-for-axe-fx-ii.patch
pci-expand-vpd-access-disabled-quirk-message.patch
asoc-intel-bytcr_rt5640-quirks-for-insyde-devices.patch
scsi-ufs-introduce-a-new-ufshcd_statea-ufshcd_state_eh_scheduled.patch
scsi-ufs-issue-link-starup-2-times-if-device-isn-t-active.patch
-arm-omap2-fix-init-for-multiple-quirks-for-the-same-soc.patch
usb-chipidea-msm-rely-on-core-to-override-ahbburst.patch
serial-8250_omap-add-omap_dma_tx_kick-quirk-for-am437x.patch
input-gpio_keys-add-support-for-gpio-descriptors.patch
drm-mga-remove-device_is_agp-callback.patch
arm-dts-stih407-family-set-snps-dis_u3_susphy_quirk.patch
pci-add-acs-quirk-for-intel-union-point.patch
-pci-xgene-fix-double-free-on-init-error.patch
-rx51-broken-build.patch
sata-ahci-da850-implement-a-workaround-for-the-softreset-quirk.patch
acpi-button-change-default-behavior-to-lid_init_state-open.patch
asoc-rt5670-add-missing-10ec5072-acpi-id.patch
asoc-intel-cht_bsw_rt5645-harden-acpi-device-detection.patch
asoc-intel-cht_bsw_rt5645-add-baytrail-mclk-support.patch
acpi-save-nvs-memory-for-lenovo-g50-45.patch
-usb-musb-da8xx-fix-host-mode-suspend.patch
asoc-sun4i-i2s-add-quirks-to-handle-a31-compatible.patch
hid-wacom-don-t-apply-generic-settings-to-old-devices.patch
arm-kernel-add-smc-structure-parameter.patch
+++ /dev/null
-From foo@baz Mon Apr 10 17:43:56 CEST 2017
-From: alexander.levin@verizon.com
-Date: Tue, 4 Apr 2017 19:32:30 +0000
-Subject: usb: musb: da8xx: Fix host mode suspend
-To: "gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>
-Cc: "stable@vger.kernel.org" <stable@vger.kernel.org>
-Message-ID: <20170404193158.19041-76-alexander.levin@verizon.com>
-
-From: Alexandre Bailon <abailon@baylibre.com>
-
-[ Upstream commit 486fc20ac8391338a42b015801b846acda4db7b7 ]
-
-On da8xx, VBUS is not maintained during suspend when musb is in host mode.
-On resume, all the connected devices will be disconnected and then will
-be enumerated again.
-This happens because MUSB_DEVCTL is cleared during suspend.
-
-Use the quirk MUSB_PRESERVE_SESSION to preseve MUSB_DEVCTL during suspend.
-
-Signed-off-by: Alexandre Bailon <abailon@baylibre.com>
-Signed-off-by: Bin Liu <b-liu@ti.com>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- drivers/usb/musb/da8xx.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/usb/musb/da8xx.c
-+++ b/drivers/usb/musb/da8xx.c
-@@ -434,7 +434,7 @@ static int da8xx_musb_exit(struct musb *
- }
-
- static const struct musb_platform_ops da8xx_ops = {
-- .quirks = MUSB_INDEXED_EP,
-+ .quirks = MUSB_INDEXED_EP | MUSB_PRESERVE_SESSION,
- .init = da8xx_musb_init,
- .exit = da8xx_musb_exit,
-
projects / thirdparty / kernel / stable-queue.git / commitdiff
