KVM: arm64: Support translation faults in inject_host_exception()

Extend inject_host_exception() to support the injection of translation
faults on both the data and instruction side to 32-bit and 64-bit EL0
as well as 64-bit EL1. This will be used in a subsequent patch when
resolving an unhandled host stage-2 abort.

Cc: Fuad Tabba <tabba@google.com>
Reviewed-by: Fuad Tabba <tabba@google.com>
Tested-by: Fuad Tabba <tabba@google.com>
Tested-by: Mostafa Saleh <smostafa@google.com>
Signed-off-by: Will Deacon <will@kernel.org>
Link: https://patch.msgid.link/20260330144841.26181-19-will@kernel.org
Signed-off-by: Marc Zyngier <maz@kernel.org>

diff --git a/arch/arm64/kvm/hyp/include/nvhe/trap_handler.h b/arch/arm64/kvm/hyp/include/nvhe/trap_handler.h
index ba5382c127870b62e44bf74f0655d13a07d339f7..32d7b7746e8e5ea273da1ba1ad2bfec0ee6b573f 100644 (file)
--- a/arch/arm64/kvm/hyp/include/nvhe/trap_handler.h
+++ b/arch/arm64/kvm/hyp/include/nvhe/trap_handler.h
@@ -16,4 +16,6 @@
                                __always_unused int ___check_reg_ ## reg;       \
                                type name = (type)cpu_reg(ctxt, (reg))
 
+void inject_host_exception(u64 esr);
+
 #endif /* __ARM64_KVM_NVHE_TRAP_HANDLER_H__ */

diff --git a/arch/arm64/kvm/hyp/nvhe/hyp-main.c b/arch/arm64/kvm/hyp/nvhe/hyp-main.c
index adfc0bc15398b47893a4c848d00505f022411f37..6db5aebd92dcdf64dda8a0504d3fdaba461c88eb 100644 (file)
--- a/arch/arm64/kvm/hyp/nvhe/hyp-main.c
+++ b/arch/arm64/kvm/hyp/nvhe/hyp-main.c
@@ -705,15 +705,24 @@ static void handle_host_smc(struct kvm_cpu_context *host_ctxt)
        kvm_skip_host_instr();
 }
 
-static void inject_host_exception(u64 esr)
+void inject_host_exception(u64 esr)
 {
        u64 sctlr, spsr_el1, spsr_el2, exc_offset = except_type_sync;
        const u64 spsr_mask = PSR_N_BIT | PSR_Z_BIT | PSR_C_BIT |
                              PSR_V_BIT | PSR_DIT_BIT | PSR_PAN_BIT;
 
-       exc_offset += CURRENT_EL_SP_ELx_VECTOR;
-
        spsr_el1 = spsr_el2 = read_sysreg_el2(SYS_SPSR);
+       switch (spsr_el1 & (PSR_MODE_MASK | PSR_MODE32_BIT)) {
+       case PSR_MODE_EL0t:
+               exc_offset += LOWER_EL_AArch64_VECTOR;
+               break;
+       case PSR_MODE_EL0t | PSR_MODE32_BIT:
+               exc_offset += LOWER_EL_AArch32_VECTOR;
+               break;
+       default:
+               exc_offset += CURRENT_EL_SP_ELx_VECTOR;
+       }
+
        spsr_el2 &= spsr_mask;
        spsr_el2 |= PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT |
                    PSR_MODE_EL1h;
@@ -728,6 +737,9 @@ static void inject_host_exception(u64 esr)
        if (system_supports_mte())
                spsr_el2 |= PSR_TCO_BIT;
 
+       if (esr_fsc_is_translation_fault(esr))
+               write_sysreg_el1(read_sysreg_el2(SYS_FAR), SYS_FAR);
+
        write_sysreg_el1(esr, SYS_ESR);
        write_sysreg_el1(read_sysreg_el2(SYS_ELR), SYS_ELR);
        write_sysreg_el1(spsr_el1, SYS_SPSR);