There is nothing connected to xhci1 in this design, nor in the actual
end devices.
Disable xhci1. Keep the USB PHY enabled, as it is a shared PHY and used
for pcie1.
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
};
&u3phy1 {
+ /* shared between xhci1 and pcie1. */
status = "okay";
};
vbus-supply = <&usb_vbus>;
};
-&xhci1 {
- status = "okay";
-
- phys = <&u2port1 PHY_TYPE_USB2>;
- rx-fifo-depth = <3072>;
- vusb33-supply = <&mt6359_vusb_ldo_reg>;
- vbus-supply = <&usb_vbus>;
- mediatek,u3p-dis-msk = <1>;
-};
-
&xhci2 {
status = "okay";
vbus-supply = <&usb_vbus>;