Use mainline board setup instead of special folder.
Also remove mainline board setup because it is broken
by this commit.
Signed-off-by: Michal Simek <monstr@monstr.eu>
LIB = $(obj)lib$(BOARD).o
-COBJS-y := board.o
+COBJS-y := board.o ../../xilinx/common/xbasic_types.o
+SOBJS := lowlevel_init.o
COBJS := $(sort $(COBJS-y))
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS)
- $(call cmd_link_o_target, $(OBJS))
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
#########################################################################
*/
#include <common.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/nand.h>
#include <netdev.h>
+#include <zynqpl.h>
+
+#define BOOT_MODE_REG (XPSS_SYS_CTRL_BASEADDR + 0x25C)
+#define BOOT_MODES_MASK 0x0000000F
+#define QSPI_MODE (0x00000001) /**< QSPI */
+#define NOR_FLASH_MODE (0x00000002) /**< NOR */
+#define NAND_FLASH_MODE (0x00000004) /**< NAND */
+#define SD_MODE (0x00000005) /**< Secure Digital card */
+#define JTAG_MODE (0x00000000) /**< JTAG */
DECLARE_GLOBAL_DATA_PTR;
+#define dmbp() __asm__ __volatile__ ("dmb" : : : "memory")
+
+void XIo_Out32(u32 OutAddress, u32 Value)
+{
+ *(volatile u32 *) OutAddress = Value;
+ dmbp();
+}
+
+u32 XIo_In32(u32 InAddress)
+{
+ volatile u32 temp = *(volatile u32 *)InAddress;
+ dmbp();
+ return temp;
+}
+
+#ifdef CONFIG_FPGA
+Xilinx_desc fpga = XILINX_XC7Z020_DESC(0);
+#endif
+
int board_init(void)
{
+ /* temporary hack to clear pending irqs before Linux as it
+ will hang Linux */
+
+ XIo_Out32(0xe0001014, 0x26d);
+
+ /* temporary hack to take USB out of reset til the is fixed
+ in Linux */
+
+ XIo_Out32(0xe000a204, 0x80);
+ XIo_Out32(0xe000a208, 0x80);
+ XIo_Out32(0xe000a040, 0x80);
+ XIo_Out32(0xe000a040, 0x00);
+ XIo_Out32(0xe000a040, 0x80);
+
icache_enable();
+#ifdef CONFIG_FPGA
+ fpga_init();
+ fpga_add(fpga_xilinx, &fpga);
+#endif
+
return 0;
}
+int board_late_init (void)
+{
+ u32 boot_mode;
+
+ boot_mode = (XIo_In32(BOOT_MODE_REG) & BOOT_MODES_MASK);
+ switch(boot_mode) {
+ case QSPI_MODE:
+ setenv("modeboot", "run qspiboot");
+ break;
+ case NAND_FLASH_MODE:
+ setenv("modeboot", "run nandboot");
+ break;
+ case NOR_FLASH_MODE:
+ setenv("modeboot", "run norboot");
+ break;
+ case SD_MODE:
+ setenv("modeboot", "run sdboot");
+ break;
+ case JTAG_MODE:
+ setenv("modeboot", "run jtagboot");
+ break;
+ default:
+ setenv("modeboot", "");
+ break;
+ }
+
+ return 0;
+}
#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bis)
{
u32 ret = 0;
-#if defined(CONFIG_ZYNQ_GEM) && defined(CONFIG_ZYNQ_GEM_BASEADDR0)
- ret = zynq_gem_initialize(bis, CONFIG_ZYNQ_GEM_BASEADDR0);
+#ifdef CONFIG_XILINX_AXIEMAC
+ ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR,
+ XILINX_AXIDMA_BASEADDR);
+#endif
+#ifdef CONFIG_XILINX_EMACLITE
+ u32 txpp = 0;
+ u32 rxpp = 0;
+# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
+ txpp = 1;
+# endif
+# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
+ rxpp = 1;
+# endif
+ ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR,
+ txpp, rxpp);
+#endif
+
+#if defined(CONFIG_ZYNQ_GEM)
+# if defined(CONFIG_ZYNQ_GEM_BASEADDR0)
+ ret |= zynq_gem_initialize(bis, CONFIG_ZYNQ_GEM_BASEADDR0);
+# endif
+# if defined(CONFIG_ZYNQ_GEM_BASEADDR1)
+ ret |= zynq_gem_initialize(bis, CONFIG_ZYNQ_GEM_BASEADDR1);
+# endif
+#endif
+
+#ifdef CONFIG_ZYNQ_GEM_OLD
+ ret |= zynq_gem_initialize_old(bis);
#endif
return ret;
}
#endif
+#ifdef CONFIG_CMD_MMC
+int board_mmc_init(bd_t *bd)
+{
+ return zynq_mmc_init(bd);
+}
+#endif
+
+#ifdef CONFIG_CMD_NAND
+int board_nand_init(struct nand_chip *nand_chip)
+{
+ return zynq_nand_init(nand_chip);
+}
+#endif
+
int dram_init(void)
{
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = CONFIG_SYS_SDRAM_SIZE;
return 0;
}
+
+/*
+ * OK, and resets too.
+ */
+void reset_cpu(ulong addr)
+{
+ u32 *slcr_p;
+
+ slcr_p = (u32*)XPSS_SYS_CTRL_BASEADDR;
+
+ /* unlock SLCR */
+ *(slcr_p + 2) = 0xDF0D;
+ /* Clear 0x0F000000 bits of reboot status register to workaround
+ * the FSBL not loading the bitstream after soft reset
+ * This is a temporary solution until we know more.
+ */
+ XIo_Out32(XPSS_SYS_CTRL_BASEADDR + 0x258, (XIo_In32(XPSS_SYS_CTRL_BASEADDR + 0x258) & 0xF0FFFFFF));
+ /* Tickle soft reset bit */
+ *(slcr_p + 128) = 1;
+
+ while(1) {;}
+}
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB = $(obj)lib$(BOARD).o
-
-COBJS-y := board.o ../../xilinx/common/xbasic_types.o
-SOBJS := lowlevel_init.o
-
-COBJS := $(sort $(COBJS-y))
-
-SRCS := $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-/*
- * (C) Copyright 2012 Xilinx
- *
- * Xilinx Zynq common board interface
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/mmc.h>
-#include <asm/arch/nand.h>
-#include <netdev.h>
-#include <zynqpl.h>
-
-#define BOOT_MODE_REG (XPSS_SYS_CTRL_BASEADDR + 0x25C)
-#define BOOT_MODES_MASK 0x0000000F
-#define QSPI_MODE (0x00000001) /**< QSPI */
-#define NOR_FLASH_MODE (0x00000002) /**< NOR */
-#define NAND_FLASH_MODE (0x00000004) /**< NAND */
-#define SD_MODE (0x00000005) /**< Secure Digital card */
-#define JTAG_MODE (0x00000000) /**< JTAG */
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define dmbp() __asm__ __volatile__ ("dmb" : : : "memory")
-
-void XIo_Out32(u32 OutAddress, u32 Value)
-{
- *(volatile u32 *) OutAddress = Value;
- dmbp();
-}
-
-u32 XIo_In32(u32 InAddress)
-{
- volatile u32 temp = *(volatile u32 *)InAddress;
- dmbp();
- return temp;
-}
-
-#ifdef CONFIG_FPGA
-Xilinx_desc fpga = XILINX_XC7Z020_DESC(0);
-#endif
-
-int board_init(void)
-{
- /* temporary hack to clear pending irqs before Linux as it
- will hang Linux */
-
- XIo_Out32(0xe0001014, 0x26d);
-
- /* temporary hack to take USB out of reset til the is fixed
- in Linux */
-
- XIo_Out32(0xe000a204, 0x80);
- XIo_Out32(0xe000a208, 0x80);
- XIo_Out32(0xe000a040, 0x80);
- XIo_Out32(0xe000a040, 0x00);
- XIo_Out32(0xe000a040, 0x80);
-
- icache_enable();
-
-#ifdef CONFIG_FPGA
- fpga_init();
- fpga_add(fpga_xilinx, &fpga);
-#endif
-
- return 0;
-}
-
-int board_late_init (void)
-{
- u32 boot_mode;
-
- boot_mode = (XIo_In32(BOOT_MODE_REG) & BOOT_MODES_MASK);
- switch(boot_mode) {
- case QSPI_MODE:
- setenv("modeboot", "run qspiboot");
- break;
- case NAND_FLASH_MODE:
- setenv("modeboot", "run nandboot");
- break;
- case NOR_FLASH_MODE:
- setenv("modeboot", "run norboot");
- break;
- case SD_MODE:
- setenv("modeboot", "run sdboot");
- break;
- case JTAG_MODE:
- setenv("modeboot", "run jtagboot");
- break;
- default:
- setenv("modeboot", "");
- break;
- }
-
- return 0;
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
- u32 ret = 0;
-
-#ifdef CONFIG_XILINX_AXIEMAC
- ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR,
- XILINX_AXIDMA_BASEADDR);
-#endif
-#ifdef CONFIG_XILINX_EMACLITE
- u32 txpp = 0;
- u32 rxpp = 0;
-# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
- txpp = 1;
-# endif
-# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
- rxpp = 1;
-# endif
- ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR,
- txpp, rxpp);
-#endif
-
-#if defined(CONFIG_ZYNQ_GEM)
-# if defined(CONFIG_ZYNQ_GEM_BASEADDR0)
- ret |= zynq_gem_initialize(bis, CONFIG_ZYNQ_GEM_BASEADDR0);
-# endif
-# if defined(CONFIG_ZYNQ_GEM_BASEADDR1)
- ret |= zynq_gem_initialize(bis, CONFIG_ZYNQ_GEM_BASEADDR1);
-# endif
-#endif
-
-#ifdef CONFIG_ZYNQ_GEM_OLD
- ret |= zynq_gem_initialize_old(bis);
-#endif
-
- return ret;
-}
-#endif
-
-#ifdef CONFIG_CMD_MMC
-int board_mmc_init(bd_t *bd)
-{
- return zynq_mmc_init(bd);
-}
-#endif
-
-#ifdef CONFIG_CMD_NAND
-int board_nand_init(struct nand_chip *nand_chip)
-{
- return zynq_nand_init(nand_chip);
-}
-#endif
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_SYS_SDRAM_SIZE);
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = CONFIG_SYS_SDRAM_SIZE;
-
- return 0;
-}
-
-/*
- * OK, and resets too.
- */
-void reset_cpu(ulong addr)
-{
- u32 *slcr_p;
-
- slcr_p = (u32*)XPSS_SYS_CTRL_BASEADDR;
-
- /* unlock SLCR */
- *(slcr_p + 2) = 0xDF0D;
- /* Clear 0x0F000000 bits of reboot status register to workaround
- * the FSBL not loading the bitstream after soft reset
- * This is a temporary solution until we know more.
- */
- XIo_Out32(XPSS_SYS_CTRL_BASEADDR + 0x258, (XIo_In32(XPSS_SYS_CTRL_BASEADDR + 0x258) & 0xF0FFFFFF));
- /* Tickle soft reset bit */
- *(slcr_p + 128) = 1;
-
- while(1) {;}
-}
twister arm armv7 twister technexion omap3
omap4_panda arm armv7 panda ti omap4
omap4_sdp4430 arm armv7 sdp4430 ti omap4
-zynq_ep107 arm armv7 zynq_common xilinx zynq
-zynq_ep107_dual_qspi arm armv7 zynq_common xilinx zynq zynq_ep107:XILINX_PSS_QSPI_USE_DUAL_FLASH
-zynq_zc770_XM010 arm armv7 zynq_common xilinx zynq zynq_zc770:ZC770_XM010
-zynq_zc770_XM011 arm armv7 zynq_common xilinx zynq zynq_zc770:ZC770_XM011
-zynq_zc770_XM011_n16b arm armv7 zynq_common xilinx zynq zynq_zc770:ZC770_XM011,XILINX_ZYNQ_NAND_BUSWIDTH_16
-zynq_zc770_XM012 arm armv7 zynq_common xilinx zynq zynq_zc770:ZC770_XM012
-zynq_zc770_XM013 arm armv7 zynq_common xilinx zynq zynq_zc770:ZC770_XM013
-zynq_afx_nor arm armv7 zynq_common xilinx zynq zynq_afx:AFX_NOR
-zynq_afx_qspi arm armv7 zynq_common xilinx zynq zynq_afx:AFX_QSPI
-zynq_afx_nand arm armv7 zynq_common xilinx zynq zynq_afx:AFX_NAND
-zynq_afx_nand_16b arm armv7 zynq_common xilinx zynq zynq_afx:AFX_NAND,XILINX_ZYNQ_NAND_BUSWIDTH_16
-zynq_zc70x arm armv7 zynq_common xilinx zynq
-zynq_cseflash arm armv7 zynq_common xilinx zynq
-zynq_zed arm armv7 zynq_common xilinx zynq
+zynq_ep107 arm armv7 zynq xilinx zynq
+zynq_ep107_dual_qspi arm armv7 zynq xilinx zynq zynq_ep107:XILINX_PSS_QSPI_USE_DUAL_FLASH
+zynq_zc770_XM010 arm armv7 zynq xilinx zynq zynq_zc770:ZC770_XM010
+zynq_zc770_XM011 arm armv7 zynq xilinx zynq zynq_zc770:ZC770_XM011
+zynq_zc770_XM011_n16b arm armv7 zynq xilinx zynq zynq_zc770:ZC770_XM011,XILINX_ZYNQ_NAND_BUSWIDTH_16
+zynq_zc770_XM012 arm armv7 zynq xilinx zynq zynq_zc770:ZC770_XM012
+zynq_zc770_XM013 arm armv7 zynq xilinx zynq zynq_zc770:ZC770_XM013
+zynq_afx_nor arm armv7 zynq xilinx zynq zynq_afx:AFX_NOR
+zynq_afx_qspi arm armv7 zynq xilinx zynq zynq_afx:AFX_QSPI
+zynq_afx_nand arm armv7 zynq xilinx zynq zynq_afx:AFX_NAND
+zynq_afx_nand_16b arm armv7 zynq xilinx zynq zynq_afx:AFX_NAND,XILINX_ZYNQ_NAND_BUSWIDTH_16
+zynq_zc70x arm armv7 zynq xilinx zynq
+zynq_cseflash arm armv7 zynq xilinx zynq
+zynq_zed arm armv7 zynq xilinx zynq
omap5_evm arm armv7 omap5_evm ti omap5
s5p_goni arm armv7 goni samsung s5pc1xx
smdkc100 arm armv7 smdkc100 samsung s5pc1xx
snowball arm armv7 snowball st-ericsson u8500
kzm9g arm armv7 kzm9g kmc rmobile
armadillo-800eva arm armv7 armadillo-800eva atmark-techno rmobile
-zynq arm armv7 zynq xilinx zynq
socfpga_cyclone5 arm armv7 socfpga_cyclone5 altera socfpga
actux1_4_16 arm ixp actux1 - - actux1:FLASH2X2
actux1_4_32 arm ixp actux1 - - actux1:FLASH2X2,RAM_32MB
projects / thirdparty / u-boot.git / commitdiff
