arm64: dts: ipq5018: Add CMN PLL node

Add CMN PLL node for enabling output clocks to the networking
hardware blocks on IPQ5018 devices.

The reference clock of CMN PLL is routed from XO to the CMN PLL
through the internal WiFi block.
.XO (48 MHZ) --> WiFi (multiplier/divider)--> 96 MHZ to CMN PLL.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Link: https://lore.kernel.org/r/20250721-ipq5018-cmn-pll-v5-1-4cbf3479af65@outlook.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
index 08bea072cf11d5fb69f3ef3af9e55c834add3a4e..fc1054301c03abb0fe1f0bd66304bc158605b520 100644 (file)
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
@@ -2,12 +2,13 @@
 /*
  * IPQ5018 SoC device tree source
  *
- * Copyright (c) 2023 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023-2025 The Linux Foundation. All rights reserved.
  */
 
 #include <dt-bindings/clock/qcom,apss-ipq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/qcom,gcc-ipq5018.h>
+#include <dt-bindings/clock/qcom,ipq5018-cmn-pll.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/reset/qcom,gcc-ipq5018.h>
 #include <dt-bindings/thermal/thermal.h>
 
@@ -29,6 +30,14 @@
                        #clock-cells = <0>;
                };
 
+               ref_96mhz_clk: ref-96mhz-clk {
+                       compatible = "fixed-factor-clock";
+                       clocks = <&xo_clk>;
+                       #clock-cells = <0>;
+                       clock-div = <1>;
+                       clock-mult = <2>;
+               };
+
                sleep_clk: sleep-clk {
                        compatible = "fixed-clock";
                        #clock-cells = <0>;
@@ -38,6 +47,12 @@
                        compatible = "fixed-clock";
                        #clock-cells = <0>;
                };
+
+               xo_clk: xo-clk {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <48000000>;
+               };
        };
 
        cpus {
@@ -229,6 +244,20 @@
                        status = "disabled";
                };
 
+               cmn_pll: clock-controller@9b000 {
+                       compatible = "qcom,ipq5018-cmn-pll";
+                       reg = <0x0009b000 0x800>;
+                       clocks = <&ref_96mhz_clk>,
+                                <&gcc GCC_CMN_BLK_AHB_CLK>,
+                                <&gcc GCC_CMN_BLK_SYS_CLK>;
+                       clock-names = "ref",
+                                     "ahb",
+                                     "sys";
+                       #clock-cells = <1>;
+                       assigned-clocks = <&cmn_pll IPQ5018_CMN_PLL_CLK>;
+                       assigned-clock-rates-u64 = /bits/ 64 <9600000000>;
+               };
+
                qfprom: qfprom@a0000 {
                        compatible = "qcom,ipq5018-qfprom", "qcom,qfprom";
                        reg = <0x000a0000 0x1000>;